From 33613a85afc4b1481367fbe92a17ee59c240250b Mon Sep 17 00:00:00 2001 From: Sven Eisenhauer Date: Fri, 10 Nov 2023 15:11:48 +0100 Subject: add new repo --- .../SS07/P6/abel_samples.zip_FILES/add1b.abl | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/add1b.abl (limited to 'Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/add1b.abl') diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/add1b.abl b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/add1b.abl new file mode 100644 index 0000000..52e7827 --- /dev/null +++ b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/add1b.abl @@ -0,0 +1,26 @@ +MODULE adder_1bit + +TITLE 'Volladdierer mit Carry' + +DEClARATIONS + Bit_1 pin 15; // I/O 0, input + Bit_2 pin 16; // I/O 1, input + C_in pin 17; // I/O 2, input + + Sum pin 29 istype 'com'; // I/O 12, output kombinatorisch + C_out pin 30 istype 'com'; // I/O 13, output kombinatorisch + + +TRUTH_TABLE ( [Bit_1,Bit_2,C_in] -> [Sum,C_out] ) // Wahrheitstabelle des Volladdierers + + [0 ,0 ,0 ] -> [0 ,0 ]; + [0 ,0 ,1 ] -> [1 ,0 ]; + [0 ,1 ,0 ] -> [1 ,0 ]; + [0 ,1 ,1 ] -> [0 ,1 ]; + [1 ,0 ,0 ] -> [1 ,0 ]; + [1 ,0 ,1 ] -> [0 ,1 ]; + [1 ,1 ,0 ] -> [0 ,1 ]; + [1 ,1 ,1 ] -> [1 ,1 ]; + +END + -- cgit v1.2.3