From 33613a85afc4b1481367fbe92a17ee59c240250b Mon Sep 17 00:00:00 2001
From: Sven Eisenhauer <sven@sven-eisenhauer.net>
Date: Fri, 10 Nov 2023 15:11:48 +0100
Subject: add new repo

---
 .../SS07/P6/abel_samples.zip_FILES/add1b.abl       | 26 ++++++++
 .../SS07/P6/abel_samples.zip_FILES/count4b1.abl    | 25 ++++++++
 .../SS07/P6/abel_samples.zip_FILES/count4b2.abl    | 71 ++++++++++++++++++++++
 3 files changed, 122 insertions(+)
 create mode 100644 Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/add1b.abl
 create mode 100644 Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b1.abl
 create mode 100644 Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b2.abl

(limited to 'Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES')

diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/add1b.abl b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/add1b.abl
new file mode 100644
index 0000000..52e7827
--- /dev/null
+++ b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/add1b.abl	
@@ -0,0 +1,26 @@
+MODULE adder_1bit
+
+TITLE 'Volladdierer mit Carry'
+
+DEClARATIONS
+	Bit_1 	pin 15;  // I/O 0, input
+	Bit_2 	pin 16;  // I/O 1, input
+	C_in  	pin 17;  // I/O 2, input
+
+	Sum	pin 29 istype 'com';  // I/O 12, output kombinatorisch
+	C_out   pin 30 istype 'com';  // I/O 13, output kombinatorisch
+
+
+TRUTH_TABLE ( 	[Bit_1,Bit_2,C_in]	->	[Sum,C_out] ) // Wahrheitstabelle des Volladdierers
+
+		[0    ,0    ,0   ]  	->	[0  ,0    ];
+		[0    ,0    ,1   ]  	->	[1  ,0    ];
+		[0    ,1    ,0   ]  	->	[1  ,0    ];
+		[0    ,1    ,1   ]  	->	[0  ,1    ];
+		[1    ,0    ,0   ]  	->	[1  ,0    ];
+		[1    ,0    ,1   ]  	->	[0  ,1    ];
+		[1    ,1    ,0   ]  	->	[0  ,1    ];
+		[1    ,1    ,1   ]  	->	[1  ,1    ];
+
+END
+
diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b1.abl b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b1.abl
new file mode 100644
index 0000000..257cd94
--- /dev/null
+++ b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b1.abl	
@@ -0,0 +1,25 @@
+MODULE Counter_4_bit
+
+TITLE '0 ... 9, version with equations'
+
+DEClARATIONS
+	clk pin 15;  " I/O 0, Eingang für den Takt
+	rst pin 16;  " I/O 1, Eingang für das Reset Signal
+	ce  pin 17;  " I/O 2, Eingang für das Enable Signal
+	q3,q2,q1,q0 pin 29,30,31,32 istype 'reg'; " I/O 12, 13, 14, 15, Ausgang: Bits des Zählers, 15: 2^0
+	carry pin 44 istype 'reg'; // I/O 23, Ausgang für Carry
+
+" bus definition, vector, register
+	counter = [q3,q2,q1,q0];
+
+EQUATIONS
+	counter.clk = clk;
+	counter.ar  = rst;
+	carry.clk   = clk;
+	when (ce & (counter < 9)) then counter := counter + 1;
+	else when (ce & (counter >= 9)) then {counter := 0; carry := 1;}
+	else counter := counter;
+
+
+END
+
diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b2.abl b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b2.abl
new file mode 100644
index 0000000..545d92b
--- /dev/null
+++ b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b2.abl	
@@ -0,0 +1,71 @@
+MODULE Counter_4_bit
+TITLE '0 ... 9, version with state diagram'
+DEClARATIONS
+	clk pin 15;  " I/O 0, Eingang für den Takt
+	rst pin 16;  " I/O 1, Eingang für das Reset Signal
+	ce  pin 17;  " I/O 2, Eingang für das Enable Signal
+	q3,q2,q1,q0 pin 29,30,31,32 istype 'reg'; " I/O 12, 13, 14, 15, Ausgang: Bits des Zählers, 15: 2^0
+	carry pin 44 istype 'reg'; // I/O 23, Ausgang für Carry
+
+" bus definition, vector, register
+	counter = [q3,q2,q1,q0];
+
+EQUATIONS
+	counter.clk = clk;
+	carry.clk   = clk;
+
+STATE_DIAGRAM counter;
+	State 0:
+		if(!rst & ce) then 1; " Bei Erfüllung der Bedingung erfolgt ein Übergang in State 1
+		else 0;
+	State 1:
+		if (rst) then 0;
+		else if (ce) then 2;
+		else 1;
+	State 2:
+		if (rst) then 0;
+		else if (ce) then 3;
+		else 2;
+	State 3:
+		if (rst) then 0;
+		else if (ce) then 4;
+		else 3;
+	State 4:
+		if (rst) then 0;
+		else if (ce) then 5;
+		else 4;
+	State 5:
+		if (rst) then 0;
+		else if (ce) then 6;
+		else 5;
+	State 6:
+		if (rst) then 0;
+		else if (ce) then 7;
+		else 6;
+	State 7:
+		if (rst) then 0;
+		else if (ce) then 8;
+		else 7;
+	State 8:
+		if (rst) then 0;
+		else if (ce) then 9;
+		else 8;
+	State 9:
+		carry := 1;
+		if (rst) then 0;
+		else if (ce) then 0;
+		else 9;
+	State 10:
+		goto 0;  " es erfolgt ein bedingungsloser Übergang in State 0
+	State 11:
+		goto 0;
+	State 12:
+		goto 0;
+	State 13:
+		goto 0;
+	State 14:
+		goto 0;
+	State 15:
+		goto 0;
+END
+
-- 
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