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2/SS07/P6/abel.ex1-Dateien/abel_002.gif b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex1-Dateien/abel_002.gif new file mode 100644 index 0000000..172aa05 Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex1-Dateien/abel_002.gif differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex1-Dateien/abel_003.gif b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex1-Dateien/abel_003.gif new file mode 100644 index 0000000..c23381c Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex1-Dateien/abel_003.gif differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex1.html b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex1.html new file mode 100644 index 0000000..ec42f09 --- /dev/null +++ b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex1.html @@ -0,0 +1,176 @@ + +Example of a Mealy Machine: string recognizer + + + + + + +

University of Pennsylvania +

+ +

Department of Electrical Engineering
+
+

+ +

Finite State Machine implemented as a Mealy Machine:

+ +

a non-resetting sequence recognizer.
+

+ +

The following state diagram (Fig. 1) describes a finite state machine +with one input X and one output Z. The FSM asserts its output Z when it +recognizes the following input bit sequence: "1011". The machine +will keep checking for the proper bit sequence and does not reset to the +initial state after it has recognized the string. As an example the input +string X= "..1011011..." will cause the output to go high twice: +Z = "..0001001.." . When the machine is in the state S3 the output +will go high after the arrival of a "1" at the input. Thus the +output is associated with the transitions as indicated on the state +diagram.

+ +


+
+
+

+ +

Figure 1: State diagram, describing the sequence detector implemented +as a Mealy machine. The number in italics underneath the states indicate +which part of the sequence the state remembers.
+

+ +

This state diagram can be described in ABEL code given in Listing 1. +The output is described with the "With" +keyword to indicate that the output will change when the input goes to +one.
+

+ +

Listing 1: ABEL source code for the Mealy Machine +implementation of the sequence detector described in Fig. 1
+

+ + + + + +

The ouput is specified with the "With" keyword. The corresponding +simulation is shown in Figure 2.

+ +


+
+
+

+ +

Figure 2: Simulation of the sequence detector for "1011" +described with the state diagram of Fig. 1. (Screen clip from Xilinx XACTstep(TM) +Foundation software)
+

+ +

Notice that the output Z asserts as soon as the input is "1" +when in state S3. Comparing this output with the one obtained for a Moore +machine of the same sequence detector may let a casual observer think +that there is a timing problem as the output seems to asserts already after +the "101" input sequence. However, when one looks at the output +carefully one concludes that the waveform is correct. One has to realize +that the outputs are valid at the end of the state time (just before the +positive clock-edge) while the valid inputs are sampled just before the +positive clock edge as indicated in Figure 3 below. The input sequence +"1011" gives indeed an output sequence of "0001".

+ +

+ +

Figure 3: Output waveform of the Mealy machine (sequence detector +for "1011") with valid inputs and outputs indicated. (Screen +clip from Xilinx XACTstep(TM) Foundation software)

+ +

One notices that there is a glitch in the output after the input sequence +10111010. However this occurs at a moment that the output is not valid +(the output is valid just before the positive clock edge). The valid output +sequence is than 000100000 as expected.

+ +

This example indicates that one has to be very careful with the timing +when using a Mealy machine. Outputs can show glitches and are only valid +at the end of a state time (i.e. just before the the positive clock edge +for a positive edge triggered flip-flop or just before the negative clock +transition for a negative egde triggered flip-flop). On the other hand +a Mealy machine can often be implemented with fewer states that a Moore +machine as can be seen from the Moore example. +An alternative way to prevent glitches and to make the ouput of a Mealy +machine synchronous with the clock, it to use a synchronous Mealy machine. +The implementation of the sequence detector as a synchronous Mealy machine +is given in the next example.
+

+ +

+

Back to ABEL Primer Contents +| To to Common +Mistakes list | Go to the EE +Undergraduate Lab Homepage | Go to Xilinx +Lab Tutorial Homepage | Go to the Foundation +Tutorial page | Go to EE200 +or EE200 Lab +Homepage |

+ +

+

Created by J. Van der Spiegel: November 16, 1997; Updated +by J. Van der Spiegel: Dec. 30, 1997.

+ + + \ No newline at end of file diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex2-Dateien/abel.gif b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex2-Dateien/abel.gif new file mode 100644 index 0000000..136bbc7 Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex2-Dateien/abel.gif differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex2-Dateien/abel_002.gif b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex2-Dateien/abel_002.gif new file mode 100644 index 0000000..9d3ea2c Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex2-Dateien/abel_002.gif differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex2.html b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex2.html new file mode 100644 index 0000000..006cd54 --- /dev/null +++ b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex2.html @@ -0,0 +1,169 @@ + +Finite State Machine (Moore) example: string detector + + + + + + +

University of Pennsylvania +

+ +

Department of Electrical Engineering
+
+

+ +

Finite State Machine implemented as a Moore Machine:

+ +

a non-resetting sequence recognizer.
+

+ +

The following state diagram (Fig. 1) describes a finite state machine +with one input X and one output Z. The FSM asserts its output Z when it +recognizes the following input bit sequence: "1011". The machine +will keep checking for the proper bit sequence and does not reset to the +initial state after it has recognized the string. As an example the input +string X= "..1011011..." will cause the output to go high twice: +Z = "..0001001.." . The output will asserts only when it is in +state S4 (after having seen the sequence 1011). The FSM is thus a Moore +machine.
+
+

+ +

+ +

Figure 1: State diagram, describing the sequence detector implemented +as a Moore machine. The number in italics underneath the states indicate +which part of the sequence the state remembers.
+

+ +

This state diagram can be described in ABEL code given in Listing 1. +The output is described after the STATE Si: statement.
+

+ +

Listing 1: ABEL source code for the Moore machine +implementation of the sequence detector described in Fig. 1
+

+ + + +

The corresponding simulation is shown in Figure 2.

+ +


+
+
+

+ +

Figure 2: Simulation of the sequence detector (for "1011") +described with the state diagram of Fig. 1. (Screen clip from Xilinx XACTstep(TM) +Foundation software)
+

+ +

One notices that the output asserts after the input sequence 1011 as +specified.
+

+ +

+

Back to ABEL Primer Contents +| To to Common +Mistakes list | Go to the EE +Undergraduate Lab Homepage | Go to Xilinx +Lab Tutorial Homepage | Go to the Foundation +Tutorial page | Go to EE200 +or EE200 Lab +Homepage |

+ +

+

Created by J. Van der Spiegel: November 16, 1997. Updated +by J. Van der Spiegel, Nov. 19, 1997.
+

+ + + \ No newline at end of file diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex3-Dateien/abel.gif b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex3-Dateien/abel.gif new file mode 100644 index 0000000..172aa05 Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex3-Dateien/abel.gif differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex3-Dateien/abel_002.gif b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex3-Dateien/abel_002.gif new file mode 100644 index 0000000..8e1a5c4 Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex3-Dateien/abel_002.gif differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex3-Dateien/abel_003.gif b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex3-Dateien/abel_003.gif new file mode 100644 index 0000000..c0baf6b Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex3-Dateien/abel_003.gif differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex3.html b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex3.html new file mode 100644 index 0000000..75bb32e --- /dev/null +++ b/Bachelor/Digitaltechnik 2/SS07/P6/abel.ex3.html @@ -0,0 +1,158 @@ + + + + + Example of a Mealy Machine: string recognizer + +
+

+University of Pennsylvania

+ +
Department of Electrical Engineering
+ +
+ +
Finite State Machine implemented as a Synchronous +Mealy Machine:
+ +
+ +
a non-resetting sequence recognizer.
+ + +

The following state diagram (Fig. 1) describes the same finite state +machine as in the previous example: a sequence +detector with one input X and one output Z. The FSM asserts its output +Z when it recognizes the following input bit sequence: "1011". The machine +will keep checking for the proper bit sequence and does not reset to the +initial state after it has recognized the string. In contrast to the previous +example, the machine will be implemented as a synchronous Mealy Machine. +This will ensure that the output changes at the clock transition and will +prevent glitches which were possible with the Mealy Machine implementation +(see previous example). +

 
+ +
+ +
+ + +

Figure 1: State diagram, describing the sequence detector ("1011") implemented +as a Mealy machine. The number in italics underneath the states indicate +which part of the sequence the state remembers. + +

This state diagram can be defined in ABEL code given in Listing 1. The +output is described with the "With" keyword +to indicate that the output will change when the input goes to one. The +difference with the regular Mealy machine, is that the output Z is now +also clocked (see e.g. the statement, [Q1,Q0,Z].CLK +=CLOCK). Also, in the State Diagram section, the "WITH Z:=0" +makes use of the registered assignment ":=" operator. + +

Listing 1: ABEL source code for the Mealy Machine +implementation of the sequence detector described in Fig. 1 +

+ + +The ouput is specified with the "With" keyword. The corresponding simulation +is shown in Figure 2. +
 
+ +
 
+ +
+ +
+ +
+ +
Figure 2: Simulation of the sequence detector for "1011" described +with the state diagram of Fig. 1, implemented as a synchronous Mealy machine. +(Screen clip from Xilinx XACTstep(TM) Foundation software)
+ + +

Notice that the output Z is valid after the positive clock edge (in +response to the input value just before the positive clock edge). The output +asserts at the positive clock edge when the input has gone through the +sequence "1011". Notice also that the glitch which was present in the non-synchronous +Mealy machine is gone. + +

This timing in a synchronous Mealy machine is thus less critical than +in a non-synchronous machine. The price one pays for this, is additional +hardware. Making the output synchronous requires additional flip-flops +as is illustrated by the blue box (Output Registers) in the generic block +diagram of a synchronous Mealy machine in Figure 3. +

+ +
+ +
+ +
Figure 3: Synchronous Mealy Machine.
+ + +

+

Back to ABEL Primer Contents +| To to Common +Mistakes list | Go to the EE +Undergraduate Lab Homepage | Go to Xilinx +Lab Tutorial Homepage | Go to the Foundation +Tutorial page | Go to EE200 +or EE200 Lab +Homepage | + +

+

Created by J. Van der +Spiegel: December 30, 1997; Updated by J. Van der Spiegel: December +30, 1997. + + \ No newline at end of file diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel.primer-Dateien/abel.gif b/Bachelor/Digitaltechnik 2/SS07/P6/abel.primer-Dateien/abel.gif new file mode 100644 index 0000000..1a3f10d Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/abel.primer-Dateien/abel.gif differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel.primer.html b/Bachelor/Digitaltechnik 2/SS07/P6/abel.primer.html new file mode 100644 index 0000000..14667a2 --- /dev/null +++ b/Bachelor/Digitaltechnik 2/SS07/P6/abel.primer.html @@ -0,0 +1,1613 @@ + + + + + + + + + HDL-ABEL Primer + +
+

+University of Pennsylvania
+Department of Electrical +Engineering

+ +
+

+ABEL-HDL Primer

+ +

+ABEL Primer Contents

+ + + +

+1 Introduction

+ABEL (Advanced Boolean Equation Language) allows you to enter behavior-like +descriptions of a logic circuit. ABEL is an industry-standard hardware +description language (HDL) that was developed by Data I/O Corporation for +programmable logic devices (PLD). There are other hardware description +languages such as VHDL and Verilog. ABEL is a simpler language than VHDL +which is capable of describing systems of larger complexity. +

ABEL can be used to describe the behavior of a system in a variety of +forms, including logic equations, truth tables, and state diagrams using +C-like statements. The ABEL compiler allows designs to be simulated and +implemented into PLDs such as PALs, CPLDs and FPGAs. +

Following is a brief overview of some of the features and syntax of +ABEL. It is not intended to be a complete discussion of all its features. +This ABEL primer will get you started with writing ABEL code. In case you +are familiar with ABEL, this write-up can serve as a quick reference of +the most often used commands. For more advanced features, please consult +an ABEL manual or the Xilinx on-line documentation. +

+2. Basic structure of an ABEL source file

+An ABEL source file consists of the following elements. + +Keywords (words recognized by ABEL such as commands, e.g. goto, if, then, +module, etc.) are not case sensitive. User-supplied names and labels (identifier) +can be uppercase, lowercase or mixed-case, but are case-sensitive +(input1 is different from Input1). +

A typical template is given below. +

+The following source file is an example of a +half adder: + +A brief explanation of the statements follow. For a more detailed discussion +see the following sections or consult an ABEL-HDL manual. When using ABEL +with the Xilinx CAD software, you can use the ABEL wizard which will give +a template of the basic structure and insert some of the keywords. Also +the Language Assistant in the ABEL editor provides on-line help. Go to +the TOOLS ->LANGUAGE ASSISTANT menu. The Language templates give a description +of most ABEL commands, syntax, hierarchy, etc, while the Synthesis template +gives examples of typical circuits. +

+3. Declarations

+Module: each source files starts with +a module statement followed by a module name (identifier). Large source +files often consist of multiple modules with their own title, equations, +end statement, etc. +

Title: is optional and can +be used to identify the project. The title name must be between single +quotes. The title line is ignored by the compiler but is handy for documentation. +

String: is a series of ASCII characters enclosed by single +quotes. Strings are used for TITLE, OPTIONS statements, and in pin, node +and attribute declarations. +

device: this declaration is optional +and associates a device identifier with a specific programmable logic device. +The device statement must end with a semicolon. When you are using the +Xilinx CAD system to compile the design, it is better not to put the device +statement in the source file to keep your design independent of the device. +When you create a new project in Xilinx you will specify the device type +(can also be changed in the Project Manager window using the Project Information +button). The format is as follows: +

+comments: comments can be inserted anywhere in the file and +begin with a double quote and end with another double quote or the end +of the line, whatever comes first. +

pin: pin declarations tell the compiler +which symbolic names are associated with the devices external pins. Format: +

+One can specify more than one pin per line: + +You do not need to specify the pin. Pin numbers can be specified later +by using a "user constraint file " when doing the compilation using Xilinx +CAD. This has the advantage that our design is more general and flexible. +The ! indicates an active low (the signal will be inverted). The istype +is an optional attribute assignment for a pin such as 'com' to indicate +that the output is a combinational signal or 'reg' for a clocked signal +(registered with a flip flop). This attribute is only for output pins. +

node: node declarations have the +same format as the pin declaration. Nodes are internal signals which are +not connected to external pins. +

+other declarations allows one to define constants, sets, macros +and expressions which can simplify the program. As an example a constant +declaration has the following format: + +The last two equations are equivalent. The use of ".." is handy to specify +a range. The last example makes use of vector notations. Any time you use +D in an equation, it will refer to the vector [D3, D2, D1. D0]. +

+4. Numbers

+Numbers can be entered in four different bases: binary, octal, decimal +and hexadecimal. The default base is decimal. Use one of the following +symbols (upper or lower case allowed) to specify the base. When no symbol +is specified it is assumed to be in the decimal base. You can change +the default base with the Directive "Radix" as explained in the next section. +
  + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BASE NAMEBASESymbol.
Binary2^b 
Octal8^o 
Decimal10^d (default) 
Hexadecimal16^h 
+ +

Examples: +
  + + + + + + + + + + + + + + + + + + + + + + + + +
+
    Specified in ABEL
+		Decimal Value
+
    35
+		 +
    35
+
+
    ^h35
+		 +
    53
+
+
    ^b101
+		 +
    5
+
+ +

+5. Directives

+Directives allow advanced manipulation of the source file and processing, +and can be placed anywhere needed in a file. +

@ALTERNATE +
Syntax +
@alternate +
  +
@ALTERNATE enables an alternate set of operators. Using the alternate +operator set precludes use of the ABEL-HDL addition (+), multiplication +(*) and division (/) operators because they represent the OR, AND and NOT +logical operators in the alternate set. The standard operator still work +when @ALTERNATE is in effect. The alternate operators remain in effect +until the @STANDARD directive is used or the end of the module is reached. +

@RADIX +
Syntax +
@radix expr ; +
Expr:  A valid expression that produces the number 2, 8, +10 or 16 to indicate a new default base number. +

The @Radix directive changes the default base. The default is base 10 +(decimal). The newly-specified default base stays in effect until another +@radix directive is issued or until the end of the module is reached. Note +that when a new @radix is issued, the specification of the new base must +be in the current base format +

Example +

@radix 2;           +“change default base to binary +
… +
@radix 1010;     “change back from binary  +to decimal
+ +


@STANDARD +
Syntax +
@standard +

The @standard option resets the operators to the ABEL-HDL standard. +The alternate set is chosen with the @alternative directive. +
  +
  +

+

+ +

+6. Sets

+A set is a collection of signals or constants used to reference a group +of signals by one name. A set is very handy to simplify logic expressions. +Any operation that is applied to a set is applied to each element. +

A set is a list of constants or signals separated by commas or the range +operator (..) put between square brackets (required). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
    [D0,D1,D2,D4,D5]
+
+
    [D0..D6]
+		" incrementing range 
+
    [b6..b0]
+		" decrementing range 
+
    [D7..D15]
+
+
    [b1,b2,a0..a3]
+		" range within a larger set
+
    [!S7..!S0]
+		"decrementing range of active -low signals
+ +

However, the following is not allowed: [D0, X]; +

+ +

+a. Indexing or accessing a set

+Indexing allows you to access elements within a set. Use numerical values +to indicate the set index. The number refers to the bit position in the +set starting with 0 for the least significant bit of the set. Here are +some examples. + +To access one element in the set, use the following syntax: + +Here a comparator operator (==) is used to convert the single-element (X[2]) +into a bit value equivalent to X2. The comparator (==) gives a"1" or "0" +depending if the comparison is True or False. Notice the +difference +between the assignment operator (=) and the equal operator (==). The +assignment operator is used in equations rather than in expressions. Equations +assign the value of an expression to the output signals. +

+b. Set operations

+Most of the operations can be applied to a set and are performed on each +element of the set according to the rules of Boolean algebra. Operations +are performed according to the operator's priority; +operators with the same priority are performed from left to right (unless +one uses parentheses). Here are a couple of examples. +
  +
  +

Example 1: +

+Example 2: + +this is equivalent to two statements: + +Example 3: + +Example 4: + +which is equivalent to + +However consider the following expression + +now the number "2" is first converted into a binary representation and +padded with zeros (0010) if necessary. Thus the above equation is equivalent +to: + +Example 5: + +Example 6: + +The number "2" is converted into binary and padded with zeros (0010). +

Example 7: Sets are also handy to specify logic equations. Suppose you +need to specify the equation: +

+This can be done using sets. First define a constant Addr set.: + +One can then use the following equation to specify the address: + +which is equivalent to saying: + +Indeed, if A7=0, A6=1 and A5=1, the expression Addr ==[0,1,1] is true (or +1) and thus Chip_Sel will be true (or 1). Another way to write the same +equation is: + +The above expressions are very helpful when working with a large number +of variables (ex. a 16 bit address). +

Example 8: +

For the same constants as in the example above, the expression, +

+which is equivalent to + +However, the following statement is different: + +which is equivalent to: + +However, the relational operator (==) gives only one bit, so that +the rest of the equation evaluates also to one bit, and the "3" is truncated +to "1":. Thus the above equation is equal to: + + +

+7. Operators

+There are four basic types of operators: logical, arithmetic, relational +and assignment.. +

+a. Logical Operators

+The table below gives the logical operators. They are performed bit by +bit. With the @ALTERNATIVE directive, one can +use the alternative set of operators as indicated in the table. +
  + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operator (default)Description Alternate operator
!NOT (ones complement)/
&AND* 
#OR+
$XOR: exclusive or:+: 
!$XNOR: exclusive nor:*:
+ +

+b. Arithmetic operators

+The table below gives the arithmetic operators. Note that the last four +operators are not allowed with sets. The minus sign can have different +meanings: used between two operands it indicates subtraction (or adding +the twos complement), while used with one operator it indicates the twos +complement. +
  + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OperatorExampleDescription
--D1Twos complement (negation) 
-C1-C2Subtraction 
+A+BAddition 
+
The following operators are not used with sets: 
+
*A*BMultiplication 
/A/BUnsigned integer division 
%A%BModulus: remainder of A/B 
<<A<<BShift A left by B bits 
>>A>>BShift B right by B bits 
+ +

+c. Relational operators

+These operators produce a Boolean value of True (-1) or False (0). +The logical true value of -1 in twos complement is represented by all ones +(i.e.all bits will be ones: ex. for a 16 bit word all bits are one: +-1 is represented by 1111 1111 1111 1111). +
  + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operator ExampleDescription 
==A==B or 3==5 (false)Equal
!=A!=B or 3 != 5 (true) Not equal
<A<B or 3 < 5 (true) Less than
<=A<=B or 3 <= 5 (true) Less than or equal
>A>B or -1 > 5 (true) Greater than
>=A>=B or !0 >= 5 (true) Greater than or equal
+ +
  +

Relational operators are unsigned. +Be careful: !0 is the one complement of 0 or 11111111 (8 bits data) which +is 255 in unsigned binary. Thus !0 > 9 is true. The expression -1>5 is +true for the same reason. +

A relational expression can be used whenever a number can be used. The +-1 or 0 will be substituted depending on the logical result. As an example +: +

+A will be equal to B if C is equal to D (true or 11111...; B XNOR 1 equals +B), otherwise, A will be equal to the complement of B (if C is not equal +to B (false or 0)). +

+d. Assignment operators

+These operators are used in equations to assign the value of an expression +to output signals. There are two types of assignment operators: combinational +and registered. In a combinational operator the assignment occurs immediately +without any delay. The registered assignment occurs at the next clock pulse +associated with the output. As an example, one can define a flip-flop with +the following statements: + +The first statement defines the Q1 flip-flop by using the 'reg' as istype +(registered output). The second statement tells that the output of the +flip-flop will take the value of the D input at the next clock transition. +
  + + + + + + + + + + + + + + + + + + +
OperatorDescription
=Combinational assignment 
:=Registered assignment
+ +

+e. Operator priority

+The priority of each operator is given in the following table, with priority +1 the highest and 4 the lowest. Operators with the same priority are performed +from left to right. +
  + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PriorityOperatorDescription 
1-Negation (twos complement) 
1!NOT 
2&AND 
2<<shift left 
2>>shift right 
2*multiply 
2/unsigned division 
2%modulus 
3+add 
3-subtract 
3#OR
3$XOR 
3!$XNOR 
4==equal 
4!=not equal 
4<less then 
4<=less then or equal 
4>greater than 
4>=greater than or equal 
+ +

+8. Logic description

+A logic design can be described in the following way. + + +

+a. Equations

+Use the keyword equations to begin the +logic descriptions. Equations specify logic expressions using the operators +described above, or "When-Then-Else" statement. +

The "When-Then-Else" statement +is used in equations to describe a logic function. (Note: "If +-Then-Else" is used in the State-diagram section to describe state +progression). +

The format of the "When-Then-Else" statement is as follows: +

+Examples of equations: + +One can use the braces { } to group sections together in blocks. The text +in a block can be on one line or span many lines. Blocks are used in equations, +state diagrams and directives. +

+b. Truth Tables

+The keyword is truth-table and the syntax +is + +or + +or + +in which "->" is for combinational output and ":>" for registered output. +The first line of a truth table (between parentheses) defines the inputs +and the output signals. The following lines gives the values of the inputs +and outputs. Each line must end with a semicolon. The inputs and outputs +can be single signals or sets. When sets are used as inputs or outputs, +use the normal set notation, i.e. signals surrounded by square brackets +and separated by commans. A don't care is represented by a ".X.". +

Example 1: half adder +

+However, if one defines a set IN = [A,B]; and OUT = [Sum, Carry_out]; the +truth table becomes simpler: + +Example 2: An excluse OR with two intputs and one enable (EN). This example +illustrates the use of don't cares (.X.) + +Example 3: (see Example in R. Katz, section 7.2.1 and table 7.14) +

Truth tables can also be used to define sequential machines. Lets implement +a three-bit up counter which counts from 000, 001, to 111 and back to 000. +Lets call QA, QB and QC the outputs of the flip-flops. In addition, we +will generate an output OUT whenever the counter reaches the state 111. +We will also reset the counter to the state 000 when the reset signal is +high. +

+For the use of .DOT extensions (.CLK and .AR) see section 7d. +

+c. State Description

+The State_diagram section contains the state description for the logic +design. This section uses the State_diagram syntax and the "If-Then-Else", +"Goto", "Case" and "With" statements. Usually one declares symbolic state +names in the Declaration section, which makes reading the program often +easier. +

State declaration (in the declaration section) syntax: +

+As an example: SREG = [Q1, Q2]; associates +the state name SREG with the state defined by Q1 and Q2. +

The syntax for State_diagram is as follows: +

+The keyword state_diagram indicates +the beginning of a state machine description. +

The STATE keyword and following statements describe one state of the +state diagram and includes a state value or symbolic state name, state +transition statement and an optional output equation. In the above syntax, +

+If-Then-Else +statement: +

This statement is used in the state_diagram section to describe the +next state and to specify mutually exclusive transition conditions. +

Syntax: +

+In which state-exp can be a logic expression or a symbolic state name. +Note that the "IF-Then-Else" statement can only be used in the state_diagram +section (use the "When-If-Then" +to describe logic functions". The ELSE clause is optional. The IF-Then-Else +statements can be nexted with Goto, Case +and With statements. +

Example (after R. Katz): +

in the declaration section we define first the state registers: +

+"If-Then-Else" statements can be nested as in the following example (after +Wakerly). We assume that one has defined the registers and states in the +declaration section. + +"with" statement: +

Syntax: +

+in which trans_stmt can be "If-then-else", 'Goto" or a "Case" statement. +
state_exp: is the next state, and equation is an +equation for the machine outputs. +

This statement can be used with the "If-Then-Else", "Goto" or "Case" +statements in place of a simple state expression. The "With" statement +allows the output equations to be written in terms of transitions. +

Example 1: +

+In the above example, the output Z will be asserted as soon as the expression +after the if statement evaluates to a logic 1 (or TRUE). The expression +after the "With" keyword can be an equation that will be evaluated as soon +as the if condition is true as in example 2: +

Example 2: +

+The "With" statement is also useful to describe output behavior of registered +outputs, since registered outputs would lag by one clock cycle. It allows +one also for instance to specify that a registered output should have a +specific value after a particular transition. As an example [1], +

Example 3[1]: +

state S1: +

+Notice that one can use curly braces to control a group of outputs and +equations after the With keyword as in the example above. +

Example 3: +

+You have to be aware of the timing when using the "With " statement with +combinational or asynchronous outputs (as in a Mealy machine). A Mealy +machine changes its outputs as soon as the input changes. This may cause +the output to change too quickly resulting in glitches. The outputs of +a Mealy machine will be valid at the end of a state time (i.e. just before +the clock transition). In this respect a Moore output (with synhronous +outputs) is less prone to timing errors. An example of a Mealy +machine and a Moore machine is available. +

Case statement +

Syntax: +

+expression is any valid ABEL expression and state_exp is an expression +that indicates the next state (optionally followed by WITH statement). +

Example: +

+The case statement is used to list a sequence of mutually-exclusive transition +conditions and corresponding next states. The CASE statement conditions +must be mutually exclusive (no two transition conditions can be true at +the same time) or the resulting next state is unpredictable. +

+d. Dot extensions

+One can use dot extensions to more precisely describe the behavior of the +circuit. The signal extensions are very handy and provide a means to refer +specifically to internal signals and nodes associated with a primary signal. +

The syntax is +

+Some of the dot extensions are given in the following table. Extensions +are not case sensitive. Some dot extensions are general purpose (also called +architecture independent or pin-to-pin) and can used with a variety of +device architectures. Other dot extensions are used for specific classes +of device architectures and are called architecture-dependent or detailed +dot extensions. In general, you can use either dot extensions. +
  +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Dot extensionDescription
Architecture independent or pin-to-pin extensions
.ACLRAsynchronous register reset 
.ASETAsynchronous register preset 
.CLKClock input to an edge-triggered flip-flop 
.CLRSynchronous register reset 
.COMCominbational feedback from flip-flop data input 
.FGRegister feedback
.OEOutput enable
.PINPin feedback
.SETSynchronous register preset 
Device Specific extensions (architecture +dependent)
.DData input to a D Flip flop 
.JJ input to a JK flip-flop 
.KK input to a JK flip-flop 
.SS input to a SR flip-flop 
.RR input to a SR flip-flop 
.TT input to a T flip-flop 
.QRegister feedback
.PRRegister preset
.RERegister reset
.APAsynchronous register preset 
.ARAsynchronous register reset 
.SPSynchronous register preset 
.SRSynchronous register reset 
+ +

The figure below illustrates some of the extensions. +


+
+
+

+

+

Figure 1: Illustration of DOT extensions for: (a) an architecture independent +(pin-to-pin) and (b) arhitecture dependent D-type (or T-type) Flip Flop +Architecture

+ +

Example 1: +

+which accesses the tri state control signal of the output buffers of the +signals S6..S0. When ACTIVE is high, the signals will be enabled, otherwise +a high Z output is generated. +

Example 2: +

+which resets to output of the registers (flip flops) to zero when reset +is high. +

+9. Test vectors

+Test vectors are optional and provide a means to verify the correct operation +of a state machine. The vectors specify the expected logical operation +of a logic device by explicitly giving the outputs as a function of the +inputs. +

Syntax: +

+Example: + +One can also specify the values for the set with numeric constants as shown +below. + +Don't cares (.X.), clock inputs (.C.) as well as symbolic constants are +allowed, as shown in the following example. +
  +
  + + +

+10. Property Statements

+ABEL allows to give device specific statements using the property statement. +This statement will be passed to the "Fitter" program during compilation. +For the CPLD devices these properties include + + +

+11. Miscellaneous

+ +

+a. Active-low declarations

+Active low signals are defined with a "!" operator, as shown below, + +When this signal is used in a subsequent design description, it will be +automatically complemented. As an example consider the following description, + +In this example, the signal OUT is an XOR of A and B, i.e. OUT will be +"1" (High, or ON) when only one of the inputs is "1", otherwise OUT is +"0". However, the output pin is defined as !OUT , i.e. as an active-low +signal, which means that the pin will go low "0" (Active-low or ON) when +only one of the two inputs are "1". One could have obtained the same result +by inverting the signal in the equations and declaring the pin to be OUT, +as is shown in the following example. This is called explicit pin-to-pin +active-low (because one uses active-low signals in the equations). + +Active low can be specified for a set as well. As an example lets define +the sets A,B and C. + +The last equation is equivalent to writing + + +

+References

+ + + +

+Acknowledgement

+The support of Mr. Jason Feinsmith and the XilinxCorporation +is acknowledged for providing the XILINX Foundation M1(TM) Software and +FPGA Demoboards for educational purposes. +

+ +

+Back to ABEL Primer Contents | To +to Common +Mistakes list | Go to the EE +Undergraduate Lab Homepage | Go to Xilinx +Lab Tutorial Homepage | Go to the Foundation +Tutorial page | Go to EE200 +or +EE200 Lab Homepage +| . +
+

Created by J. Van der Spiegel, +<jan@ee.upenn.edu> Sept. 26, 1997; Updated August 13, 1999 +

\ No newline at end of file diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip new file mode 100644 index 0000000..7c9c28a Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/add1b.abl b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/add1b.abl new file mode 100644 index 0000000..52e7827 --- /dev/null +++ b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/add1b.abl @@ -0,0 +1,26 @@ +MODULE adder_1bit + +TITLE 'Volladdierer mit Carry' + +DEClARATIONS + Bit_1 pin 15; // I/O 0, input + Bit_2 pin 16; // I/O 1, input + C_in pin 17; // I/O 2, input + + Sum pin 29 istype 'com'; // I/O 12, output kombinatorisch + C_out pin 30 istype 'com'; // I/O 13, output kombinatorisch + + +TRUTH_TABLE ( [Bit_1,Bit_2,C_in] -> [Sum,C_out] ) // Wahrheitstabelle des Volladdierers + + [0 ,0 ,0 ] -> [0 ,0 ]; + [0 ,0 ,1 ] -> [1 ,0 ]; + [0 ,1 ,0 ] -> [1 ,0 ]; + [0 ,1 ,1 ] -> [0 ,1 ]; + [1 ,0 ,0 ] -> [1 ,0 ]; + [1 ,0 ,1 ] -> [0 ,1 ]; + [1 ,1 ,0 ] -> [0 ,1 ]; + [1 ,1 ,1 ] -> [1 ,1 ]; + +END + diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b1.abl b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b1.abl new file mode 100644 index 0000000..257cd94 --- /dev/null +++ b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b1.abl @@ -0,0 +1,25 @@ +MODULE Counter_4_bit + +TITLE '0 ... 9, version with equations' + +DEClARATIONS + clk pin 15; " I/O 0, Eingang für den Takt + rst pin 16; " I/O 1, Eingang für das Reset Signal + ce pin 17; " I/O 2, Eingang für das Enable Signal + q3,q2,q1,q0 pin 29,30,31,32 istype 'reg'; " I/O 12, 13, 14, 15, Ausgang: Bits des Zählers, 15: 2^0 + carry pin 44 istype 'reg'; // I/O 23, Ausgang für Carry + +" bus definition, vector, register + counter = [q3,q2,q1,q0]; + +EQUATIONS + counter.clk = clk; + counter.ar = rst; + carry.clk = clk; + when (ce & (counter < 9)) then counter := counter + 1; + else when (ce & (counter >= 9)) then {counter := 0; carry := 1;} + else counter := counter; + + +END + diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b2.abl b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b2.abl new file mode 100644 index 0000000..545d92b --- /dev/null +++ b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b2.abl @@ -0,0 +1,71 @@ +MODULE Counter_4_bit +TITLE '0 ... 9, version with state diagram' +DEClARATIONS + clk pin 15; " I/O 0, Eingang für den Takt + rst pin 16; " I/O 1, Eingang für das Reset Signal + ce pin 17; " I/O 2, Eingang für das Enable Signal + q3,q2,q1,q0 pin 29,30,31,32 istype 'reg'; " I/O 12, 13, 14, 15, Ausgang: Bits des Zählers, 15: 2^0 + carry pin 44 istype 'reg'; // I/O 23, Ausgang für Carry + +" bus definition, vector, register + counter = [q3,q2,q1,q0]; + +EQUATIONS + counter.clk = clk; + carry.clk = clk; + +STATE_DIAGRAM counter; + State 0: + if(!rst & ce) then 1; " Bei Erfüllung der Bedingung erfolgt ein Übergang in State 1 + else 0; + State 1: + if (rst) then 0; + else if (ce) then 2; + else 1; + State 2: + if (rst) then 0; + else if (ce) then 3; + else 2; + State 3: + if (rst) then 0; + else if (ce) then 4; + else 3; + State 4: + if (rst) then 0; + else if (ce) then 5; + else 4; + State 5: + if (rst) then 0; + else if (ce) then 6; + else 5; + State 6: + if (rst) then 0; + else if (ce) then 7; + else 6; + State 7: + if (rst) then 0; + else if (ce) then 8; + else 7; + State 8: + if (rst) then 0; + else if (ce) then 9; + else 8; + State 9: + carry := 1; + if (rst) then 0; + else if (ce) then 0; + else 9; + State 10: + goto 0; " es erfolgt ein bedingungsloser Übergang in State 0 + State 11: + goto 0; + State 12: + goto 0; + State 13: + goto 0; + State 14: + goto 0; + State 15: + goto 0; +END + diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/intro2k.pdf b/Bachelor/Digitaltechnik 2/SS07/P6/intro2k.pdf new file mode 100644 index 0000000..25ee5a8 Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/intro2k.pdf differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/ispLever_Kurzanleitung.pdf b/Bachelor/Digitaltechnik 2/SS07/P6/ispLever_Kurzanleitung.pdf new file mode 100644 index 0000000..3ed22c3 Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/ispLever_Kurzanleitung.pdf differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/p6.odt b/Bachelor/Digitaltechnik 2/SS07/P6/p6.odt new file mode 100644 index 0000000..f3088c7 Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/p6.odt differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/p6a1-state.dia b/Bachelor/Digitaltechnik 2/SS07/P6/p6a1-state.dia new file mode 100644 index 0000000..fb7b6da Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/p6a1-state.dia differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/p6a1-state.png b/Bachelor/Digitaltechnik 2/SS07/P6/p6a1-state.png new file mode 100644 index 0000000..29489f0 Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/p6a1-state.png differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/p6a1-statetab.ods b/Bachelor/Digitaltechnik 2/SS07/P6/p6a1-statetab.ods new file mode 100644 index 0000000..619fcaf Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/p6a1-statetab.ods differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/p6a1.abl b/Bachelor/Digitaltechnik 2/SS07/P6/p6a1.abl new file mode 100755 index 0000000..739e7a5 --- /dev/null +++ b/Bachelor/Digitaltechnik 2/SS07/P6/p6a1.abl @@ -0,0 +1,95 @@ +MODULE ampel1 +TITLE 'Ampelsteuerung 1, state diagram' +DEClARATIONS + clk pin 15; " I/O 0, Eingang für den Takt + rst pin 16; " I/O 1, Eingang für das Reset Signal + ce pin 17; " I/O 2, Eingang für das Enable Signal + vg,vy,vr,fg,fr pin 25,26,27,28,29 istype 'reg'; " I/O 8,9,10,11,12 + +" bus definition, vector, register + ampel = [vg,vy,vr,fg,fr]; + +EQUATIONS + ampel.clk = clk; + +STATE_DIAGRAM ampel; + State 0: + if(!rst & ce) then 17; " Bei Erfüllung der Bedingung erfolgt ein Übergang in State 17 + else 0; + State 1: + goto 0; " es erfolgt ein bedingungsloser Übergang in State 0 + State 2: + goto 0; + State 3: + goto 0; + State 4: + goto 0; + State 5: + goto 0; + State 6: + if (rst) then 0; + else if (ce) then 13; + else 0; + State 7: + if (rst) then 0; + else if (ce) then 8; + else 7; + State 8: + if (rst) then 0; + else if (ce) then 9; + else 8; + State 9: + if (rst) then 0; + else if (ce) then 6; + else 0; + State 10: + goto 0; " es erfolgt ein bedingungsloser Übergang in State 0 + State 11: + goto 0; + State 12: + goto 0; + State 13: + if (rst) then 0; + else if (ce) then 17; + else 0; + State 14: + goto 0; + State 15: + goto 0; + State 16: + goto 0; + State 17: + if (rst) then 0; + else if (ce) then 9; + else 0; + State 18: + goto 0; + State 19: + goto 0; + State 20: + goto 0; + State 21: + goto 0; + State 22: + goto 0; + State 23: + goto 0; + State 24: + goto 0; + State 25: + goto 0; + State 26: + goto 0; + State 27: + goto 0; + State 28: + goto 0; + State 29: + goto 0; + State 30: + goto 0; + State 31: + goto 0; + +END + diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/p6a1b.abl b/Bachelor/Digitaltechnik 2/SS07/P6/p6a1b.abl new file mode 100755 index 0000000..c3846ce --- /dev/null +++ b/Bachelor/Digitaltechnik 2/SS07/P6/p6a1b.abl @@ -0,0 +1,41 @@ +MODULE ampel1 +TITLE 'Ampelsteuerung 1, state diagram' +DEClARATIONS + clk pin 15; " I/O 0, Eingang für den Takt + rst pin 16; " I/O 1, Eingang für das Reset Signal + ce pin 17; " I/O 2, Eingang für das Enable Signal + vg,vy,vr,fg,fr pin 25,26,27,28,29 istype 'reg'; " I/O 8,9,10,11,12 + state0 node istype 'reg'; + state1 node istype 'reg'; + +" bus definition, vector, register + ampel = [vg,vy,vr,fg,fr]; + states =[state0,state1]; + +EQUATIONS + ampel.clk = clk; + states.clk = clk; + +STATE_DIAGRAM states; + State 0: + ampel:=17; + if(!rst & ce) then 1; " Bei Erfüllung der Bedingung erfolgt ein Übergang in State 1 + else 0; + State 1: + ampel:=9; + if (rst) then 0; + else if (ce) then 2; + else 0; + State 2: + ampel:=6; + if (rst) then 0; + else if (ce) then 3; + else 0; + State 3: + ampel:=13; + if (rst) then 0; + else if (ce) then 0; + else 0; + +END + diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/p6a2-state.dia b/Bachelor/Digitaltechnik 2/SS07/P6/p6a2-state.dia new file mode 100644 index 0000000..b71dd0a Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/p6a2-state.dia differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/p6a2-state.png b/Bachelor/Digitaltechnik 2/SS07/P6/p6a2-state.png new file mode 100644 index 0000000..749d261 Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/p6a2-state.png differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/p6a2-statetab.ods b/Bachelor/Digitaltechnik 2/SS07/P6/p6a2-statetab.ods new file mode 100644 index 0000000..4eba64e Binary files /dev/null and b/Bachelor/Digitaltechnik 2/SS07/P6/p6a2-statetab.ods differ diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/p6a2.abl b/Bachelor/Digitaltechnik 2/SS07/P6/p6a2.abl new file mode 100755 index 0000000..9f8f11f --- /dev/null +++ b/Bachelor/Digitaltechnik 2/SS07/P6/p6a2.abl @@ -0,0 +1,96 @@ +MODULE Ampel2 +TITLE 'Ampelsteuerung state diagram' +DEClARATIONS + clk pin 15; " I/O 0, Eingang für den Takt + rst pin 16; " I/O 1, Eingang für das Reset Signal + ce pin 17; " I/O 2, Eingang für das Enable Signal + taste pin 18; " I/O 3, Eingang für das Tasten-Signal + vg,vy,vr,fg,fr pin 25,26,27,28,29 istype 'reg'; " I/O 8,9,10,11,12 + +" bus definition, vector, register + ampel = [vg,vy,vr,fg,fr]; + +EQUATIONS + ampel.clk = clk; + +STATE_DIAGRAM ampel; + State 0: + if(!rst & ce) then 17; " Bei Erfüllung der Bedingung erfolgt ein Übergang in State 17 + else 0; + State 1: + goto 0; " es erfolgt ein bedingungsloser Übergang in State 0 + State 2: + goto 0; + State 3: + goto 0; + State 4: + goto 0; + State 5: + goto 0; + State 6: + if (rst) then 0; + else if (ce) then 13; + else 0; + State 7: + if (rst) then 0; + else if (ce) then 8; + else 7; + State 8: + if (rst) then 0; + else if (ce) then 9; + else 8; + State 9: + if (rst) then 0; + else if (ce) then 6; + else 0; + State 10: + goto 0; " es erfolgt ein bedingungsloser Übergang in State 0 + State 11: + goto 0; + State 12: + goto 0; + State 13: + if (rst) then 0; + else if (ce) then 17; + else 0; + State 14: + goto 0; + State 15: + goto 0; + State 16: + goto 0; + State 17: + if (rst) then 0; + else if (ce) then 9; + else 0; + State 18: + goto 0; + State 19: + goto 0; + State 20: + goto 0; + State 21: + goto 0; + State 22: + goto 0; + State 23: + goto 0; + State 24: + goto 0; + State 25: + goto 0; + State 26: + goto 0; + State 27: + goto 0; + State 28: + goto 0; + State 29: + goto 0; + State 30: + goto 0; + State 31: + goto 0; + +END + diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/p6a2.xcf b/Bachelor/Digitaltechnik 2/SS07/P6/p6a2.xcf new file mode 100755 index 0000000..5f380be --- /dev/null +++ b/Bachelor/Digitaltechnik 2/SS07/P6/p6a2.xcf @@ -0,0 +1,53 @@ + + + + + + JTAG + + 1 + Lattice + ispLSI 2000VE + 2032VE(VL) + 0x10301043 + All + ispLSI2032VE/VL + + 5 + 11111 + 1 + 0 + + C:\Programme\ispTOOLS5_1_STRT\ispcpld\bin\untitled.jed + 06/20/07 14:58:00 + 0xCA74 + Erase,Program,Verify + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + + + TMS LOW; + TCK LOW; + TDI LOW; + TDO LOW; + CableEN HIGH; + ISPEN LOW; + + + diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/p6a2b.abl b/Bachelor/Digitaltechnik 2/SS07/P6/p6a2b.abl new file mode 100755 index 0000000..88b56bb --- /dev/null +++ b/Bachelor/Digitaltechnik 2/SS07/P6/p6a2b.abl @@ -0,0 +1,51 @@ +MODULE ampel2 +TITLE 'Ampelsteuerung 1, state diagram' +DEClARATIONS + clk pin 15; " I/O 0, Eingang für den Takt + taste pin 18 istype 'reg'; " I/O 3, Eingang für das Enable Signal + vg,vy,vr,fg,fr pin 25,26,27,28,29 istype 'reg'; " I/O 8,9,10,11,12 + state0 node istype 'reg'; + state1 node istype 'reg'; + state2 node istype 'reg'; + tmp_taste node istype 'reg'; + +" bus definition, vector, register + ampel = [vg,vy,vr,fg,fr]; + states =[state0,state1,state2]; + +EQUATIONS + ampel.clk = clk; + states.clk = clk; + tmp_taste.clk=clk; + tmp_taste.aset=taste; + tmp_taste.d=0; + +STATE_DIAGRAM states; + State 0: + ampel:=17; + if(tmp_taste == 1) then 1; " Bei Erfüllung der Bedingung erfolgt ein Übergang in State 1 + else 0; + State 1: + ampel:=9; + goto 2; + State 2: + ampel:=5; + goto 3; + State 3: + ampel:=6; + goto 4; + State 4: + ampel:=6; + goto 5; + State 5: + ampel:=5; + goto 6; + State 6: + ampel:=13; + goto 0; + State 7: + ampel:=0; + goto 0; + +END + -- cgit v1.2.3