From 33613a85afc4b1481367fbe92a17ee59c240250b Mon Sep 17 00:00:00 2001 From: Sven Eisenhauer Date: Fri, 10 Nov 2023 15:11:48 +0100 Subject: add new repo --- .../ARM202U/EXAMPLES/BASICASM/LOADCON3.S | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON3.S (limited to 'Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON3.S') diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON3.S b/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON3.S new file mode 100644 index 0000000..425c1de --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON3.S @@ -0,0 +1,14 @@ + AREA Example, CODE + ENTRY ; Mark first instruction +Start + ADR r0, Start ; => SUB r0, PC, #offset to Start + ADR r1, DataArea ; => ADD r1, PC, #offset to DataArea + ; ADR r2, DataArea+4300 ; This would fail as the offset is + ; cannot be expressed by operand2 + ; of an ADD + ADRL r3, DataArea+4300 ; => ADD r2, PC, #offset1 + ; ADD r2, r2, #offset2 + SWI 0x11 ; Terminate +DataArea % 8000 + + END -- cgit v1.2.3