From 33613a85afc4b1481367fbe92a17ee59c240250b Mon Sep 17 00:00:00 2001
From: Sven Eisenhauer <sven@sven-eisenhauer.net>
Date: Fri, 10 Nov 2023 15:11:48 +0100
Subject: add new repo

---
 .../ARM202U/EXAMPLES/EXPLASM/RANDOM.S              | 42 ++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/RANDOM.S

(limited to 'Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/RANDOM.S')

diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/RANDOM.S b/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/RANDOM.S
new file mode 100644
index 0000000..67aacdf
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/RANDOM.S
@@ -0,0 +1,42 @@
+; Random number generator
+;
+; This uses a 33-bit feedback shift register to generate a pseudo-randomly
+; ordered sequence of numbers which repeats in a cycle of length 2^33 - 1
+; NOTE: randomseed should not be set to 0, otherwise a zero will be generated
+; continuously (not particularly random!).
+;
+; This is a good application of direct ARM assembler, because the 33-bit
+; shift register can be implemented using RRX (which uses reg + carry).
+; An ANSI C version would be less efficient as the compiler would not use RRX.
+
+	AREA 	|Random$$code|, CODE, READONLY
+
+	EXPORT	randomnumber
+
+randomnumber
+; on exit:
+;	a1 = low 32-bits of pseudo-random number
+;	a2 = high bit (if you want to know it)
+	LDR	ip, |seedpointer|
+	LDMIA	ip, {a1, a2}
+	TST	a2, a2, LSR#1		; to bit into carry
+	MOVS	a3, a1, RRX		; 33-bit rotate right
+	ADC	a2, a2, a2		; carry into LSB of a2
+	EOR	a3, a3, a1, LSL#12	; (involved!)
+	EOR	a1, a3, a3, LSR#20	; (similarly involved!)
+	STMIA	ip, {a1, a2}
+
+	MOV	pc, lr
+
+|seedpointer|
+	DCD	seed
+
+
+	AREA	|Random$$data|, DATA
+
+	EXPORT	seed
+seed
+	DCD	&55555555
+	DCD	&55555555
+
+	END
-- 
cgit v1.2.3