From 33613a85afc4b1481367fbe92a17ee59c240250b Mon Sep 17 00:00:00 2001 From: Sven Eisenhauer Date: Fri, 10 Nov 2023 15:11:48 +0100 Subject: add new repo --- .../ARM202U/EXAMPLES/EXPLASM/UDIV10.S | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/UDIV10.S (limited to 'Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/UDIV10.S') diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/UDIV10.S b/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/UDIV10.S new file mode 100644 index 0000000..787bb0b --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/UDIV10.S @@ -0,0 +1,23 @@ +; generated by divc 1.01 (Advanced RISC Machines) [01 Jul 92] + + AREA |div10$code|, CODE, READONLY + + EXPORT udiv10 + +udiv10 +; takes argument in a1 +; returns quotient in a1, remainder in a2 +; cycles could be saved if only divide or remainder is required + SUB a2, a1, #10 + SUB a1, a1, a1, lsr #2 + ADD a1, a1, a1, lsr #4 + ADD a1, a1, a1, lsr #8 + ADD a1, a1, a1, lsr #16 + MOV a1, a1, lsr #3 + ADD a3, a1, a1, asl #2 + SUBS a2, a2, a3, asl #1 + ADDPL a1, a1, #1 + ADDMI a2, a2, #10 + MOV pc, lr + + END -- cgit v1.2.3