From 33613a85afc4b1481367fbe92a17ee59c240250b Mon Sep 17 00:00:00 2001 From: Sven Eisenhauer Date: Fri, 10 Nov 2023 15:11:48 +0100 Subject: add new repo --- .../ARM202U/SOURCE/WIN32/ARMUL/ARMCOPRO.C | 360 +++++ .../ARM202U/SOURCE/WIN32/ARMUL/ARMDEFS.H | 509 ++++++ .../ARM202U/SOURCE/WIN32/ARMUL/ARMFAST.C | 365 +++++ .../ARM202U/SOURCE/WIN32/ARMUL/ARMFPE.H | 1701 ++++++++++++++++++++ .../ARM202U/SOURCE/WIN32/ARMUL/ARMOS.C | 828 ++++++++++ .../ARM202U/SOURCE/WIN32/ARMUL/ARMOS.H | 64 + .../ARM202U/SOURCE/WIN32/ARMUL/ARMPROTO.C | 512 ++++++ .../ARM202U/SOURCE/WIN32/ARMUL/ARMULATE.DEF | 28 + .../ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.C | 122 ++ .../ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.H | 62 + .../ARM202U/SOURCE/WIN32/ARMUL/ARMVIRT.C | 871 ++++++++++ .../SOURCE/WIN32/ARMUL/MSVC20/DLL/ARMULATE.MAK | 29 + .../ARM202U/SOURCE/WIN32/ARMUL/MSVC20/IARM.LIB | Bin 0 -> 175136 bytes 13 files changed, 5451 insertions(+) create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMCOPRO.C create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMDEFS.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFAST.C create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFPE.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.C create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMPROTO.C create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULATE.DEF create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.C create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMVIRT.C create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/DLL/ARMULATE.MAK create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/IARM.LIB (limited to 'Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL') diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMCOPRO.C b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMCOPRO.C new file mode 100644 index 0000000..15afbc6 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMCOPRO.C @@ -0,0 +1,360 @@ +/***************************************************************************\ +* armcopro.c * +* ARMulator II co-processor interface. * +* Copyright (C) 1991 Advanced RISC Machines Limited. All rights reserved. * +* Written by Dave Jaggar. * +* Project started on 1st July 1991. * +\***************************************************************************/ + +/* RCS $Revision: 1.13 $ + * Checkin $Date: 1994/02/28 11:33:39 $ + * Revising $Author: hmeekings $ + */ + +#include "armdefs.h" + +extern unsigned ARMul_CoProInit(ARMul_State *state) ; +extern void ARMul_CoProExit(ARMul_State *state) ; +extern void ARMul_CoProAttach(ARMul_State *state, unsigned number, + ARMul_CPInits *init, ARMul_CPExits *exit, + ARMul_LDCs *ldc, ARMul_STCs *stc, + ARMul_MRCs *mrc, ARMul_MCRs *mcr, + ARMul_CDPs *cdp, + ARMul_CPReads *read, ARMul_CPWrites *write, + unsigned char const *regwords) ; +extern void ARMul_CoProDetach(ARMul_State *state, unsigned number) ; + + +/***************************************************************************\ +* Dummy Co-processors * +\***************************************************************************/ + +static unsigned NoCoPro3R(ARMul_State *state,unsigned,ARMword) ; +static unsigned NoCoPro4R(ARMul_State *state,unsigned,ARMword,ARMword) ; +static unsigned NoCoPro4W(ARMul_State *state,unsigned,ARMword,ARMword *) ; + +/***************************************************************************\ +* Define Co-Processor instruction handlers here * +\***************************************************************************/ + +/* Here's ARMulator's MMU definition. A few things to note: +1) it has eight registers, but only two are defined. +2) you can only access its registers with MCR and MRC. +3) MMU Register 0 (ID) returns 0x41440110 +4) Register 1 only has 4 bits defined. Bits 0 to 3 are unused, bit 4 +controls 32/26 bit program space, bit 5 controls 32/26 bit data space, +bit 6 controls late abort timimg and bit 7 controls big/little endian. +*/ + +static ARMword MMUReg[8] ; +static const unsigned char MMURegWords[] = {8,1,1,1,1,1,1,1,1}; + +static unsigned MMUInit(ARMul_State *state) +{MMUReg[1] = state->prog32Sig << 4 | + state->data32Sig << 5 | + state->lateabtSig << 6 | + state->bigendSig << 7 ; + ARMul_ConsolePrint(state, ", MMU present") ; + return(TRUE) ; +} + +static unsigned MMUMRC(ARMul_State *state, unsigned type, ARMword instr,ARMword *value) +{int reg = (int)(BITS(16,19) & 7) ; + + if (reg == 0) + *value = 0x41440110 ; + else + *value = MMUReg[reg] ; + return(ARMul_DONE) ; + } + +static unsigned MMUMCR(ARMul_State *state, unsigned type, ARMword instr, ARMword value) +{int reg = (int)(BITS(16,19) & 7) ; + + MMUReg[reg] = value ; + if (reg == 1) { + state->prog32Sig = (unsigned)((value >> 4) & 1) ; + state->data32Sig = (unsigned)((value >> 5) & 1) ; + state->lateabtSig = (unsigned)((value >> 6) & 1) ; + state->bigendSig = (unsigned)((value >> 7) & 1) ; + state->Emulate = TRUE ; /* force ARMulator to notice these now !*/ + } + return(ARMul_DONE) ; + } + + +static unsigned MMURead(ARMul_State *state, unsigned reg, ARMword *value) +{if (reg == 0) + *value = 0x41440110 ; + else if (reg < 8) + *value = MMUReg[reg] ; + return(TRUE) ; + } + +static unsigned MMUWrite(ARMul_State *state, unsigned reg, ARMword const *valp) +{ARMword value = *valp; + if (reg < 8) + MMUReg[reg] = value ; + if (reg == 1) { + state->prog32Sig = (unsigned)((value >> 4) & 1) ; + state->data32Sig = (unsigned)((value >> 5) & 1) ; + state->lateabtSig = (unsigned)((value >> 6) & 1) ; + state->bigendSig = (unsigned)((value >> 7) & 1) ; + state->Emulate = TRUE ; /* force ARMulator to notice these now !*/ + } + return(TRUE) ; + } + + +/* What follows is the Validation Suite Coprocessor. It uses two +co-processor numbers (4 and 5) and has the follwing functionality. +Sixteen registers. Both co-processor nuimbers can be used in an MCR and +MRC to access these registers. CP 4 can LDC and STC to and from the +registers. CP 4 and CP 5 CDP 0 will busy wait for the number of cycles +specified by a CP register. CP 5 CDP 1 issues a FIQ after a number of +cycles (specified in a CP register), CDP 2 issues an IRQW in the same +way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5 stores a 32 +bit time value in a CP register (actually it's the total number of N, S, +I, C and F cyles) */ + +static ARMword ValReg[16] ; + +static unsigned ValLDC(ARMul_State *state, unsigned type, + ARMword instr, ARMword data) +{static unsigned words ; + + if (type != ARMul_DATA) { + words = 0 ; + return(ARMul_DONE) ; + } + if (BIT(22)) { /* it's a long access, get two words */ + ValReg[BITS(12,15)] = data ; + if (words++ == 4) + return(ARMul_DONE) ; + else + return(ARMul_INC) ; + } + else { /* get just one word */ + ValReg[BITS(12,15)] = data ; + return(ARMul_DONE) ; + } + } + +static unsigned ValSTC(ARMul_State *state, unsigned type, + ARMword instr, ARMword *data) +{static unsigned words ; + + if (type != ARMul_DATA) { + words = 0 ; + return(ARMul_DONE) ; + } + if (BIT(22)) { /* it's a long access, get two words */ + *data = ValReg[BITS(12,15)] ; + if (words++ == 4) + return(ARMul_DONE) ; + else + return(ARMul_INC) ; + } + else { /* get just one word */ + *data = ValReg[BITS(12,15)] ; + return(ARMul_DONE) ; + } + } + +static unsigned ValMRC(ARMul_State *state, unsigned type, ARMword instr,ARMword *value) +{ + *value = ValReg[BITS(16,19)] ; + return(ARMul_DONE) ; + } + +static unsigned ValMCR(ARMul_State *state, unsigned type, ARMword instr, ARMword value) +{ + ValReg[BITS(16,19)] = value ; + return(ARMul_DONE) ; + } + +static unsigned ValCDP(ARMul_State *state, unsigned type, ARMword instr) +{ + static unsigned long finish = 0 ; + ARMword howlong ; + + howlong = ValReg[BITS(0,3)] ; + if (BITS(20,23)==0) { + if (type == ARMul_FIRST) { /* First cycle of a busy wait */ + finish = ARMul_Time(state) + howlong ; + if (howlong == 0) + return(ARMul_DONE) ; + else + return(ARMul_BUSY) ; + } + else if (type == ARMul_BUSY) { + if (ARMul_Time(state) >= finish) + return(ARMul_DONE) ; + else + return(ARMul_BUSY) ; + } + } + return(ARMul_CANT) ; + } + +static unsigned DoAFIQ(ARMul_State *state) +{state->NfiqSig = LOW ; + state->Exception++ ; + return(0) ; +} + +static unsigned DoAIRQ(ARMul_State *state) +{state->NirqSig = LOW ; + state->Exception++ ; + return(0) ; +} + +static unsigned IntCDP(ARMul_State *state, unsigned type, ARMword instr) +{static unsigned long finish ; + ARMword howlong ; + + howlong = ValReg[BITS(0,3)] ; + switch((int)BITS(20,23)) { + case 0 : if (type == ARMul_FIRST) { /* First cycle of a busy wait */ + finish = ARMul_Time(state) + howlong ; + if (howlong == 0) + return(ARMul_DONE) ; + else + return(ARMul_BUSY) ; + } + else if (type == ARMul_BUSY) { + if (ARMul_Time(state) >= finish) + return(ARMul_DONE) ; + else + return(ARMul_BUSY) ; + } + return(ARMul_DONE) ; + case 1 : if (howlong == 0) + ARMul_Abort(state,ARMul_FIQV) ; + else + ARMul_ScheduleEvent(state,howlong,DoAFIQ) ; + return(ARMul_DONE) ; + case 2 : if (howlong == 0) + ARMul_Abort(state,ARMul_IRQV) ; + else + ARMul_ScheduleEvent(state,howlong,DoAIRQ) ; + return(ARMul_DONE) ; + case 3 : state->NfiqSig = HIGH ; + state->Exception-- ; + return(ARMul_DONE) ; + case 4 : state->NirqSig = HIGH ; + state->Exception-- ; + return(ARMul_DONE) ; + case 5 : ValReg[BITS(0,3)] = ARMul_Time(state) ; + return(ARMul_DONE) ; + } + return(ARMul_CANT) ; + } + +/***************************************************************************\ +* Install co-processor instruction handlers in this routine * +\***************************************************************************/ + +unsigned ARMul_CoProInit(ARMul_State *state) +{register unsigned i ; + + for (i = 0 ; i < 16 ; i++) /* initialise tham all first */ + ARMul_CoProDetach(state, i) ; + + /* Install CoPro Instruction handlers here + The format is + ARMul_CoProAttach(state, CP Number, Init routine, Exit routine + LDC routine, STC routine, MRC routine, MCR routine, + CDP routine, Read Reg routine, Write Reg routine, + Register size array) ; + */ + + ARMul_CoProAttach(state, 4, NULL, NULL, + ValLDC, ValSTC, ValMRC, ValMCR, + ValCDP, NULL, NULL, NULL) ; + + ARMul_CoProAttach(state, 5, NULL, NULL, + NULL, NULL, ValMRC, ValMCR, + IntCDP, NULL, NULL, NULL) ; + + ARMul_CoProAttach(state, 15, MMUInit, NULL, + NULL, NULL, MMUMRC, MMUMCR, + NULL, MMURead, MMUWrite, MMURegWords) ; + + + /* No handlers below here */ + + for (i = 0 ; i < 16 ; i++) /* Call all the initialisation routines */ + if (state->CPInit[i]) + (state->CPInit[i])(state) ; + return(TRUE) ; + } + +/***************************************************************************\ +* Install co-processor finalisation routines in this routine * +\***************************************************************************/ + +void ARMul_CoProExit(ARMul_State *state) +{register unsigned i ; + + for (i = 0 ; i < 16 ; i++) + if (state->CPExit[i]) + (state->CPExit[i])(state) ; + for (i = 0 ; i < 16 ; i++) /* Detach all handlers */ + ARMul_CoProDetach(state, i) ; + } + +/***************************************************************************\ +* Routines to hook Co-processors into ARMulator * +\***************************************************************************/ + +void ARMul_CoProAttach(ARMul_State *state, unsigned number, + ARMul_CPInits *init, ARMul_CPExits *exit, + ARMul_LDCs *ldc, ARMul_STCs *stc, + ARMul_MRCs *mrc, ARMul_MCRs *mcr, ARMul_CDPs *cdp, + ARMul_CPReads *read, ARMul_CPWrites *write, + unsigned char const *regwords) +{if (init != NULL) + state->CPInit[number] = init ; + if (exit != NULL) + state->CPExit[number] = exit ; + if (ldc != NULL) + state->LDC[number] = ldc ; + if (stc != NULL) + state->STC[number] = stc ; + if (mrc != NULL) + state->MRC[number] = mrc ; + if (mcr != NULL) + state->MCR[number] = mcr ; + if (cdp != NULL) + state->CDP[number] = cdp ; + if (read != NULL) + state->CPRead[number] = read ; + if (write != NULL) + state->CPWrite[number] = write ; + state->CPRegWords[number] = regwords == NULL ? NULL : regwords+1; +} + +void ARMul_CoProDetach(ARMul_State *state, unsigned number) +{ARMul_CoProAttach(state, number, NULL, NULL, + NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R, + NoCoPro3R, NULL, NULL, NULL) ; + state->CPInit[number] = NULL ; + state->CPExit[number] = NULL ; + state->CPRead[number] = NULL ; + state->CPWrite[number] = NULL ; +} + +/***************************************************************************\ +* There is no CoPro around, so Undefined Instruction trap * +\***************************************************************************/ + +static unsigned NoCoPro3R(ARMul_State *state,unsigned a,ARMword b) +{return(ARMul_CANT) ;} + +static unsigned NoCoPro4R(ARMul_State *state, unsigned a,ARMword b,ARMword c) +{return(ARMul_CANT) ;} + +static unsigned NoCoPro4W(ARMul_State *state, unsigned a,ARMword b,ARMword *c) +{return(ARMul_CANT) ;} + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMDEFS.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMDEFS.H new file mode 100644 index 0000000..8f35bfa --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMDEFS.H @@ -0,0 +1,509 @@ +/***************************************************************************\ +* armdefs.h * +* ARMulator II environment definitions. * +* Copyright (C) Advanced RISC Machines Limited. All rights reserved. * +* Written by Dave Jaggar. * +\***************************************************************************/ + +/* RCS $Revision: 1.30.2.1 $ + * Checkin $Date: 1995/05/14 13:00:08 $ + * Revising $Author: plg $ + */ + +#include +#include + +#define LOW 0 +#define HIGH 1 +#define LOWHIGH 1 +#define HIGHLOW 2 + +#include "host.h" + +typedef unsigned32 ARMword; /* must be 32 bits wide */ + +typedef struct ARMul_State ARMul_State ; +typedef struct MemDescr MemDescr; + +typedef struct EventNode EventNode; + +typedef unsigned ARMul_CPInits(ARMul_State *state) ; +typedef unsigned ARMul_CPExits(ARMul_State *state) ; +typedef unsigned ARMul_LDCs(ARMul_State *state,unsigned type,ARMword instr,ARMword value) ; +typedef unsigned ARMul_STCs(ARMul_State *state,unsigned type,ARMword instr,ARMword *value) ; +typedef unsigned ARMul_MRCs(ARMul_State *state,unsigned type,ARMword instr,ARMword *value) ; +typedef unsigned ARMul_MCRs(ARMul_State *state,unsigned type,ARMword instr,ARMword value) ; +typedef unsigned ARMul_CDPs(ARMul_State *state,unsigned type,ARMword instr) ; +typedef unsigned ARMul_CPReads(ARMul_State *state,unsigned reg,ARMword *value) ; +typedef unsigned ARMul_CPWrites(ARMul_State *state,unsigned reg,ARMword const *value) ; +typedef void ARMul_ModeChangeUpcall(ARMul_State *state, ARMword oldmode, ARMword newmode); + +#include "dbg_stat.h" + +struct MemDescr { + MemDescr *next; + RDI_MemDescr md; + RDI_MemAccessStats a; + int ns_LoadInstrS; + int ns_LoadInstrN; + int ns_LoadInstr16S; + int ns_LoadInstr16N; + int ns_LoadWordS; + int ns_LoadWordN; + int ns_LoadHalfWord; + int ns_LoadByte; + int ns_StoreWordS; + int ns_StoreWordN; + int ns_StoreHalfWord; + int ns_StoreByte; + int ns_SwapWord; + int ns_SwapByte; +}; + +struct ARMul_State { + unsigned Processor ; /* type of ARM we are emulating */ + unsigned Instruction_set ; /* 1=16 bits or 0=32, added for thumb */ + ARMword Emulate ; /* to start and stop emulation */ + unsigned EndCondition ; /* reason for stopping */ + unsigned ErrorCode ; /* type of illegal instruction */ + ARMword Reg[16] ; /* the current register file */ + ARMword RegBank[7][16] ; /* all the registers */ + ARMword Cpsr ; /* the current psr */ + ARMword Spsr[7] ; /* the exception psr's */ + ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags ; /* dummy flags for speed */ + ARMword Bank ; /* the current register bank */ + ARMword Mode ; /* the current mode */ + ARMword instr, pc, temp ; /* saved register state */ + ARMword loaded, decoded ; /* saved pipeline state */ + unsigned long NumScycles, + NumNcycles, + NumIcycles, + NumCcycles, + NumFcycles ; /* emulated cycles used */ + unsigned long NumInstrs ; /* the number of instructions executed */ + unsigned long cpu_ns; + unsigned long ns, s; + unsigned NextInstr ; + unsigned VectorCatch ; /* caught exception mask */ + unsigned CallDebug ; /* set to call the debugger */ + unsigned CanWatch ; /* set by memory interface if its willing to suffer the + overhead of checking for watchpoints on each memory + access */ + unsigned MemReadDebug, MemWriteDebug ; + unsigned long StopHandle ; + + unsigned char *MemDataPtr ; /* admin data */ + MemDescr *MemInfoPtr ; + unsigned char *MemInPtr ; /* the Data In bus */ + unsigned char *MemOutPtr ; /* the Data Out bus (which you may not need */ + unsigned char *MemSparePtr ; /* extra space */ + ARMword MemSize ; + + unsigned char *OSptr ; /* OS Handle */ + char *CommandLine ; /* Command Line from ARMsd */ + + ARMul_CPInits *CPInit[16] ; /* coprocessor initialisers */ + ARMul_CPExits *CPExit[16] ; /* coprocessor finalisers */ + ARMul_LDCs *LDC[16] ; /* LDC instruction */ + ARMul_STCs *STC[16] ; /* STC instruction */ + ARMul_MRCs *MRC[16] ; /* MRC instruction */ + ARMul_MCRs *MCR[16] ; /* MCR instruction */ + ARMul_CDPs *CDP[16] ; /* CDP instruction */ + ARMul_CPReads *CPRead[16] ; /* Read CP register */ + ARMul_CPWrites *CPWrite[16] ; /* Write CP register */ + unsigned char *CPData[16] ; /* Coprocessor data */ + unsigned char const *CPRegWords[16] ; /* map of coprocessor register sizes */ + + unsigned EventSet ; /* the number of events in the queue */ + unsigned long Now ; /* time to the nearest cycle */ + EventNode **EventPtr ; /* the event list */ + + unsigned Exception ; /* enable the next four values */ + unsigned Debug ; /* show instructions as they are executed */ + unsigned NresetSig ; /* reset the processor */ + unsigned NfiqSig ; + unsigned NirqSig ; + + unsigned abortSig ; + unsigned NtransSig ; + unsigned bigendSig ; + unsigned prog32Sig ; + unsigned data32Sig ; + unsigned lateabtSig ; + ARMword Vector ; /* synthesize aborts in cycle modes */ + ARMword Aborted ; /* sticky flag for aborts */ + ARMword Reseted ; /* sticky flag for Reset */ + ARMword Inted, LastInted ; /* sticky flags for interrupts */ + ARMword Base ; /* extra hand for base writeback */ + ARMword AbortAddr ; /* to keep track of Prefetch aborts */ + +#ifdef CYCLEBASED + unsigned NextCycle ; /* the position in the state machine */ + ARMword TempReg[16] ; /* undo aborts with these */ + unsigned NumCycles ; /* counter for state iterations */ + ARMword Temp ; /* sometimes you just need an extra hand */ + + ARMword addrBus ; + ARMword datainBus ; + ARMword dataoutBus ; + unsigned mas0Sig; /* Thumb memory access size mas[0] */ + unsigned NbwSig ; /* = mas[1] */ + unsigned NrwSig ; + unsigned seqSig ; + unsigned NmreqSig ; + unsigned NopcSig ; + unsigned NexecSig ; + unsigned lockSig ; + unsigned NmBus ; + unsigned NcpiSig ; + unsigned cpaSig ; + unsigned cpbSig ; + unsigned doutenSig ; /* synthesize NENOUT with this plus DBE */ + + unsigned LSCActive ; /* LDC or STC is happening */ + ARMword addr01Bus ; /* used to fake the bottom two bits of address */ + unsigned LastCycle ; /* so you can know what you did last */ + ARMword NextaddrBus ; /* extra hands for the coprocessor fix up routine */ + unsigned NextNrwSig ; + unsigned NextseqSig ; + unsigned NextNmreqSig ; + unsigned NextNopcSig ; + ARMword PrevaddrBus ; + unsigned PrevNrwSig ; + ARMword OldBase ; /* undo aborts with this */ + + unsigned mclkSig ; + unsigned NwaitSig ; + unsigned tdiSig, tdoSig, tmsSig, NtrstSig ; /* Boundary scan interface */ + char *TAPDataPtr ; + struct ARMul_State *Core ; /* used when in BS test mode */ + ARMword BSID ; /* the boundary scan identification number */ +#endif + + const struct Dbg_HostosInterface *hostif; + + ARMul_ModeChangeUpcall *ModeChange; + unsigned clearAborts; /* Set this <>0 to have aborts cleared for you */ + + unsigned fpe; /* 0 if fpe shouldn't be/isn't loaded */ + } ; + +#define ResetPin NresetSig +#define FIQPin NfiqSig +#define IRQPin NirqSig +#define AbortPin abortSig +#define TransPin NtransSig +#define BigEndPin bigendSig +#define Prog32Pin prog32Sig +#define Data32Pin data32Sig +#define LateAbortPin lateabtSig +#ifdef CYCLEBASED +#define AddrBus addrBus +#define DataInBus datainBus +#define DataOutBus dataoutBus +#define BWPin NbwSig +#define RWPin NrwSig +#define SeqPin seqSig +#define MreqPin NmreqSig +#define OpcPin NopcSig +#define ExecPin NexecSig +#define LockPin lockSig +#define ModePins NmBus +#define CPIPin NcpiSig +#define CPAPin cpaSig +#define CPBPin cpbSig +#define TDIPin tdiSig +#define TDOPin tdoSig +#define TMSPin tmsSig +#define NTRSTPin NtrstSig +#endif + +/***************************************************************************\ +* Types of ARM we know about * +\***************************************************************************/ + +/* The bitflags */ +#define ARM_Fix26_Prop 0x01 +#define ARM_Nexec_Prop 0x02 +#define ARM_Abort7_Prop 0x04 +#define ARM_Mult64_Prop 0x08 +#define ARM_Debug_Prop 0x10 +#define ARM_Isync_Prop ARM_Debug_Prop +#define ARM_Lock_Prop 0x20 +#define ARM_Halfword_Prop 0x40 +#define ARM_Code16_Prop 0x80 +#define ARM_System32_Prop 0x100 + +/* ARM2 family */ +#define ARM2 (ARM_Fix26_Prop) +#define ARM2as ARM2 +#define ARM61 ARM2 +#define ARM3 ARM2 + +/* ARM6 family */ +#define ARM6 (ARM_Lock_Prop) +#define ARM60 ARM6 +#define ARM600 ARM6 +#define ARM610 ARM6 +#define ARM620 ARM6 + +/* ARM7 family */ +#define ARM7 (ARM_Nexec_Prop | ARM_Abort7_Prop) +#define ARM70 ARM7 +#define ARM700 ARM7 +/* ...with debug */ +#define ARM7d (ARM7 | ARM_Debug_Prop) +#define ARM70d ARM7d +/* ...with extended multiply */ +#define ARM7dm (ARM7d | ARM_Mult64_Prop) +#define ARM70dm ARM7dm +/* ...with halfwords and 16 bit instruction set and system mode */ +#define ARM7tdm (ARM7dm | ARM_Halfword_Prop | ARM_Code16_Prop | ARM_System32_Prop) + +/***************************************************************************\ +* Macros to extract instruction fields * +\***************************************************************************/ + +#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */ +#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */ +#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */ + +/***************************************************************************\ +* The hardware vector addresses * +\***************************************************************************/ + +#define ARMResetV 0L +#define ARMUndefinedInstrV 4L +#define ARMSWIV 8L +#define ARMPrefetchAbortV 12L +#define ARMDataAbortV 16L +#define ARMAddrExceptnV 20L +#define ARMIRQV 24L +#define ARMFIQV 28L +#define ARMErrorV 32L /* This is an offset, not an address ! */ + +#define ARMul_ResetV ARMResetV +#define ARMul_UndefinedInstrV ARMUndefinedInstrV +#define ARMul_SWIV ARMSWIV +#define ARMul_PrefetchAbortV ARMPrefetchAbortV +#define ARMul_DataAbortV ARMDataAbortV +#define ARMul_AddrExceptnV ARMAddrExceptnV +#define ARMul_IRQV ARMIRQV +#define ARMul_FIQV ARMFIQV + +/***************************************************************************\ +* Mode and Bank Constants * +\***************************************************************************/ + +#define USER26MODE 0L +#define FIQ26MODE 1L +#define IRQ26MODE 2L +#define SVC26MODE 3L +#define USER32MODE 16L +#define FIQ32MODE 17L +#define IRQ32MODE 18L +#define SVC32MODE 19L +#define ABORT32MODE 23L +#define UNDEF32MODE 27L +#define SYSTEM32MODE 31L + +#define ARM32BITMODE (state->Mode > 3) +#define ARM26BITMODE (state->Mode <= 3) +#define ARMMODE (state->Mode) +#define ARMul_MODEBITS 0x1fL +#define ARMul_MODE32BIT ARM32BITMODE +#define ARMul_MODE26BIT ARM26BITMODE + +#define USERBANK 0 +#define FIQBANK 1 +#define IRQBANK 2 +#define SVCBANK 3 +#define ABORTBANK 4 +#define UNDEFBANK 5 +#define DUMMYBANK 6 + +/***************************************************************************\ +* Definitions of things in the emulator * +\***************************************************************************/ + +extern void ARMul_EmulateInit(void) ; +extern ARMul_State *ARMul_NewState(void) ; +extern void ARMul_Reset(ARMul_State *state) ; +extern void ARMul_SelectProcessor(ARMul_State *state, unsigned processor) ; +#ifdef CYCLEBASED +extern ARMword ARMul_DoCycle(ARMul_State *state) ; +extern unsigned ARMul_DoCoPro(ARMul_State *state) ; +#else +extern ARMword ARMul_DoProg(ARMul_State *state) ; +extern ARMword ARMul_DoInstr(ARMul_State *state) ; +#endif + +/***************************************************************************\ +* Definitions of things for event handling * +\***************************************************************************/ + +extern void ARMul_ScheduleEvent(ARMul_State *state, unsigned long delay, unsigned (*func)() ) ; +extern void ARMul_InvokeEvent(ARMul_State *state) ; +extern unsigned long ARMul_Time(ARMul_State *state) ; + +/***************************************************************************\ +* Useful support routines * +\***************************************************************************/ + +extern ARMword ARMul_GetReg(ARMul_State *state, unsigned mode, unsigned reg) ; +extern void ARMul_SetReg(ARMul_State *state, unsigned mode, unsigned reg, ARMword value) ; +extern ARMword ARMul_GetPC(ARMul_State *state) ; +extern ARMword ARMul_GetNextPC(ARMul_State *state) ; +extern void ARMul_SetPC(ARMul_State *state, ARMword value) ; +extern ARMword ARMul_GetR15(ARMul_State *state) ; +extern void ARMul_SetR15(ARMul_State *state, ARMword value) ; + +extern ARMword ARMul_GetCPSR(ARMul_State *state) ; +extern void ARMul_SetCPSR(ARMul_State *state, ARMword value) ; +extern ARMword ARMul_GetSPSR(ARMul_State *state, ARMword mode) ; +extern void ARMul_SetSPSR(ARMul_State *state, ARMword mode, ARMword value) ; + +/***************************************************************************\ +* Definitions of things to handle aborts * +\***************************************************************************/ + +extern void ARMul_Abort(ARMul_State *state, ARMword address) ; +#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */ +#ifdef CODE16 +#define ARMul_PREFETCHABORT(address) \ + if (state->AbortAddr == 1) \ + state->AbortAddr = (address & (INSTRUCTION16STATE ? ~1L : ~3L)) +#else +#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \ + state->AbortAddr = (address & ~3L) +#endif +#define ARMul_DATAABORT(address) state->abortSig = HIGH ; \ + state->Aborted = ARMul_DataAbortV ; +#define ARMul_CLEARABORT state->abortSig = LOW + +#ifndef CYCLEBASED + +/***************************************************************************\ +* Definitions of things in the memory interface * +\***************************************************************************/ + +extern unsigned ARMul_MemoryInit(ARMul_State *state,unsigned long initmemsize) ; +extern void ARMul_MemoryExit(ARMul_State *state) ; + +extern ARMword ARMul_LoadInstrS(ARMul_State *state,ARMword address) ; +extern ARMword ARMul_LoadInstrN(ARMul_State *state,ARMword address) ; + +extern ARMword ARMul_LoadWordS(ARMul_State *state,ARMword address) ; +extern ARMword ARMul_LoadWordN(ARMul_State *state,ARMword address) ; +extern ARMword ARMul_LoadByte(ARMul_State *state,ARMword address) ; + +extern void ARMul_StoreWordS(ARMul_State *state,ARMword address, ARMword data) ; +extern void ARMul_StoreWordN(ARMul_State *state,ARMword address, ARMword data) ; +extern void ARMul_StoreByte(ARMul_State *state,ARMword address, ARMword data) ; + +extern ARMword ARMul_LoadInstr16S(ARMul_State *state,ARMword address) ; +extern ARMword ARMul_LoadInstr16N(ARMul_State *state,ARMword address) ; +extern ARMword ARMul_LoadHalfWord(ARMul_State *state,ARMword address) ; +extern void ARMul_StoreHalfWord(ARMul_State *state,ARMword address, ARMword data) ; +extern ARMword ARMul_ReadHalfWord(ARMul_State *state,ARMword address) ; +extern void ARMul_WriteHalfWord(ARMul_State *state,ARMword address, ARMword data) ; + +extern ARMword ARMul_SwapWord(ARMul_State *state,ARMword address, ARMword data) ; +extern ARMword ARMul_SwapByte(ARMul_State *state,ARMword address, ARMword data) ; + +extern void ARMul_Icycles(ARMul_State *state,unsigned number, ARMword address) ; +extern void ARMul_Ccycles(ARMul_State *state,unsigned number, ARMword address) ; + +extern ARMword ARMul_ReadWord(ARMul_State *state,ARMword address) ; +extern ARMword ARMul_ReadByte(ARMul_State *state,ARMword address) ; +extern void ARMul_WriteWord(ARMul_State *state,ARMword address, ARMword data) ; +extern void ARMul_WriteByte(ARMul_State *state,ARMword address, ARMword data) ; + +extern ARMword ARMul_MemAccess(ARMul_State *state,ARMword,ARMword,ARMword, + ARMword,ARMword,ARMword,ARMword,ARMword,ARMword,ARMword,ARMword) ; + +/***************************************************************************\ +* Definitions of things in the co-processor interface * +\***************************************************************************/ + +#define ARMul_FIRST 0 +#define ARMul_TRANSFER 1 +#define ARMul_BUSY 2 +#define ARMul_DATA 3 +#define ARMul_INTERRUPT 4 +#define ARMul_DONE 0 +#define ARMul_CANT 1 +#define ARMul_INC 3 + +extern unsigned ARMul_CoProInit(ARMul_State *state) ; +extern void ARMul_CoProExit(ARMul_State *state) ; +extern void ARMul_CoProAttach(ARMul_State *state, unsigned number, + ARMul_CPInits *init, ARMul_CPExits *exit, + ARMul_LDCs *ldc, ARMul_STCs *stc, + ARMul_MRCs *mrc, ARMul_MCRs *mcr, + ARMul_CDPs *cdp, + ARMul_CPReads *read, ARMul_CPWrites *write, + unsigned char const *regwords) ; +extern void ARMul_CoProDetach(ARMul_State *state, unsigned number) ; + +/***************************************************************************\ +* Definitions of things in the host environment * +\***************************************************************************/ + +extern unsigned ARMul_OSInit(ARMul_State *state) ; +extern void ARMul_OSExit(ARMul_State *state) ; +extern unsigned ARMul_OSHandleSWI(ARMul_State *state,ARMword number) ; +extern ARMword ARMul_OSLastErrorP(ARMul_State *state) ; +#else +char *ARMul_Disass(ARMword instr, ARMword address, ARMword cpsr) ; +extern char *ARMul_ErrorMess(ARMul_State *state,unsigned number) ; +#define UNDEF_BadInstruction 132 +#define UNDEF_IllInstruction 133 +#endif /* CYCLEBASED */ + +extern ARMword ARMul_Debug(ARMul_State *state, ARMword pc, ARMword instr) ; +extern void ARMul_CheckWatch(ARMul_State *state, ARMword addr, int access) ; + +extern unsigned ARMul_OSException(ARMul_State *state, ARMword vector, ARMword pc) ; +extern void ARMul_DebugPrint(ARMul_State *state, const char *format, ...); +extern void ARMul_DebugPause(ARMul_State *state); +extern void ARMul_ConsolePrint(ARMul_State *state, const char *format, ...); + +/* IF the macro HOURGLASS_RATE is defined, then you must provide this fn */ +#ifdef HOURGLASS_RATE +extern void armsd_hourglass(void); +#endif + +/***************************************************************************\ +* ARM / THUMB differences * +\***************************************************************************/ + +#define INSTRUCTION32SIZE (4) +#define INSTRUCTION32 (0) + +#ifdef CODE16 +/* state->Instruction_set values */ + +#define INSTRUCTION16 (1) + +#define INSTRUCTION16STATE (state->Instruction_set == INSTRUCTION16) + +#define INSTRUCTION16SIZE (2) +#define INSTRUCTIONSIZE (INSTRUCTION16STATE ? INSTRUCTION16SIZE : INSTRUCTION32SIZE) + +/* bits in registers */ + +#define BXINSTRUCTIONSETBITS (0x1) +#define CPSRINSTRUCTIONSETBITPOSN (5) +#define CPSRINSTRUCTIONSETBITS (0x1 << CPSRINSTRUCTIONSETBITPOSN) + +#define BXINSTRUCTIONSET(r) ((r & BXINSTRUCTIONSETBITS) ? INSTRUCTION16 : INSTRUCTION32) +#define CPSRINSTRUCTIONSET(r) ((r & CPSRINSTRUCTIONSETBITS) ? INSTRUCTION16 : INSTRUCTION32) +#define CPSRINSTRUCTIONSIZE(r) ((r & CPSRINSTRUCTIONSETBITS) ? INSTRUCTION16SIZE : INSTRUCTION32SIZE) + +#else +#define INSTRUCTIONSIZE INSTRUCTION32SIZE +#define CPSRINSTRUCTIONSET(r) (INSTRUCTION32) +#define CPSRINSTRUCTIONSIZE(r) (INSTRUCTION32SIZE) +#endif + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFAST.C b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFAST.C new file mode 100644 index 0000000..4f31123 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFAST.C @@ -0,0 +1,365 @@ +/***************************************************************************\ +* armfast.c * +* Version 1.20 * +* ARMulator II Simple Memory Interface. * +* Copyright (C) 1991 Advanced RISC Machines Limited. All rights reserved. * +* Written by Dave Jaggar. * +* Project started on 1st July 1991. * +\***************************************************************************/ + +/* + * RCS $Revision: 1.14 $ + * Checkin $Date: 1995/01/18 12:26:52 $ + * Revising $Author: hmeekings $ + */ + +/* This file contains the fastest of example ARMulator memory systems. +It implements the ARM's memory as a fixed size block of host memory, and +does endian switching for byte accesses only. Memory accesses outside +the memory block are truncated to the size of the memory block. Each +routine is almost a cut-and-paste of some other, it's all quite simple */ +/* Halfwords added 940909 by Andy Chapman */ + +#include "armdefs.h" + +#define DEFMEMSIZE (512 * 1024) /* default memory size, must be a power of 2 */ +#define WORDWRAP (DEFMEMSIZE - 4) +#define HWORDWRAP (DEFMEMSIZE - 2) +#define BYTEWRAP (DEFMEMSIZE - 1) + +#define WORDMASK(addr) (addr & WORDWRAP) +#define HWORDMASK(addr) (addr & HWORDWRAP) +#define BYTEMASK(addr) (addr & BYTEWRAP) +#define ENDSWAP(addr) (addr ^ 3) +#define ENDSWAPH(addr) (addr ^ 2) +#define ENDSWAPB(addr) (addr ^ 1) +static unsigned HostEndian ; + +#ifdef DOWATCH +#include "dbg_rdi.h" +#endif + +/***************************************************************************\ +* Initialise the memory interface * +\***************************************************************************/ + +unsigned ARMul_MemoryInit(ARMul_State *state, unsigned long initmemsize) +{unsigned char *Memory ; + + if (initmemsize == 0 || initmemsize > DEFMEMSIZE) + initmemsize = DEFMEMSIZE ; + state->MemSize = initmemsize ; + Memory = (unsigned char *)malloc(DEFMEMSIZE) ; + if (Memory == NULL) + return(FALSE) ; + state->MemInPtr = Memory ; + *(ARMword *)Memory = 1 ; + HostEndian = (*Memory != 1) ; /* 1 for big endian, 0 for little */ +#ifdef BIGEND + state->bigendSig = HIGH ; +#endif +#ifdef LITTLEEND + state->bigendSig = LOW ; +#endif + ARMul_ConsolePrint(state, ", %d Kb RAM",state->MemSize/1024) ; +#ifdef DOWATCH + state->CanWatch = TRUE ; +#endif + return(TRUE) ; +} + +/***************************************************************************\ +* Remove the memory interface * +\***************************************************************************/ + +void ARMul_MemoryExit(ARMul_State *state) +{free((char *)state->MemInPtr) ; + return ; + } + +/***************************************************************************\ +* Load Instruction, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstrS(ARMul_State *state,ARMword address) +{state->NumScycles++ ; + +#ifdef DOWATCH + if (state->MemReadDebug) ARMul_CheckWatch(state, address, RDIWatch_WordRead); +#endif + +#ifdef HOURGLASS_RATE + if( (state->NumScycles & HOURGLASS_RATE) == 0 ) { + armsd_hourglass(); + } +#endif + + return( *(ARMword *)(state->MemInPtr + WORDMASK(address)) ) ; +} + +/***************************************************************************\ +* Load Instruction, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstrN(ARMul_State *state,ARMword address) +{state->NumNcycles++ ; +#ifdef DOWATCH + if (state->MemReadDebug) ARMul_CheckWatch(state, address, RDIWatch_WordRead); +#endif + return( *(ARMword *)(state->MemInPtr + WORDMASK(address)) ) ; +} + +/***************************************************************************\ +* Load 16 Bit Instruction, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstr16S(ARMul_State *state,ARMword address) +{state->NumScycles++ ; + +#ifdef HOURGLASS_RATE + if( (state->NumScycles & HOURGLASS_RATE) == 0 ) { + armsd_hourglass(); + } +#endif + + return( (*(ARMword *)(state->MemInPtr + WORDMASK(address))) >> + ((((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3) & + 0xffffL ) ; +} + +/***************************************************************************\ +* Load 16 Bit Instruction, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstr16N(ARMul_State *state,ARMword address) +{state->NumNcycles++ ; + return( (*(ARMword *)(state->MemInPtr + WORDMASK(address))) >> + ((((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3) & + 0xffffL ) ; +} + +/***************************************************************************\ +* Load Word, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadWordS(ARMul_State *state,ARMword address) +{state->NumScycles++ ; +#ifdef DOWATCH + if (state->MemReadDebug) ARMul_CheckWatch(state, address, RDIWatch_WordRead); +#endif + return( *(ARMword *)(state->MemInPtr + WORDMASK(address)) ) ; +} + +/***************************************************************************\ +* Load Word, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadWordN(ARMul_State *state,ARMword address) +{state->NumNcycles++ ; +#ifdef DOWATCH + if (state->MemReadDebug) ARMul_CheckWatch(state, address, RDIWatch_WordRead); +#endif + return( *(ARMword *)(state->MemInPtr + WORDMASK(address)) ) ; +} + +/***************************************************************************\ +* Load Halfword, (Non Sequential Cycle) * +\***************************************************************************/ + +ARMword ARMul_LoadHalfWord(ARMul_State *state,ARMword address) +{state->NumNcycles++ ; + address = BYTEMASK(address); + if (HostEndian == state->bigendSig) { + return( (ARMword)((*(state->MemInPtr + address) << 8) + + *(state->MemInPtr + ENDSWAPB(address)))) ; + } else { + return( (ARMword)((*(state->MemInPtr + ENDSWAPH(address)) << 8)+ + *(state->MemInPtr + ENDSWAPB(ENDSWAPH(address))))) ; + } +} + +/***************************************************************************\ +* Load Byte, (Non Sequential Cycle) * +\***************************************************************************/ + +ARMword ARMul_LoadByte(ARMul_State *state,ARMword address) +{state->NumNcycles++ ; +#ifdef DOWATCH + if (state->MemReadDebug) ARMul_CheckWatch(state, address, RDIWatch_ByteRead); +#endif + if (HostEndian == state->bigendSig) + return( (ARMword)*(state->MemInPtr + BYTEMASK(address)) ) ; + else + return( (ARMword)*(state->MemInPtr + ENDSWAP(BYTEMASK(address))) ) ; +} + +/***************************************************************************\ +* Store Word, Sequential Cycle * +\***************************************************************************/ + +void ARMul_StoreWordS(ARMul_State *state,ARMword address, ARMword data) +{state->NumScycles++ ; +#ifdef DOWATCH + if (state->MemWriteDebug) ARMul_CheckWatch(state, address, RDIWatch_WordWrite); +#endif + *(ARMword *)(state->MemInPtr + WORDMASK(address)) = data ; +} +/***************************************************************************\ +* Store Word, Sequential Cycle * +\***************************************************************************/ + +void ARMul_StoreWordN(ARMul_State *state,ARMword address, ARMword data) +{state->NumNcycles++ ; +#ifdef DOWATCH + if (state->MemWriteDebug) ARMul_CheckWatch(state, address, RDIWatch_WordWrite); +#endif + *(ARMword *)(state->MemInPtr + WORDMASK(address) ) = data ; +} + +/***************************************************************************\ +* Store HalfWord, (Non Sequential Cycle) * +\***************************************************************************/ + +void ARMul_StoreHalfWord(ARMul_State *state,ARMword address, ARMword data) +{state->NumNcycles++ ; + + address = HWORDMASK(address); + if (HostEndian == state->bigendSig) { + *(state->MemInPtr + address) = (unsigned char)((data & 0xff00) >> 8); + *(state->MemInPtr + address + 1) = (unsigned char)data ; + } else { + *(state->MemInPtr + ENDSWAPH(address)) = (unsigned char)((data & 0xff00) >> 8); + *(state->MemInPtr + ENDSWAPH(address) + 1) = (unsigned char)data ; + } +} + +/***************************************************************************\ +* Store Byte, (Non Sequential Cycle) * +\***************************************************************************/ + +void ARMul_StoreByte(ARMul_State *state,ARMword address, ARMword data) +{state->NumNcycles++ ; +#ifdef DOWATCH + if (state->MemWriteDebug) ARMul_CheckWatch(state, address, RDIWatch_ByteWrite); +#endif + if (HostEndian == state->bigendSig) + *(state->MemInPtr + BYTEMASK(address)) = (unsigned char)data ; + else + *(state->MemInPtr + ENDSWAP(BYTEMASK(address))) = (unsigned char)data ; +} + +/***************************************************************************\ +* Swap Word, (Two Non Sequential Cycles) * +\***************************************************************************/ + +ARMword ARMul_SwapWord(ARMul_State *state,ARMword address, ARMword data) +{ARMword temp ; + + temp = ARMul_LoadWordN(state,address) ; + ARMul_StoreWordN(state,address,data) ; + return(temp) ; +} + +/***************************************************************************\ +* Swap Byte, (Two Non Sequential Cycles) * +\***************************************************************************/ + +ARMword ARMul_SwapByte(ARMul_State *state,ARMword address, ARMword data) +{ARMword temp ; + + temp = ARMul_LoadByte(state,address) ; + ARMul_StoreByte(state,address,data) ; + return(temp) ; +} + +/***************************************************************************\ +* Count I Cycles * +\***************************************************************************/ + +void ARMul_Icycles(ARMul_State *state,unsigned number, ARMword address) +{state->NumIcycles += number ; +} + +/***************************************************************************\ +* Count C Cycles * +\***************************************************************************/ + +void ARMul_Ccycles(ARMul_State *state,unsigned number, ARMword address) +{state->NumCcycles += number ; +} + +/***************************************************************************\ +* Read Word (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadWord(ARMul_State *state,ARMword address) +{ + return( *(ARMword *)(state->MemInPtr + WORDMASK(address)) ) ; +} + +/***************************************************************************\ +* Read Halfword (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadHalfWord(ARMul_State *state,ARMword address) +{ + address = BYTEMASK(address); + if (HostEndian == state->bigendSig) { + return( (ARMword)((*(state->MemInPtr + address) << 8) + + *(state->MemInPtr + ENDSWAPB(address)))) ; + } else { + return( (ARMword)((*(state->MemInPtr + ENDSWAPH(address)) << 8)+ + *(state->MemInPtr + ENDSWAPB(ENDSWAPH(address))))) ; + } +} + +/***************************************************************************\ +* Read Byte (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadByte(ARMul_State *state,ARMword address) +{ + if (HostEndian == state->bigendSig) + return( (ARMword)*(state->MemInPtr + BYTEMASK(address)) ) ; + else + return( (ARMword)*(state->MemInPtr + ENDSWAP(BYTEMASK(address))) ) ; +} + +/***************************************************************************\ +* Write Word (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteWord(ARMul_State *state,ARMword address, ARMword data) +{ + *(ARMword *)(state->MemInPtr + WORDMASK(address)) = data ; +} + +/***************************************************************************\ +* Write Halfword (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteHalfWord(ARMul_State *state,ARMword address, ARMword data) +{ + address = HWORDMASK(address); + if (HostEndian == state->bigendSig) { + *(state->MemInPtr + address) = (unsigned char)((data & 0xff00) >> 8); + *(state->MemInPtr + address + 1) = (unsigned char)data ; + } else { + *(state->MemInPtr + ENDSWAPH(address)) = (unsigned char)((data & 0xff00) >> 8); + *(state->MemInPtr + ENDSWAPH(address) + 1) = (unsigned char)data ; + } +} + +/***************************************************************************\ +* Write Byte (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteByte(ARMul_State *state,ARMword address, ARMword data) +{ + if (HostEndian == state->bigendSig) + *(state->MemInPtr + BYTEMASK(address)) = (unsigned char)data ; + else + *(state->MemInPtr + ENDSWAP(BYTEMASK(address))) = (unsigned char)data ; +} + + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFPE.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFPE.H new file mode 100644 index 0000000..eefaeef --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFPE.H @@ -0,0 +1,1701 @@ +/* + * RCS $Revision: 1.3.2.1 $ + * Checkin $Date: 1995/05/25 08:35:07 $ + * Revising $Author: plg $ + */ + +#include "aif.h" + +static struct { + struct aif_hdr hdr; + unsigned32 code[6698]; +} fpe = { + { +0xe1a00000,0xe1a00000,0xeb00000c,0x00000000, +0xef000011,0x000068a4,0x00000000,0x000001c4, +0x00000000,0x00000001,0x00001400,0x00000000, +0x00000020,0x00000000,0x00000000,0x00000000, +0xe1a00000,0xe04ec00f,0xe08fc00c,0xe99c000f, +0xe24cc010,0xe59c2030,0xe3120c01,0x159cc034, +0x008cc000,0xe08cc001,0xe3a00000,0xe3530000, +0xd1a0f00e,0xe48c0004,0xe2533004,0xeafffffb, + }, + { +0xeb00192d,0xef000011,0x00000000,0x00000000, +0x00000000,0xe24dd040,0xe8cd7fff,0xe58de03c, +0xe1a0c00d,0xe10fa000,0xe14f9000,0xe92d0600, +0xe319000f,0xe24e9004,0x04b9b000,0x1599b000, +0xe28faa06,0xe28aae62,0xe31b0302,0x0a0005b7, +0xe20b9c0f,0xe3590c01,0x1a0004b9,0xe59a8084, +0xe3380000,0x1a0004b0,0xe10f8000,0xe3c88080, +0xe129f008,0xe1a00000,0xe59a7080,0xe31b0402, +0x1a0003ee,0xe1a0948b,0xe209920a,0xe31b0902, +0x13899101,0xe20b380f,0xe353080f,0x23899201, +0xe51c8008,0xe218800f,0x13899302,0xe2095103, +0xe08ffca9,0x00000000,0xea00001e,0xea00003c, +0xea000074,0xea000081,0xea0001c2,0xea0001e6, +0xea000224,0xea00022b,0xea00008a,0xea0000a9, +0xea0000d3,0xea0000e1,0xea00022f,0xea000257, +0xea000298,0xea00029f,0xea0000ea,0xea00010a, +0xea000134,0xea000143,0xea0002a3,0xea0002c9, +0xea000307,0xea00030e,0xea00014c,0xea00015f, +0xea00018c,0xea00019c,0xea000312,0xea000324, +0xea00034c,0xea000353,0xe20b8a07,0xe08a8428, +0xe8980007,0xe1a05ba5,0xeb000581,0xe20b380f, +0xe79c4723,0xe20b80ff,0xe31b0502,0x10848108, +0x00448108,0xe31b0401,0x11a04008,0xe31b0602, +0x178c8723,0xe4a40000,0xe58a7080,0xe59c903c, +0xe3390000,0x14b9b000,0x100b808b,0x13180302, +0x1b000540,0xe91c0300,0xe129f009,0xe169f008, +0xe1a0d00c,0xe8dc7fff,0xe1a00000,0xe28dd03c, +0xe8fd8000,0xe20b8a07,0xe08a8428,0xe8980007, +0xe1a05ba5,0xeb000562,0xe20b380f,0xe353080d, +0x2a000018,0xe79c4723,0xe20b80ff,0xe31b0502, +0x10848108,0x00448108,0xe31b0401,0x11a04008, +0xe31b0602,0x178c8723,0xe8840001,0xe58a7080, +0xe59c903c,0xe3390000,0x1599b000,0x100b808b, +0x13180302,0x1b00051f,0xe91c0300,0xe129f009, +0xe169f008,0xe1a0d00c,0xe8dc7fff,0xe1a00000, +0xe28dd03c,0xe8fd8000,0xe51c8008,0xe218800f, +0xe10f9000,0xe3888090,0xe3c9401f,0xe1848008, +0xe129f008,0xe353080d,0x01a0400d,0x11a0400e, +0xe20b80ff,0xe31b0502,0x10848108,0x00448108, +0xe31b0401,0x11a04008,0xe31b0602,0x0a000002, +0xe353080d,0x01a0d008,0x11a0e008,0xe129f009, +0xe8840001,0xeaffffd8,0xe20b8a07,0xe08a8428, +0xe8980007,0xe1a05ba5,0xeb000529,0xe59c403c, +0xe2844004,0xe31b0401,0x120b80ff,0x10444108, +0x131b0502,0x10844188,0xe4a40000,0xeaffffa9, +0xe20b8a07,0xe08a8428,0xe8980007,0xe1a05ba5, +0xeb00051b,0xe59c403c,0xe2844004,0xe31b0401, +0x120b80ff,0x10444108,0x131b0502,0x10844188, +0xe8840001,0xeaffffbc,0xe20b8a07,0xe08a8428, +0xe8980007,0xe1a05ba5,0xeb000560,0xe20b380f, +0xe79c4723,0xe20b80ff,0xe31b0502,0x10848108, +0x00448108,0xe31b0401,0x11a04008,0xe31b0602, +0x178c8723,0xe4a40004,0xe4241004,0xe58a7080, +0xe59c903c,0xe3390000,0x14b9b000,0x100b808b, +0x13180302,0x1b0004cb,0xe91c0300,0xe129f009, +0xe169f008,0xe1a0d00c,0xe8dc7fff,0xe1a00000, +0xe28dd03c,0xe8fd8000,0xe20b8a07,0xe08a8428, +0xe8980007,0xe1a05ba5,0xeb000540,0xe20b380f, +0xe353080d,0x2a00000a,0xe79c4723,0xe20b80ff, +0xe31b0502,0x10848108,0x00448108,0xe31b0401, +0x11a04008,0xe31b0602,0x178c8723,0xe8840003, +0xeaffff89,0xe51c8008,0xe218800f,0xe10f9000, +0xe3888090,0xe3c9401f,0xe1848008,0xe129f008, +0xe353080d,0x01a0400d,0x11a0400e,0xe20b80ff, +0xe31b0502,0x10848108,0x00448108,0xe31b0401, +0x11a04008,0xe31b0602,0x0a000002,0xe353080d, +0x01a0d008,0x11a0e008,0xe129f009,0xe8840003, +0xeaffff71,0xe20b8a07,0xe08a8428,0xe8980007, +0xe1a05ba5,0xeb000515,0xe59c403c,0xe2844004, +0xe31b0401,0x120b80ff,0x10444108,0x131b0502, +0x10844188,0xe4a40004,0xe4241004,0xeaffff41, +0xe20b8a07,0xe08a8428,0xe8980007,0xe1a05ba5, +0xeb000506,0xe59c403c,0xe2844004,0xe31b0401, +0x120b80ff,0x10444108,0x131b0502,0x10844188, +0xe8840003,0xeaffff54,0xe20b8a07,0xe08a8428, +0xe8980007,0xe1a05ba5,0xeb000551,0xe20b380f, +0xe79c4723,0xe20b80ff,0xe31b0502,0x10848108, +0x00448108,0xe31b0401,0x11a04008,0xe31b0602, +0x178c8723,0xe4a40004,0xe4a41004,0xe4242008, +0xe58a7080,0xe59c903c,0xe3390000,0x14b9b000, +0x100b808b,0x13180302,0x1b000462,0xe91c0300, +0xe129f009,0xe169f008,0xe1a0d00c,0xe8dc7fff, +0xe1a00000,0xe28dd03c,0xe8fd8000,0xe20b8a07, +0xe08a8428,0xe8980007,0xe1a05ba5,0xeb000530, +0xe20b380f,0xe353080d,0x2a00000a,0xe79c4723, +0xe20b80ff,0xe31b0502,0x10848108,0x00448108, +0xe31b0401,0x11a04008,0xe31b0602,0x178c8723, +0xe8840007,0xeaffff20,0xe51c8008,0xe218800f, +0xe10f9000,0xe3888090,0xe3c9401f,0xe1848008, +0xe129f008,0xe353080d,0x01a0400d,0x11a0400e, +0xe20b80ff,0xe31b0502,0x10848108,0x00448108, +0xe31b0401,0x11a04008,0xe31b0602,0x0a000002, +0xe353080d,0x01a0d008,0x11a0e008,0xe129f009, +0xe8840007,0xeaffff08,0xe20b8a07,0xe08a8428, +0xe8980007,0xe1a05ba5,0xeb000505,0xe59c403c, +0xe2844004,0xe31b0401,0x120b80ff,0x10444108, +0x131b0502,0x10844188,0xe4a40004,0xe4a41004, +0xe4242008,0xeafffed7,0xe20b8a07,0xe08a8428, +0xe8980007,0xe1a05ba5,0xeb0004f5,0xe59c403c, +0xe2844004,0xe31b0401,0x120b80ff,0x10444108, +0x131b0502,0x10844188,0xe8840007,0xeafffeea, +0xe20b8a07,0xe08a8428,0xe8980007,0xeb000570, +0xe20b380f,0xe79c4723,0xe20b80ff,0xe31b0502, +0x10848108,0x00448108,0xe31b0401,0x11a04008, +0xe31b0602,0x178c8723,0xe3170b02,0xe4a40004, +0xe4a41004,0xe4a42004,0x14a46000,0xeafffeb5, +0xe20b8a07,0xe08a8428,0xe8980007,0xeb00055c, +0xe20b380f,0xe353080d,0x2a00000c,0xe79c4723, +0xe20b80ff,0xe31b0502,0x10848108,0x00448108, +0xe31b0401,0x11a04008,0xe31b0602,0x178c8723, +0xe3170b02,0x08840007,0x18840047,0xeafffec2, +0xe51c8008,0xe218800f,0xe10f9000,0xe3888090, +0xe3c9401f,0xe1848008,0xe129f008,0xe353080d, +0x01a0400d,0x11a0400e,0xe20b80ff,0xe31b0502, +0x10848108,0x00448108,0xe31b0401,0x11a04008, +0xe31b0602,0x0a000002,0xe353080d,0x01a0d008, +0x11a0e008,0xe129f009,0xe3170b02,0x08840007, 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+0x00000000,0x00000000,0x00000000,0x00000000, +0x00000000,0x00000000,0x00000000,0x00000000, +0x00000000,0x00000000,0xffffffff,0x00003bc8, +0x00003c08,0x0000523c,0x000052bc,0x00000002, +0x00007a68,0xffffffff,0x80000204,0x616f6c46, +0x676e6974,0x696f5020,0x4520746e,0x70656378, +0x6e6f6974,0x49203a20,0x6178656e,0x52207463, +0x6c757365,0x00000074,0x80000203,0x616f6c46, +0x676e6974,0x696f5020,0x4520746e,0x70656378, +0x6e6f6974,0x55203a20,0x7265646e,0x776f6c66, +0x00000000,0x80000202,0x616f6c46,0x676e6974, +0x696f5020,0x4520746e,0x70656378,0x6e6f6974, +0x44203a20,0x64697669,0x79422065,0x72655a20, +0x0000006f,0x80000201,0x616f6c46,0x676e6974, +0x696f5020,0x4520746e,0x70656378,0x6e6f6974, +0x4f203a20,0x66726576,0x00776f6c,0x80000200, +0x616f6c46,0x676e6974,0x696f5020,0x4520746e, +0x70656378,0x6e6f6974,0x49203a20,0x6c61766e, +0x4f206469,0x61726570,0x6e6f6974,0x00000000, +0x80000280,0x20455046,0x65746e49,0x6c616e72, +0x72724520,0x3a20726f,0x726f4320,0x61462065, +0x79746c75,0x00000000,0x80000281,0x20455046, +0x65746e49,0x6c616e72,0x72724520,0x3a20726f, +0x726f4320,0x69442065,0x6c626173,0x00006465, +0xef000071,0 + } +}; + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.C b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.C new file mode 100644 index 0000000..cdc0115 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.C @@ -0,0 +1,828 @@ +/***************************************************************************\ +* armos.c * +* ARMulator II Prototype Operating System Interface. * +* Copyright (C) 1991 Advanced RISC Machines Limited. All rights reserved. * +* Written by Dave Jaggar. * +\***************************************************************************/ + +/* + * RCS $Revision: 1.51.2.2 $ + * Checkin $Date: 1995/06/08 18:45:22 $ + * Revising $Author: plg $ + */ + +/* This file contains a model of Demon, ARM Ltd's Debug Monitor, +including all the SWI's required to support the C library. The code in +it is not really for the faint-hearted (especially the abort handling +code), but it is a complete example. Defining NOOS will disable all the +fun, and definign VAILDATE will define SWI 1 to enter SVC mode, and SWI +0x11 to halt the emulator. */ + +#include +#include +#include + +#include "armdefs.h" +#include "armos.h" +#ifndef NOFPE +#ifndef NOOS +#ifndef VALIDATE +#include "armfpe.h" +#endif +#endif +#endif +#include "dbg_hif.h" + +struct fpedesc fpedesc; + +#ifndef __STDC__ +#define remove(s) unlink(s) +#endif + +#ifdef __riscos + extern int _fisatty(FILE *); +# define isatty_(f) _fisatty(f) +# define EMFILE -1 +# define EBADF -1 + int _kernel_escape_seen(void) { return 0 ;} +#else +# if defined(_WINDOWS) || defined(_CONSOLE) +# define isatty_(f) (f == stdin || f == stdout) +# else +# ifdef __ZTC__ +# include +# define isatty_(f) isatty((f)->_file) +# else +# ifdef macintosh +# include +# define isatty_(f) (~ioctl((f)->_file,FIOINTERACTIVE,NULL)) +# else +# define isatty_(f) isatty(fileno(f)) +# endif +# endif +# endif +#endif + +extern unsigned ARMul_OSInit(ARMul_State *state) ; +extern void ARMul_OSExit(ARMul_State *state) ; +extern unsigned ARMul_OSHandleSWI(ARMul_State *state,ARMword number) ; +extern unsigned ARMul_OSException(ARMul_State *state, ARMword vector, ARMword pc) ; +extern ARMword ARMul_OSLastErrorP(ARMul_State *state) ; +extern ARMword ARMul_Debug(ARMul_State *state, ARMword pc, ARMword instr) ; +extern ARMword ARMul_ReadClock(ARMul_State *state) ; + +#define BUFFERSIZE 4096 +#ifndef FOPEN_MAX +#define FOPEN_MAX 64 +#endif +#define UNIQUETEMPS 256 + +#ifndef NOOS +static void UnwindDataAbort(ARMul_State *state, ARMword addr, ARMword iset); +static void getstring(ARMul_State *state, ARMword from, char *to) ; +#endif + +#define OLDINSTRUCTIONSIZE (CPSRINSTRUCTIONSIZE(ARMul_GetSPSR(state, ARMul_GetCPSR(state)))) + +/***************************************************************************\ +* OS private Information * +\***************************************************************************/ + +struct OSblock { + ARMword Time0 ; + ARMword ErrorP ; + ARMword ErrorNo ; + FILE *FileTable[FOPEN_MAX] ; + char FileFlags[FOPEN_MAX] ; + char *tempnames[UNIQUETEMPS] ; + } ; + +#define NOOP 0 +#define BINARY 1 +#define READOP 2 +#define WRITEOP 4 + +#ifdef macintosh +#define FIXCRLF(t,c) ((t & BINARY)?c:((c=='\n'||c=='\r')?(c ^ 7):c)) +#else +#define FIXCRLF(t,c) c +#endif + +static ARMword softvectorcode[] = +{ /* basic: swi tidyexception + event; mov lr, pc; + ldmia r11,{r11,pc}; swi generateexception + event + */ + 0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /*Reset*/ + 0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /*Undef*/ + 0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /*SWI */ + 0xef000093, 0xe1a0e00f, 0xe89b8800, 0xef000083, /*Prefetch abort*/ + 0xef000094, 0xe1a0e00f, 0xe89b8800, 0xef000084, /*Data abort*/ + 0xef000095, 0xe1a0e00f, 0xe89b8800, 0xef000085, /*Address exception*/ + 0xef000096, 0xe1a0e00f, 0xe89b8800, 0xef000086, /*IRQ*/ + 0xef000097, 0xe1a0e00f, 0xe89b8800, 0xef000087, /*FIQ*/ + 0xef000098, 0xe1a0e00f, 0xe89b8800, 0xef000088, /*Error*/ + 0xe1a0f00e /* default handler */ +}; + +/***************************************************************************\ +* Time for the Operating System to initialise itself. * +\***************************************************************************/ + +unsigned ARMul_OSInit(ARMul_State *state) +{ +#ifndef NOOS +#ifndef VALIDATE + ARMword instr, i , j ; + struct OSblock* OSptr = (struct OSblock*)state->OSptr; + + if (state->OSptr == NULL) { + state->OSptr = (unsigned char *)malloc(sizeof(struct OSblock)); + if (state->OSptr == NULL) { + perror("OS Memory"); + exit(15); + } + } + OSptr = (struct OSblock*)state->OSptr; + OSptr->ErrorP = 0; + state->Reg[13] = ADDRSUPERSTACK; /* set up a stack for the current mode */ + ARMul_SetReg(state,(unsigned)SVC32MODE,13,ADDRSUPERSTACK); /* and for supervisor mode */ + ARMul_SetReg(state,(unsigned)ABORT32MODE,13,ADDRABORTSTACK); /* and for abort 32 mode */ + ARMul_SetReg(state,(unsigned)UNDEF32MODE,13,ADDRUNDEFSTACK); /* and for undef 32 mode */ + ARMul_SetReg(state,(unsigned)IRQ32MODE,13,ADDRIRQSTACK); /* and for IRQ 32 mode */ + ARMul_SetReg(state,(unsigned)FIQ32MODE,13,ADDRFIQSTACK); /* and for FIQ 32 mode */ + instr = 0xe59ff000 | (ADDRSOFTVECTORS - 8); /* load pc from soft vector */ + for (i = ARMul_ResetV ; i <= ARMFIQV ; i += 4) + ARMul_WriteWord(state, i, instr); /* write hardware vectors */ + for (i = ARMul_ResetV ; i <= ARMFIQV + 4 ; i += 4) { + ARMul_WriteWord(state, ADDRSOFTVECTORS + i, SOFTVECTORCODE + i * 4); + ARMul_WriteWord(state, ADDRSOFHANDLERS + 2*i + 4L, SOFTVECTORCODE + sizeof(softvectorcode) - 4L); + } + for (i = 0 ; i < sizeof(softvectorcode) ; i += 4) + ARMul_WriteWord(state, SOFTVECTORCODE + i, softvectorcode[i/4]); + for (i = 0 ; i < FOPEN_MAX ; i++) + OSptr->FileTable[i] = NULL ; + for (i = 0 ; i < UNIQUETEMPS ; i++) + OSptr->tempnames[i] = NULL ; + ARMul_ConsolePrint(state, ", soft DEMON vsn 1.3") ; + +#ifndef NOFPE + if (state->fpe) /* install fpe (conditionally) */ + { ARMword addr = fpe.hdr.imagebase; + fpedesc.base = addr; + fpedesc.regs = 0; + if (addr + sizeof(fpe.code) > FPEEND) + ARMul_ConsolePrint(state, ", FPE too big to load"); + else { + for (i = 0 ; i < sizeof(fpe.code) - 4; i += 4) /* copy the code */ + ARMul_WriteWord(state, addr + i, fpe.code[i >> 2]) ; + i = (sizeof(fpe.code) >> 2); + + while ((j = fpe.code[--i]) != 0xffffffff) + { + if (state->bigendSig && j < 0x80000000) { + /* it's part of the string so swap it */ + j = ((j >> 0x18) & 0x000000ff) | + ((j >> 0x08) & 0x0000ff00) | + ((j << 0x08) & 0x00ff0000) | + ((j << 0x18) & 0xff000000) ; + ARMul_WriteWord(state, addr + (i<<2), j) ; + } + } + + fpedesc.regs = fpe.code[--i]; + fpedesc.version = (int)fpe.code[--i]; + + if (fpedesc.version > 1) + { /* reverse FPE/FPASC byte tables for versions > 1 */ + ARMword start, end; /* region to be reversed */ + while ((end = fpe.code[--i]) != 0xffffffff) + { + start = fpe.code[--i]; + + if (state->bigendSig) + for (j = start; j < end; j += 4) + { + ARMword t = ARMul_ReadWord(state, j); + t = ((t >> 0x18) & 0x000000ff) | + ((t >> 0x08) & 0x0000ff00) | + ((t << 0x08) & 0x00ff0000) | + ((t << 0x18) & 0xff000000); + ARMul_WriteWord(state, j, t); + } + } + } + ARMul_ConsolePrint(state, ", FPE") ; + ARMul_SetPC(state, fpe.hdr.imagebase + fpe.hdr.entry_br); + state->EndCondition = 0; + ARMul_DoProg(state); + if (state->EndCondition != 0) { + ARMul_ConsolePrint(state, " initialisation failed"); + fpedesc.regs = 0; + } + } + } +#endif /* NOFPE */ + +#endif /* VALIDATE */ +#endif /* NOOS */ + + return(TRUE) ; +} + +void ARMul_OSExit(ARMul_State *state) +{ + free((char *)state->OSptr) ; +} + + +/***************************************************************************\ +* Return the last Operating System Error. * +\***************************************************************************/ + +ARMword ARMul_OSLastErrorP(ARMul_State *state) +{ + return ((struct OSblock *)state->OSptr)->ErrorP; +} + +/***************************************************************************\ +* The emulator calls this routine when a SWI instruction is encuntered. The * +* parameter passed is the SWI number (lower 24 bits of the instruction). * +\***************************************************************************/ + +unsigned ARMul_OSHandleSWI(ARMul_State *state,ARMword number) +{ +#ifdef NOOS + return(FALSE) ; +#else +#ifdef VALIDATE + switch (number) { + case 0x11 : + state->Emulate = FALSE ; + return(TRUE) ; + case 0x01 : + if (ARM32BITMODE) /* Stay in entry (ARM/THUMB) state */ + ARMul_SetCPSR(state, (ARMul_GetCPSR(state) & 0xffffffe0) | 0x13) ; + else + ARMul_SetCPSR(state, (ARMul_GetCPSR(state) & 0xffffffc0) | 0x3) ; + return(TRUE) ; + default : + return(FALSE) ; + } +#else + ARMword addr, temp ; + char buffer[BUFFERSIZE], *cptr ; + FILE *fptr ; + struct OSblock* OSptr = (struct OSblock*)state->OSptr ; + + switch (number) { + case SWI_WriteC : + state->hostif->writec(state->hostif->hostosarg,(int)state->Reg[0]); + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_Write0 : + addr = state->Reg[0] ; + while ((temp = ARMul_ReadByte(state,addr++)) != 0) + state->hostif->writec(state->hostif->hostosarg,(char)temp); + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_ReadC : + state->Reg[0] = (ARMword)state->hostif->readc(state->hostif->hostosarg) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_CLI : + addr = state->Reg[0] ; + getstring(state,state->Reg[0],buffer) ; + state->Reg[0] = (ARMword)system(buffer) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_GetEnv : + state->Reg[0] = ADDRCMDLINE ; + if (state->MemSize) + state->Reg[1] = state->MemSize ; + else + state->Reg[1] = ADDRUSERSTACK ; + + addr = state->Reg[0] ; + cptr = state->CommandLine ; + if (cptr == NULL) + cptr = "\0" ; + do { + temp = (ARMword)*cptr++ ; + ARMul_WriteByte(state,addr++,temp) ; + } while (temp != 0) ; + return(TRUE) ; + + case SWI_Exit : + state->Emulate = FALSE ; + return(TRUE) ; + + case SWI_EnterOS : + if (ARM32BITMODE) /* Stay in entry (ARM/THUMB) state */ + ARMul_SetCPSR(state, (ARMul_GetCPSR(state) & 0xffffffe0) | 0x13) ; + else + ARMul_SetCPSR(state, (ARMul_GetCPSR(state) & 0xffffffc0) | 0x3) ; + return(TRUE) ; + + case SWI_GetErrno : + state->Reg[0] = OSptr->ErrorNo ; + return(TRUE) ; + + case SWI_Clock : { + /* return muber of centi-seconds... */ + /* Only use the simulated clock if memory speed & cpu speed specified */ + /* This should be in the memory model, called via. ARMul_ReadClock() */ + if (state->MemInfoPtr != NULL && state->cpu_ns != 0) { + MemDescr *m; + unsigned long ns = state->ns, + s = state->s; + for (m = state->MemInfoPtr; m != NULL; m = m->next) { + ns += m->a.ns; + if (ns >= 1000000000) s++, ns -= 1000000000; + s += m->a.s; + } + state->Reg[0] = s * 100 + ns / 10000000; + } else { + state->Reg[0] = +#ifdef CLOCKS_PER_SEC + (CLOCKS_PER_SEC >= 100) + ? (ARMword) (clock() / (CLOCKS_PER_SEC / 100)) + : (ARMword) ((clock() * 100) / CLOCKS_PER_SEC) ; +#else + /* presume unix... clock() returns microseconds */ + (ARMword) (clock() / 10000) ; +#endif + OSptr->ErrorNo = errno ; + } + return(TRUE) ; + } + + case SWI_Time : + state->Reg[0] = (ARMword)time(NULL) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_Remove : + getstring(state,state->Reg[0],buffer) ; + state->Reg[0] = remove(buffer) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_Rename : { + char buffer2[BUFFERSIZE] ; + + getstring(state,state->Reg[0],buffer) ; + getstring(state,state->Reg[1],buffer2) ; + state->Reg[0] = rename(buffer,buffer2) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + } + + case SWI_Open : { + static char* fmode[] = {"r","rb","r+","r+b", + "w","wb","w+","w+b", + "a","ab","a+","a+b", + "r","r","r","r"} /* last 4 are illegal */ ; + unsigned type ; + + type = (unsigned)(state->Reg[1] & 15L) ; + getstring(state,state->Reg[0],buffer) ; + if (strcmp(buffer,":tt")==0 && (type == 0 || type == 1)) /* opening tty "r" */ + fptr = stdin ; + else if (strcmp(buffer,":tt")==0 && (type == 4 || type == 5)) /* opening tty "w" */ + fptr = stdout ; + else + fptr = fopen(buffer,fmode[type]) ; + + state->Reg[0] = 0 ; + if (fptr != NULL) { + for (temp = 0 ; temp < FOPEN_MAX ; temp++) + if (OSptr->FileTable[temp] == NULL || + (OSptr->FileTable[temp] == fptr && (OSptr->FileFlags[temp] & 1) == (type & 1))) { + OSptr->FileTable[temp] = fptr ; + OSptr->FileFlags[temp] = type & 1 ; /* preserve the binary bit */ + state->Reg[0] = (ARMword)(temp + 1) ; + break ; + } + if (state->Reg[0] == 0) + OSptr->ErrorNo = EMFILE ; /* too many open files */ + else + OSptr->ErrorNo = errno ; + } + else + OSptr->ErrorNo = errno ; + return(TRUE) ; + } + + case SWI_Close : + temp = state->Reg[0] ; + if (temp == 0 || temp > FOPEN_MAX || OSptr->FileTable[temp - 1] == 0) { + OSptr->ErrorNo = EBADF ; + state->Reg[0] = -1L ; + return(TRUE) ; + } + temp-- ; + fptr = OSptr->FileTable[temp] ; + if (fptr == stdin || fptr == stdout) + state->Reg[0] = 0 ; + else + state->Reg[0] = fclose(fptr) ; + OSptr->FileTable[temp] = NULL ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_Write : { + unsigned size, upto, type ; + char ch ; + + temp = state->Reg[0] ; + if (temp == 0 || temp > FOPEN_MAX || OSptr->FileTable[temp - 1] == 0) { + OSptr->ErrorNo = EBADF ; + state->Reg[0] = -1L ; + return(TRUE) ; + } + temp-- ; + fptr = OSptr->FileTable[temp] ; + type = OSptr->FileFlags[temp] ; + addr = state->Reg[1] ; + size = (unsigned)state->Reg[2] ; + + if (type & READOP) + fseek(fptr,0L,SEEK_CUR) ; + OSptr->FileFlags[temp] = (type & BINARY) | WRITEOP ; ; + while (size > 0) { + if (size >= BUFFERSIZE) + upto = BUFFERSIZE ; + else + upto = size ; + for (cptr = buffer ; (cptr - buffer) < upto ; cptr++) { + ch = (char)ARMul_ReadByte(state,(ARMword)addr++) ; + *cptr = FIXCRLF(type,ch) ; + } + temp = (fptr == stderr || fptr == stdout) + ? state->hostif->write(state->hostif->hostosarg, buffer, upto) + : fwrite(buffer,1,upto,fptr); + if (temp < upto) { + state->Reg[0] = (ARMword)(size - temp) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + } + size -= upto ; + } + state->Reg[0] = 0 ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + } + + case SWI_Read : { + unsigned size, upto, type ; + char ch ; + + temp = state->Reg[0] ; + if (temp == 0 || temp > FOPEN_MAX || OSptr->FileTable[temp - 1] == 0) { + OSptr->ErrorNo = EBADF ; + state->Reg[0] = -1L ; + return(TRUE) ; + } + temp-- ; + fptr = OSptr->FileTable[temp] ; + addr = state->Reg[1] ; + size = (unsigned)state->Reg[2] ; + type = OSptr->FileFlags[temp] ; + + if (type & WRITEOP) + fseek(fptr,0L,SEEK_CUR) ; + OSptr->FileFlags[temp] = (type & BINARY) | READOP ; ; + while (size > 0) { + if (isatty_(fptr)) { + upto = (size >= BUFFERSIZE)?BUFFERSIZE:size + 1 ; + if (state->hostif->gets(state->hostif->hostosarg, buffer, upto) != 0) + temp = strlen(buffer) ; + else + temp = 0 ; + upto-- ; /* 1 char used for terminating null */ + } + else { + upto = (size>=BUFFERSIZE)?BUFFERSIZE:size ; + temp = fread(buffer,1,upto,fptr) ; + } + for (cptr = buffer ; (cptr - buffer) < temp ; cptr++) { + ch = *cptr ; + ARMul_WriteByte(state,(ARMword)addr++,FIXCRLF(type,ch)) ; + } + if (temp < upto) { + state->Reg[0] = (ARMword)(size - temp) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + } + size -= upto ; + } + state->Reg[0] = 0 ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + } + + case SWI_Seek : + if (state->Reg[0] == 0 || state->Reg[0] > FOPEN_MAX + || OSptr->FileTable[state->Reg[0] - 1] == 0) { + OSptr->ErrorNo = EBADF ; + state->Reg[0] = -1L ; + return(TRUE) ; + } + fptr = OSptr->FileTable[state->Reg[0] - 1] ; + state->Reg[0] = fseek(fptr,(long)state->Reg[1],SEEK_SET) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_Flen : + if (state->Reg[0] == 0 || state->Reg[0] > FOPEN_MAX + || OSptr->FileTable[state->Reg[0] - 1] == 0) { + OSptr->ErrorNo = EBADF ; + state->Reg[0] = -1L ; + return(TRUE) ; + } + fptr = OSptr->FileTable[state->Reg[0] - 1] ; + addr = (ARMword)ftell(fptr) ; + if (fseek(fptr,0L,SEEK_END) < 0) + state->Reg[0] = -1 ; + else { + state->Reg[0] = (ARMword)ftell(fptr) ; + (void)fseek(fptr,addr,SEEK_SET) ; + } + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_IsTTY : + if (state->Reg[0] == 0 || state->Reg[0] > FOPEN_MAX + || OSptr->FileTable[state->Reg[0] - 1] == 0) { + OSptr->ErrorNo = EBADF ; + state->Reg[0] = -1L ; + return(TRUE) ; + } + fptr = OSptr->FileTable[state->Reg[0] - 1] ; + state->Reg[0] = isatty_(fptr) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_TmpNam :{ + ARMword size ; + + addr = state->Reg[0] ; + temp = state->Reg[1] & 0xff ; + size = state->Reg[2] ; + if (OSptr->tempnames[temp] == NULL) { + if ((OSptr->tempnames[temp] = (char *)malloc(L_tmpnam)) == NULL) { + state->Reg[0] = 0 ; + return(TRUE) ; + } + (void)tmpnam(OSptr->tempnames[temp]) ; + } + cptr = OSptr->tempnames[temp] ; + if (strlen(cptr) > state->Reg[2]) + state->Reg[0] = 0 ; + else + do { + ARMul_WriteByte(state,addr++,*cptr) ; + } while (*cptr++ != 0) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + } + + case SWI_InstallHandler: + { ARMword handlerp = ADDRSOFHANDLERS + state->Reg[0] * 8; + ARMword oldr1 = ARMul_ReadWord(state, handlerp), + oldr2 = ARMul_ReadWord(state, handlerp + 4); + ARMul_WriteWord(state, handlerp, state->Reg[1]); + ARMul_WriteWord(state, handlerp + 4, state->Reg[2]); + state->Reg[1] = oldr1; + state->Reg[2] = oldr2; + return(TRUE); + } + + case SWI_GenerateError: + ARMul_Abort(state, ARMSWIV) ; + if (state->Emulate) + ARMul_SetR15(state, ARMul_ReadWord(state, ADDRSOFTVECTORS + ARMErrorV)); + return(TRUE); + +/* SWI's 0x9x unwind the state of the CPU after an abort of type x */ + + case 0x90: /* Branch through zero */ + { ARMword oldpsr = ARMul_GetCPSR(state) ; + ARMul_SetCPSR(state, (oldpsr & 0xffffffc0) | 0x13) ; + ARMul_SetSPSR(state, SVC32MODE, oldpsr) ; + state->Reg[14] = 0; + goto TidyCommon; + } + + case 0x98: /* Error */ + { ARMword errorp = state->Reg[0], + regp = state->Reg[1]; + unsigned i; + ARMword errorpsr = ARMul_ReadWord(state, regp + 16*4); + for (i = 0; i < 15; i++) + ARMul_SetReg(state,(unsigned)errorpsr,i,ARMul_ReadWord(state, regp + i*4L)) ; + state->Reg[14] = ARMul_ReadWord(state, regp + 15*4L); + state->Reg[10] = errorp; + ARMul_SetSPSR(state,state->Mode,errorpsr) ; + OSptr->ErrorP = errorp; + goto TidyCommon; + } + + case 0x94: /* Data abort */ + { ARMword addr = state->Reg[14] - OLDINSTRUCTIONSIZE * 2; + ARMword cpsr = ARMul_GetCPSR(state) ; + if (ARM26BITMODE) + addr = addr & 0x3fffffc ; + ARMul_SetCPSR(state,ARMul_GetSPSR(state,cpsr)) ; + UnwindDataAbort(state, addr, CPSRINSTRUCTIONSET(ARMul_GetSPSR(state,cpsr))); +#ifndef NOFPE + if (addr >= fpedesc.base && addr < FPEEND) { /* in the FPE */ + ARMword regdump; + if (fpedesc.version == 0) { + /* fpe340. user's registers are the only things on the fpe's stack */ + ARMword sp = state->Reg[13] ; + state->Reg[13] += 64 ; /* fix the aborting mode sp */ + regdump = sp; + } else { + /* new fpe. r12 addresses a frame on the fpe's stack, immediately + above which are dumped the user's registers. The saved pc is for + the instruction after the one causing the fault. + */ + ARMword fp = state->Reg[12]; + state->Reg[13] = fp + 64; /* reset the fpe's stack */ + regdump = fp; + } + state->Reg[14] = ARMul_ReadWord(state,regdump + 15*4) ; /* and its lr */ + { ARMword spsr = ARMul_GetSPSR(state,state->Mode); + int i; + ARMul_SetCPSR(state,spsr) ; + for (i = 0 ; i < 15 ; i++) + ARMul_SetReg(state,(unsigned)spsr,i,ARMul_ReadWord(state,regdump + (ARMword)i*4)); + ARMul_SetCPSR(state,cpsr) ; + state->Reg[14] = ARMul_ReadWord(state,regdump + 15*4) + INSTRUCTION32SIZE ; /* botch it */ + ARMul_SetSPSR(state,state->Mode,spsr) ; + } + } else +#endif + ARMul_SetCPSR(state,cpsr) ; + + /* and fall through to correct r14 */ + } + case 0x95: /* Address Exception */ + state->Reg[14] -= OLDINSTRUCTIONSIZE; + case 0x91: /* Undefined instruction */ + case 0x92: /* SWI */ + case 0x93: /* Prefetch abort */ + case 0x96: /* IRQ */ + case 0x97: /* FIQ */ + state->Reg[14] -= OLDINSTRUCTIONSIZE; + TidyCommon: + if (state->VectorCatch & (1 << (number - 0x90))) { + ARMul_SetR15(state, state->Reg[14] + OLDINSTRUCTIONSIZE * 2) ; /* the pipelining the the RDI will undo */ + ARMul_SetCPSR(state,ARMul_GetSPSR(state,ARMul_GetCPSR(state))) ; + if (number == 0x90) + state->EndCondition = 10 ; /* Branch through Zero Error */ + else + state->EndCondition = (unsigned)number - 0x8f; + state->Emulate = FALSE ; + } + else { + ARMword sp = state->Reg[13]; + ARMul_WriteWord(state, sp - 4, state->Reg[14]); + ARMul_WriteWord(state, sp - 8, state->Reg[12]); + ARMul_WriteWord(state, sp - 12, state->Reg[11]); + ARMul_WriteWord(state, sp - 16, state->Reg[10]); + state->Reg[13] = sp - 16; + state->Reg[11] = ADDRSOFHANDLERS + 8 * (number - 0x90); + } + return(TRUE); + +/* SWI's 0x8x pass an abort of type x to the debugger if a handler returns */ + + case 0x80: case 0x81: case 0x82: case 0x83: + case 0x84: case 0x85: case 0x86: case 0x87: case 0x88: + { ARMword sp = state->Reg[13]; + state->Reg[10] = ARMul_ReadWord(state, sp); + state->Reg[11] = ARMul_ReadWord(state, sp + 4); + state->Reg[12] = ARMul_ReadWord(state, sp + 8); + state->Reg[14] = ARMul_ReadWord(state, sp + 12); + state->Reg[13] = sp + 16; + ARMul_SetR15(state, state->Reg[14] + OLDINSTRUCTIONSIZE * 2) ; /* the pipelining the the RDI will undo */ + ARMul_SetCPSR(state,ARMul_GetSPSR(state,ARMul_GetCPSR(state))) ; + if (number == 0x80) + state->EndCondition = 10 ; /* Branch through Zero Error */ + else + state->EndCondition = (unsigned)number - 0x7f; + state->Emulate = FALSE ; + return(TRUE); + } + + default : + return(FALSE) ; + } +#endif +#endif + } + +/***************************************************************************\ +* The emulator calls this routine when an Exception occurs. The second * +* parameter is the address of the relevant exception vector. Returning * +* FALSE from this routine causes the trap to be taken, TRUE causes it to * +* be ignored (so set state->Emulate to FALSE!). * +\***************************************************************************/ + +unsigned ARMul_OSException(ARMul_State *state, ARMword vector, ARMword pc) +{ /* don't use this here */ + return(FALSE) ; +} + +#ifndef NOOS + +/***************************************************************************\ +* Unwind a data abort * +\***************************************************************************/ + +static void UnwindDataAbort(ARMul_State *state, ARMword addr, ARMword iset) +{ +#ifdef CODE16 + if (iset == INSTRUCTION16) { + ARMword instr = ARMul_ReadWord(state, addr); + ARMword offset; + unsigned long regs; + if (state->bigendSig ^ ((addr & 2) == 2)) /* get instruction into low 16 bits */ + instr = instr >> 16; + switch (BITS(11,15)) { + case 0x16: + case 0x17: + if (BITS(9,10) == 2) { /* push/pop */ + regs = BITS(0, 8); + offset = 0; + for (; regs != 0; offset++) + regs ^= (regs & -regs); + if (BIT(11)) + state->Reg[13] -= offset * 4; /* pop */ + else + state->Reg[13] += offset * 4; /* push */ + } + break; + case 0x18: + case 0x19: + regs = BITS(0,7); + offset = 0; + for (; regs != 0; offset++) + regs ^= (regs & -regs); + if (BITS(11,15) == 0x19) { /* ldmia rb! */ + state->Reg[BITS(8,10)] -= offset * 4; + } else { /* stmia rb! */ + state->Reg[BITS(8,10)] += offset * 4; + } + break; + default: + break; + } + } else { +#endif + ARMword instr = ARMul_ReadWord(state, addr); + ARMword rn = BITS(16, 19); + ARMword itype = BITS(24, 27); + ARMword offset; + if (rn == 15) return; + if (itype == 8 || itype == 9) { + /* LDM or STM */ + unsigned long regs = BITS(0, 15); + offset = 0; + if (!BIT(21)) return; /* no wb */ + for (; regs != 0; offset++) + regs ^= (regs & -regs); + if (offset == 0) offset = 16; + } else if (itype == 12 || /* post-indexed CPDT */ + (itype == 13 && BIT(21))) { /* pre_indexed CPDT with WB */ + offset = BITS(0, 7); + } else + return; + + if (BIT(23)) + state->Reg[rn] -= offset * 4; + else + state->Reg[rn] += offset * 4; +#ifdef CODE16 + } +#endif +} + +/***************************************************************************\ +* Copy a string from the debuggee's memory to the host's * +\***************************************************************************/ + +static void getstring(ARMul_State *state, ARMword from, char *to) +{do { + *to = (char)ARMul_ReadByte(state,from++) ; + } while (*to++ != '\0') ; + } + +#endif /* NOOS */ + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.H new file mode 100644 index 0000000..d9508f5 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.H @@ -0,0 +1,64 @@ +/***************************************************************************\ +* armos.h * +* Version 1.20 * +* ARMulator II Operating System Definitions. * +* Copyright (C) 1991 Advanced RISC Machines Limited. All rights reserved. * +* Written by Dave Jaggar. * +* Project started on 1st July 1991. * +* Last change was Friday 10th July 1992. * +\***************************************************************************/ + + +/***************************************************************************\ +* Define the initial layout of memory * +\***************************************************************************/ + +#define ADDRSUPERSTACK 0xA00L /* supervisor stack space */ +#define ADDRABORTSTACK 0x800L /* abort stack space */ +#define ADDRUNDEFSTACK 0x700L /* undef stack space */ +#define ADDRIRQSTACK 0x500L /* IRQ stack space */ +#define ADDRFIQSTACK 0x400L /* FIQ stack space */ +#define ADDRUSERSTACK 0x80000L /* default user stack start */ +#define ADDRSOFTVECTORS 0xA40L /* soft vectors are here */ +#define ADDRCMDLINE 0xf00L /* command line is here after a SWI GetEnv */ +#define ADDRSOFHANDLERS 0xad0L /* address and workspace for installed handlers */ +#define SOFTVECTORCODE 0xb80L /* default handlers */ + +/***************************************************************************\ +* SWI numbers * +\***************************************************************************/ + +#define SWI_WriteC 0x0 +#define SWI_Write0 0x2 +#define SWI_ReadC 0x4 +#define SWI_CLI 0x5 +#define SWI_GetEnv 0x10 +#define SWI_Exit 0x11 +#define SWI_EnterOS 0x16 + +#define SWI_GetErrno 0x60 +#define SWI_Clock 0x61 +#define SWI_Time 0x63 +#define SWI_Remove 0x64 +#define SWI_Rename 0x65 +#define SWI_Open 0x66 + +#define SWI_Close 0x68 +#define SWI_Write 0x69 +#define SWI_Read 0x6a +#define SWI_Seek 0x6b +#define SWI_Flen 0x6c + +#define SWI_IsTTY 0x6e +#define SWI_TmpNam 0x6f +#define SWI_InstallHandler 0x70 +#define SWI_GenerateError 0x71 + +#define FPEEND 0x8000L + +extern struct fpedesc { + ARMword base; + ARMword regs; + int version; +} fpedesc; + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMPROTO.C b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMPROTO.C new file mode 100644 index 0000000..5d7ec12 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMPROTO.C @@ -0,0 +1,512 @@ +/***************************************************************************\ +* armproto.c * +* Version 1.20 * +* ARMulator II Fast Prototype Memory Interface. * +* Copyright (C) 1991 Advanced RISC Machines Limited. All rights reserved. * +* Written by Dave Jaggar. * +* Project started on 1st July 1991. * +\***************************************************************************/ + +/* + * RCS $Revision: 1.12 $ + * Checkin $Date: 1995/01/18 12:27:02 $ + * Revising $Author: hmeekings $ + */ + +/* This file contains the ARMulator interface to the memory model +designed for fast prototyping. This model is also the closest to the +real ARM memory interface. Two routines must be written to build a +memory interface, ARMul_MemoryInit and ARMul_MemoryAccess. An example +memory interface is implemented, with 64K pages, allocated on demand +from a 64K entry page table. The routines PutWord and GetWord implement +this, lifted from armvirt.c, the virtual memory model. Pages are never +freed as they might be needed again. A single area of memory may be +defined to generate aborts. */ + +#include "armdefs.h" + +#ifdef VALIDATE /* for running the validate suite */ +#define TUBE 48 * 1024 * 1024 /* write a char on the screen */ +#define ABORTS +#endif + +#ifdef ABORTS /* the memory system will abort */ +/* For the old test suite Abort between 32 Kbytes and 32 Mbytes + For the new test suite Abort between 8 Mbytes and 26 Mbytes */ +/* #define LOWABORT 32 * 1024 + #define HIGHABORT 32 * 1024 * 1024 */ +#define LOWABORT 8 * 1024 * 1024 +#define HIGHABORT 26 * 1024 * 1024 +#endif + +/* #define TRACEBUS */ + +#define NUMPAGES 64 * 1024 +#define PAGESIZE 64 * 1024 +#define PAGEBITS 16 +#define OFFSETBITS 0xffff + +static ARMword GetWord(ARMul_State *state,ARMword address) ; +static void PutWord(ARMul_State *state,ARMword address, ARMword word) ; + +/***************************************************************************\ +* Initialise the memory interface * +\***************************************************************************/ + +unsigned ARMul_MemoryInit(ARMul_State *state, unsigned long initmemsize) +{ARMword **pagetable ; + unsigned page ; + + state->MemSize = initmemsize ; + pagetable = (ARMword **)malloc(sizeof(ARMword)*NUMPAGES) ; + if (pagetable == NULL) + return(FALSE) ; + for (page = 0 ; page < NUMPAGES ; page++) + *(pagetable + page) = NULL ; + state->MemDataPtr = (unsigned char *)pagetable ; +#ifdef BIGEND + state->bigendSig = HIGH ; +#endif +#ifdef LITTLEEND + state->bigendSig = LOW ; +#endif + ARMul_ConsolePrint(state, ", 4 Gb memory") ; + return(TRUE) ; +} + +/***************************************************************************\ +* Remove the memory interface * +\***************************************************************************/ + +void ARMul_MemoryExit(ARMul_State *state) +{ARMword page ; + ARMword **pagetable ; + ARMword *pageptr ; + + pagetable = (ARMword **)state->MemDataPtr ; + for (page = 0 ; page < NUMPAGES ; page++) { + pageptr = *(pagetable + page) ; + if (pageptr != NULL) + free((char *)pageptr) ; + } + free((char *)pagetable) ; + return ; + } + +/***************************************************************************\ +* Generic memory interface. Just alter this for a prototype memory system. * +\***************************************************************************/ + +ARMword ARMul_MemAccess(ARMul_State *state, + ARMword address, + ARMword dataOut, + ARMword mas1, + ARMword mas0, + ARMword rw, + ARMword seq, + ARMword mreq, + ARMword opc, + ARMword lock, + ARMword trans, + ARMword account) +{ARMword dataIn = 0 ; + +#ifdef TRACEBUS + ARMul_DebugPrint(state, "A=%08x, M=%01x, S=%01x, O=%01x\n", + address,mreq,seq,opc) ; +#endif + + ARMul_CLEARABORT ; + if (mreq == LOW) { /* memory request */ + if (account == TRUE) { /* a "real" memory access */ + if (seq == LOW) /* non-sequential (N) cycle */ + state->NumNcycles++ ; + else + state->NumScycles++ ; + } +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + if (opc == LOW) { /* opcode fetch */ + ARMul_PREFETCHABORT(address) ; + } + else { /* data access */ + ARMul_DATAABORT(address) ; + } +#ifdef TRACEBUS + ARMul_DebugPrint(state, "ABORT\n") ; +#endif + return(ARMul_ABORTWORD) ; + } /* abort */ +#endif + if (rw == LOW) { /* read */ + /* it's always a word, bytes and halfwords are extracted by ARM */ + dataIn = GetWord(state,address) ; + } /* read */ + else { /* write */ + if (mas0 == LOW) { /* byte or word */ + if (mas1 == LOW) { /* byte */ + ARMword word, offset ; + +#ifdef VALIDATE + if (address == TUBE) { + if (dataOut == 4) + state->Emulate = FALSE ; + else + (void)putc((char)dataOut,stderr) ; /* Write Char */ + return(0) ; + } +#endif + word = GetWord(state,address) ; + offset = (((ARMword)state->bigendSig * 3) ^ (address & 3)) << 3 ; /* bit offset into the word */ + PutWord(state,address,(word & ~(0xffL << offset)) | ((dataOut & 0xffL) << offset)) ; + } + else { /* write word */ + PutWord(state,address,dataOut) ; + } + } /* byte or word */ + else { /* halfword or reserved */ + if (mas1 == LOW) { /* halfword */ + ARMword word, offset ; + word = GetWord(state,address) ; + offset = (((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3 ; /* bit offset into the word */ + PutWord(state,address,(word & ~(0xffffL << offset)) | ((dataOut & 0xffffL) << offset)) ; + } else { /* reserved */ + ARMul_ConsolePrint(state, "Reserved memory access\n") ; + } + } /* halfword or reserved */ + } /* write */ + } /* memory request */ + else { /* not a memory request */ + if (seq == LOW) /* internal (I) cycle */ + state->NumIcycles++ ; + else /* co-processor (C) cycle */ + state->NumCcycles++ ; + } + return(dataIn) ; + } + +/***************************************************************************\ +* Get a Word from Virtual Memory, maybe allocating the page * +\***************************************************************************/ + +static ARMword GetWord(ARMul_State *state, ARMword address) +{ARMword page, offset ; + ARMword **pagetable ; + ARMword *pageptr ; + + page = address >> PAGEBITS ; + offset = (address & OFFSETBITS) >> 2 ; + pagetable = (ARMword **)state->MemDataPtr ; + pageptr = *(pagetable + page) ; + + if (pageptr == NULL) { + pageptr = (ARMword *)malloc(PAGESIZE) ; + if (pageptr == NULL) { + perror("ARMulator can't allocate VM page") ; + exit(12) ; + } + *(pagetable + page) = pageptr ; + } + + return(*(pageptr + offset)) ; + } + +/***************************************************************************\ +* Put a Word into Virtual Memory, maybe allocating the page * +\***************************************************************************/ + +static void PutWord(ARMul_State *state, ARMword address, ARMword data) +{ARMword page, offset ; + ARMword **pagetable ; + ARMword *pageptr ; + + page = address >> PAGEBITS ; + offset = (address & OFFSETBITS) >> 2 ; + pagetable = (ARMword **)state->MemDataPtr ; + pageptr = *(pagetable + page) ; + + if (pageptr == NULL) { + pageptr = (ARMword *)malloc(PAGESIZE) ; + if (pageptr == NULL) { + perror("ARMulator can't allocate VM page") ; + exit(13) ; + } + *(pagetable + page) = pageptr ; + } + + *(pageptr + offset) = data ; + } + +/*-------------------------------------------------------------------------*\ +* * +| NOTHING BELOW HERE SHOULD NEED CHANGING | +* * +\*-------------------------------------------------------------------------*/ + + +/***************************************************************************\ +* Load Instruction, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstrS(ARMul_State *state, ARMword address) +{ARMword temp ; + +#ifdef HOURGLASS_RATE + if( ( state->NumScycles & HOURGLASS_RATE ) == 0 ) { + armsd_hourglass(); + } +#endif + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + temp = ARMul_MemAccess(state,address,0L, 1L,0L,0L, 1L,0L, 0L, 0L,1L, 1L) ; + return(temp) ; +} + +/***************************************************************************\ +* Load Instruction, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstrN(ARMul_State *state, ARMword address) +{ARMword temp ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + temp = ARMul_MemAccess(state,address,0L, 1L,0L,0L, 0L,0L, 0L, 0L,1L, 1L) ; + return(temp) ; + } + +/***************************************************************************\ +* Load 16 bit Instruction, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstr16S(ARMul_State *state, ARMword address) +{ARMword temp, offset ; + +#ifdef HOURGLASS_RATE + if( ( state->NumScycles & HOURGLASS_RATE ) == 0 ) { + armsd_hourglass(); + } +#endif + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + temp = ARMul_MemAccess(state,address,0L, 0L,1L,0L, 1L,0L, 0L, 0L,1L, 1L) ; + offset = (((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3 ; /* bit offset into the word */ + return(temp >> offset & 0xffffL) ; +} + +/***************************************************************************\ +* Load 16 bit Instruction, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstr16N(ARMul_State *state, ARMword address) +{ARMword temp, offset ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + temp = ARMul_MemAccess(state,address,0L, 0L,1L,0L, 0L,0L, 0L, 0L,1L, 1L) ; + offset = (((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3 ; /* bit offset into the word */ + return(temp >> offset & 0xffffL) ; + } + +/***************************************************************************\ +* Load Word, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadWordS(ARMul_State *state, ARMword address) +{ARMword temp ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + temp = ARMul_MemAccess(state,address,0L, 1L,0L,0L, 1L,0L, 1L, 0L,1L, 1L) ; + return(temp) ; + } + +/***************************************************************************\ +* Load Word, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadWordN(ARMul_State *state, ARMword address) +{ARMword temp ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + temp = ARMul_MemAccess(state,address,0L, 1L,0L,0L, 0L,0L, 1L, 0L,1L, 1L) ; + return(temp) ; + } + +/***************************************************************************\ +* Load Halfword, (Non Sequential Cycle) * +\***************************************************************************/ + +ARMword ARMul_LoadHalfWord(ARMul_State *state, ARMword address) +{ARMword word, offset ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + word = ARMul_MemAccess(state,address,0L, 0L,1L,0L, 0L,0L, 1L, 0L,1L, 1L) ; + offset = (((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3 ; /* bit offset into the word */ + return(word >> offset & 0xffffL) ; + } + +/***************************************************************************\ +* Load Byte, (Non Sequential Cycle) * +\***************************************************************************/ + +ARMword ARMul_LoadByte(ARMul_State *state, ARMword address) +{ARMword word, offset ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + word = ARMul_MemAccess(state,address,0L, 0L,0L,0L, 0L,0L, 1L, 0L,1L, 1L) ; + offset = (((ARMword)state->bigendSig * 3) ^ (address & 3)) << 3 ; /* bit offset into the word */ + return(word >> offset & 0xffL) ; + } + +/***************************************************************************\ +* Store Word, Sequential Cycle * +\***************************************************************************/ + +void ARMul_StoreWordS(ARMul_State *state, ARMword address, ARMword data) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + (void)ARMul_MemAccess(state,address,data, 1L,0L,1L, 1L,0L, 1L, 0L,1L, 1L) ; +} +/***************************************************************************\ +* Store Word, Sequential Cycle * +\***************************************************************************/ + +void ARMul_StoreWordN(ARMul_State *state, ARMword address, ARMword data) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + (void)ARMul_MemAccess(state,address,data, 1L,0L,1L, 0L,0L, 1L, 0L,1L, 1L) ; +} + +/***************************************************************************\ +* Store Halfword, (Non Sequential Cycle) * +\***************************************************************************/ + +void ARMul_StoreHalfWord(ARMul_State *state, ARMword address, ARMword data) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + (void)ARMul_MemAccess(state,address,data, 0L,1L,1L, 0L,0L, 1L, 0L,1L, 1L) ; + } + +/***************************************************************************\ +* Store Byte, (Non Sequential Cycle) * +\***************************************************************************/ + +void ARMul_StoreByte(ARMul_State *state, ARMword address, ARMword data) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + (void)ARMul_MemAccess(state,address,data, 0L,0L,1L, 0L,0L, 1L, 0L,1L, 1L) ; + } + +/***************************************************************************\ +* Swap Word, (Two Non Sequential Cycles) * +\***************************************************************************/ + +ARMword ARMul_SwapWord(ARMul_State *state, ARMword address, ARMword data) +{ARMword temp ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + temp = ARMul_MemAccess(state,address,0L, 1L,0L,0L, 0L,0L, 1L, 1L,1L, 1L) ; + (void)ARMul_MemAccess(state,address,data, 1L,0L,1L, 0L,0L, 1L, 0L,1L, 1L) ; + return(temp) ; + } + +/***************************************************************************\ +* Swap Byte, (Two Non Sequential Cycles) * +\***************************************************************************/ + +ARMword ARMul_SwapByte(ARMul_State *state, ARMword address, ARMword data) +{ARMword word, offset ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + word = ARMul_MemAccess(state,address,0L, 0L,0L,0L, 0L,0L, 1L, 1L,1L, 1L) ; + (void)ARMul_MemAccess(state,address,data, 0L,0L,1L, 0L,0L, 1L, 0L,1L, 1L) ; + offset = (((ARMword)state->bigendSig * 3) ^ (address & 3)) << 3 ; /* bit offset into the word */ + return(word >> offset & 0xffL) ; + } + +/***************************************************************************\ +* Count I Cycles * +\***************************************************************************/ + +void ARMul_Icycles(ARMul_State *state, unsigned number, ARMword address) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + while (number--) + (void)ARMul_MemAccess(state,address,0L, 0L,0L,0L, 0L,1L, 1L, 0L,1L, 1L) ; + } +/***************************************************************************\ +* Count C Cycles * +\***************************************************************************/ + +void ARMul_Ccycles(ARMul_State *state, unsigned number, ARMword address) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + while (number--) + (void)ARMul_MemAccess(state,address,0L, 0L,0L,0L, 1L,1L, 1L, 0L,1L, 1L) ; + } + +/***************************************************************************\ +* Read Word (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadWord(ARMul_State *state, ARMword address) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + return(ARMul_MemAccess(state,address,0L, 1L,0L,0L, 0L,0L, 1L, 0L,1L, 0L)) ; + } + +/***************************************************************************\ +* Read Halfword (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadHalfWord(ARMul_State *state, ARMword address) +{ARMword word, offset ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + word = ARMul_MemAccess(state,address,0L, 0L,1L,0L, 0L,0L, 1L, 0L,1L, 0L) ; + offset = (((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3 ; /* bit offset into the word */ + return(word >> offset & 0xffffL) ; + } + +/***************************************************************************\ +* Read Byte (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadByte(ARMul_State *state, ARMword address) +{ARMword word, offset ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + word = ARMul_MemAccess(state,address,0L, 0L,0L,0L, 0L,0L, 1L, 0L,1L, 0L) ; + offset = (((ARMword)state->bigendSig * 3) ^ (address & 3)) << 3 ; /* bit offset into the word */ + return(word >> offset & 0xffL) ; + } + +/***************************************************************************\ +* Write Word (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteWord(ARMul_State *state, ARMword address, ARMword data) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + (void)ARMul_MemAccess(state,address,data, 1L,0L,1L, 0L,0L, 1L, 0L,1L, 0L) ; +} + +/***************************************************************************\ +* Write HalfWord (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteHalfWord(ARMul_State *state, ARMword address, ARMword data) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + (void)ARMul_MemAccess(state,address,data, 0L,1L,1L, 0L,0L, 1L, 0L,1L, 0L) ; + } + +/***************************************************************************\ +* Write Byte (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteByte(ARMul_State *state, ARMword address, ARMword data) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + (void)ARMul_MemAccess(state,address,data, 0L,0L,1L, 0L,0L, 1L, 0L,1L, 0L) ; + } + + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULATE.DEF b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULATE.DEF new file mode 100644 index 0000000..5ad1432 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULATE.DEF @@ -0,0 +1,28 @@ +; RCS $Revision: 1.2.2.1 $ +; Checkin $Date: 1996/02/07 15:50:34 $ +; Revising $Author: jporter $ +; + +LIBRARY ARMULATE + +CODE LOADONCALL DISCARDABLE +DATA LOADONCALL SINGLE + +EXPORTS + ARMul_RDI_open @1 + ARMul_RDI_close @2 + ARMul_RDI_read @3 + ARMul_RDI_write @4 + ARMul_RDI_CPUread @5 + ARMul_RDI_CPUwrite @6 + ARMul_RDI_CPread @7 + ARMul_RDI_CPwrite @8 + ARMul_RDI_setbreak @9 + ARMul_RDI_clearbreak @10 + ARMul_RDI_setwatch @11 + ARMul_RDI_clearwatch @12 + ARMul_RDI_execute @13 + ARMul_RDI_step @14 + ARMul_RDI_info @15 + ARMul_RDI_cpunames @16 + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.C b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.C new file mode 100644 index 0000000..64305af --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.C @@ -0,0 +1,122 @@ +/***************************************************************************\ +* armuldll.c * +* Copyright (C) 1995 Advanced RISC Machines Limited. All rights reserved. * +\***************************************************************************/ + +/* + * RCS $Revision: 1.1.2.1 $ + * Checkin $Date: 1996/02/07 15:50:38 $ + * Revising $Author: jporter $ + */ + +#include +#include +#include "armuldll.h" + +UINT AbortRead; + +BOOL WINAPI DllMain (HANDLE hDLL, DWORD dwReason, LPVOID lpReserved) +{ + switch (dwReason) + { + case DLL_PROCESS_ATTACH: + { + AbortRead = RegisterWindowMessage("ABORT_READ"); +#ifdef _DEBUG + char buf[BUFSIZE+1]; + // + // DLL is attaching to the address space of the current process. + // + + ghMod = hDLL; + GetModuleFileName (NULL, (LPTSTR) buf, BUFSIZE); + MessageBox ( GetFocus(), + (LPCTSTR) buf, + (LPCTSTR) "ARMulator DLL: Process attaching", + MB_OK | MB_SYSTEMMODAL); +#endif + break; + } + + case DLL_THREAD_ATTACH: + { +#ifdef _DEBUG + + // + // A new thread is being created in the current process. + // + + MessageBox ( GetFocus(), + (LPCTSTR) "ARMulator DLL: Thread attaching", + (LPCTSTR) "", + MB_OK | MB_SYSTEMMODAL); +#endif + break; + } + case DLL_THREAD_DETACH: + { +#ifdef _DEBUG + + // + // A thread is exiting cleanly. + // + + MessageBox ( GetFocus(), + (LPCTSTR) "ARMulator DLL: Thread detaching", + (LPCTSTR) "", + MB_OK | MB_SYSTEMMODAL); +#endif + break; + } + case DLL_PROCESS_DETACH: + { +#ifdef _DEBUG + + // + // The calling process is detaching the DLL from its address space. + // + MessageBox ( GetFocus(), + (LPCTSTR) "ARMulator DLL: Process detaching", + (LPCTSTR) "", + MB_OK | MB_SYSTEMMODAL ); +#endif + break; + } + } + +return TRUE; +} + + +/******************************************************************************\ +* +* FUNCTION: Utils +* +* RETURNS: ARMulator DLL Utility functions (not exported) +* +\******************************************************************************/ + +void YieldControl(int nLoops) +{ + MSG Message; + int loop = 0; + + if (PeekMessage(&Message, NULL, AbortRead,AbortRead, PM_NOREMOVE)) return; + if (PeekMessage(&Message, NULL, WM_CLOSE,WM_CLOSE, PM_NOREMOVE)) return; + while (loop < nLoops) + { + while (PeekMessage(&Message, NULL, 0,0, PM_REMOVE)) + { + TranslateMessage(&Message); + DispatchMessage(&Message); + } + loop++; + } +} + +void armsd_hourglass(void) +{ + YieldControl(1); // This could be Selected By Options +} + + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.H new file mode 100644 index 0000000..3c6379a --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.H @@ -0,0 +1,62 @@ +/***************************************************************************\ +* armuldll.h * +* Copyright (C) 1995 Advanced RISC Machines Limited. All rights reserved. * +\***************************************************************************/ + +/* + * RCS $Revision: 1.1.2.1 $ + * Checkin $Date: 1996/02/07 15:50:39 $ + * Revising $Author: jporter $ + */ + +#define BUFSIZE 80 +#include +#include "armdbg.h" +#include "dbg_rdi.h" + +#ifdef __WATCOMC__ + #define DLL_EXPORT __export +#elif _MSC_VER + #define DLL_EXPORT _declspec(dllexport) +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif +/******************************************************************************\ +* GLOBAL VARIABLES +\******************************************************************************/ +HANDLE ghMod; + +/******************************************************************************\ +* FUNCTION PROTOTYPES +\******************************************************************************/ + +//RDIProcVec *ARMul_DLL_GetRDI(); +RDI_NameList const *ARMul_RDI_cpunames(void); +INT ARMul_RDI_open(unsigned type, const Dbg_ConfigBlock *config, + const Dbg_HostosInterface *hostif, + struct Dbg_MCState *dbg_state); + +INT ARMul_RDI_close(void); +INT ARMul_RDI_read(ARMword source, void *dest, unsigned *nbytes); +INT ARMul_RDI_write(const void *source, ARMword dest, unsigned *nbytes); +INT ARMul_RDI_CPUread(unsigned mode, unsigned long mask, ARMword *buffer); +INT ARMul_RDI_CPUwrite(unsigned mode, unsigned long mask, ARMword const *buffer); +INT ARMul_RDI_CPread(unsigned CPnum, unsigned long mask, ARMword *buffer); +INT ARMul_RDI_CPwrite(unsigned CPnum, unsigned long mask, ARMword const *buffer); +INT ARMul_RDI_setbreak(ARMword address, unsigned type, ARMword bound, + PointHandle *handle); +INT ARMul_RDI_clearbreak(PointHandle handle); +INT ARMul_RDI_setwatch(ARMword address, unsigned type, unsigned datatype, + ARMword bound, PointHandle *handle); +INT ARMul_RDI_clearwatch(PointHandle handle); +INT ARMul_RDI_execute(PointHandle *handle); +INT ARMul_RDI_step(unsigned ninstr, PointHandle *handle); +INT ARMul_RDI_info(unsigned type, ARMword *arg1, ARMword *arg2); + +#ifdef __cplusplus +} +#endif + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMVIRT.C b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMVIRT.C new file mode 100644 index 0000000..70ec5d0 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMVIRT.C @@ -0,0 +1,871 @@ +/*************************************************************************** + * armvirt.c + * ARMulator II virtual memory interface. + * Copyright (C) 1991 Advanced RISC Machines Limited. All rights reserved. + ***************************************************************************/ + +/* + * RCS $Revision: 1.19.2.4 $ + * Checkin $Date: 1995/08/31 09:36:54 $ + * Revising $Author: plg $ + */ + +/* This file contains a complete ARMulator memory model, modelling a +"virtual memory" system. A much simpler model can be found in +armfast.c, and that model goes faster too, but has a fixed amount of +memory. This model's memory has 64K pages, allocated on demand from a +64K entry page table, when the page is first written. Reads to an +unwritten (un-allocated) page are serviced by an access to a dummy page. +Pages are never freed as they might be needed again. A single area of +memory can be defined to generate aborts. */ + +#include "armdefs.h" + +/* The following hack, if defined, uses the F counter to count 32 bit + word accesses. This is useful when pretending to have 16 bit wide memory. + */ +/* #define RUN_IN_16_BIT_MEMORY_HACK */ + + +#ifdef VALIDATE /* for running the validate suite */ +#define TUBE 48 * 1024 * 1024 /* write a char on the screen */ +#define ABORTS 1 +#endif + +#ifdef ABORTS /* the memory system will abort */ +/* For the old test suite Abort between 32 Kbytes and 32 Mbytes + For the new test suite Abort between 8 Mbytes and 26 Mbytes */ +#define LOWABORT 32 * 1024 +#define HIGHABORT 32 * 1024 * 1024 +/* #define LOWABORT 8 * 1024 * 1024 +#define HIGHABORT 26 * 1024 * 1024 */ +#endif + +#define TOP_OF_MEM 0x80000000 /* 2Gb to avoid stack-checking probs */ +#define NUMPAGES 64 * 1024 +#define PAGESIZE 64 * 1024 +#define PAGEBITS 16 +#define WORDOFFSETBITS 0xfffc +#define HWRDOFFSETBITS 0xfffe +#define BYTEOFFSETBITS 0xffff +#define ENDSWAP(addr) (addr ^ 3) +#define ENDSWAPH(addr) (addr ^ 2) +static unsigned HostEndian ; + +#define PAGETABLE ((unsigned char **)state->MemDataPtr) +#define DUMMYPAGE ((unsigned char *)state->MemSparePtr) + +/***************************************************************************\ +* Get a Word/Byte from Virtual Memory * +\***************************************************************************/ + +#define GetWord(state, address) \ + *( (ARMword *) \ + ( *(PAGETABLE + (address >> PAGEBITS)) + (address & WORDOFFSETBITS) ) \ + ) + +#define GetHalfWord(state, address) \ + (HostEndian ? \ + ( \ + (*( *(PAGETABLE + (address >> PAGEBITS)) + (address & HWRDOFFSETBITS)) << 8) + \ + *( *(PAGETABLE + (address >> PAGEBITS)) + (address & HWRDOFFSETBITS) + 1) \ + ) : \ + ( \ + *( *(PAGETABLE + (address >> PAGEBITS)) + (address & HWRDOFFSETBITS)) + \ + (*( *(PAGETABLE + (address >> PAGEBITS)) + (address & HWRDOFFSETBITS) + 1) << 8) \ + )) + +#define GetByte(state, address) \ + *( \ + ( *(PAGETABLE + (address >> PAGEBITS)) + (address & BYTEOFFSETBITS) ) \ + ) + +/***************************************************************************\ +* Put a Word/Byte into Virtual Memory, maybe allocating the page * +\***************************************************************************/ + +#define PutWord(state, address, data) \ + {unsigned char *xxpageptr; \ + if ((xxpageptr = PAGETABLE[address >> PAGEBITS]) == DUMMYPAGE) \ + xxpageptr = AllocatePage(state,address); \ + *(ARMword *)(xxpageptr + (address & WORDOFFSETBITS)) = data; \ + } + +#define PutHalfWord(state, address, data) \ + {unsigned char *xxpageptr; \ + ARMword xxaddr; \ + if ((xxpageptr = PAGETABLE[(address) >> PAGEBITS]) == DUMMYPAGE) \ + xxpageptr = AllocatePage(state, address); \ + xxaddr = (address) & HWRDOFFSETBITS; \ + if (HostEndian) { \ + xxpageptr[xxaddr] = (unsigned char)(((data) & 0xff00) >> 8); \ + xxpageptr[xxaddr + 1] = (unsigned char)((data) & 0xff); \ + } else { \ + xxpageptr[xxaddr] = (unsigned char)((data) & 0xff); \ + xxpageptr[xxaddr + 1] = (unsigned char)(((data) & 0xff00) >> 8); \ + } \ + } + +#define PutByte(state, address, data) \ + {unsigned char *xxpageptr ; \ + if ((xxpageptr = PAGETABLE[address >> PAGEBITS]) == DUMMYPAGE) \ + xxpageptr = AllocatePage(state,address) ; \ + xxpageptr[address & BYTEOFFSETBITS] = (unsigned char)data ; \ + } + +/***************************************************************************\ +* Allocate and return a memory page * +\***************************************************************************/ + +static unsigned char * AllocatePage(ARMul_State *state, ARMword address) +{unsigned char *pageptr ; + + pageptr = (unsigned char *)malloc(PAGESIZE) ; + if (pageptr == NULL) { + perror("ARMulator can't allocate VM page") ; + exit(13) ; + } + *(PAGETABLE + (address >> PAGEBITS)) = pageptr ; + return(pageptr) ; + } + +/***************************************************************************\ +* Initialise the memory interface * +\***************************************************************************/ + +unsigned ARMul_MemoryInit(ARMul_State *state, unsigned long initmemsize) +{unsigned char **pagetable ; + unsigned page ; + unsigned char *dummypage ; + + if (initmemsize == 0) + state->MemSize = TOP_OF_MEM; /* initialise to 4Gb if no size specified */ + else + state->MemSize = initmemsize; + if ((pagetable = (unsigned char **)malloc(sizeof(ARMword *)*NUMPAGES))==NULL) + return(FALSE) ; + if ((dummypage = (unsigned char *)malloc(PAGESIZE))==NULL) + return(FALSE) ; + for (page = 0 ; page < NUMPAGES ; page++) + *(pagetable + page) = dummypage ; + state->MemDataPtr = (unsigned char *)pagetable ; + state->MemSparePtr = (unsigned char *)dummypage ; + *(ARMword *)dummypage = 1 ; + HostEndian = (*dummypage != 1) ; /* 1 for big endian, 0 for little */ + *(ARMword *)dummypage = 0 ; +#ifdef BIGEND + state->bigendSig = HIGH ; +#endif +#ifdef LITTLEEND + state->bigendSig = LOW ; +#endif + if (state->MemSize >= 10 * 1024 * 1024) + ARMul_ConsolePrint(state, ", %dMbyte",state->MemSize/1024/1024); + else + ARMul_ConsolePrint(state, ", %dKbyte",state->MemSize/1024); + return(TRUE) ; +} + +/***************************************************************************\ +* Remove the memory interface * +\***************************************************************************/ + +void ARMul_MemoryExit(ARMul_State *state) +{ARMword page ; + unsigned char *pageptr ; + + for (page = 0 ; page < NUMPAGES ; page++) { + pageptr = *(PAGETABLE + page) ; + if (pageptr != DUMMYPAGE) + free((unsigned char *)pageptr) ; + } + free((unsigned char *)DUMMYPAGE) ; + free((unsigned char *)PAGETABLE) ; + return ; + } + +/***************************************************************************\ +* Load Instruction, Sequential Cycle * +\***************************************************************************/ + +#define NS_PER_S 1000000000 +#define ADDNS(p,t) \ + do { \ + (p)->a.ns += (p)->t; \ + if ((p)->a.ns >= NS_PER_S) (p)->a.ns -= NS_PER_S, (p)->a.s++; } \ + while (0) + +ARMword ARMul_LoadInstrS(ARMul_State *state,ARMword address) +{ + MemDescr *m; + + state->NumScycles++ ; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Sreads += 4L >> m->md.width; + ADDNS(m, ns_LoadInstrS); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef HOURGLASS_RATE + if( ( state->NumScycles & HOURGLASS_RATE ) == 0 ) { + armsd_hourglass(); + } +#endif + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_PREFETCHABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + return(GetWord(state,address)) ; +} + +/***************************************************************************\ +* Load Instruction, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstrN(ARMul_State *state,ARMword address) +{ + MemDescr *m; + + state->NumNcycles++ ; +#ifdef RUN_IN_16_BIT_MEMORY_HACK +state->NumFcycles++ ; +#endif + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nreads++; + m->a.Sreads += (4L >> m->md.width) - 1; + ADDNS(m, ns_LoadInstrN); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_PREFETCHABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + return(GetWord(state,address)) ; +} + +/***************************************************************************\ +* Load 16 bit Instruction, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstr16S(ARMul_State *state,ARMword address) +{ + MemDescr *m; + ARMword temp ; + + state->NumScycles++ ; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + if ((m->md.access & 4) && (address & 2) && m->md.width == 2) { + m->a.ns += state->cpu_ns; + } else { + m->a.Sreads++; + if (m->md.width == 0) m->a.Sreads++; + m->a.ns += m->ns_LoadInstr16S; + } + if (m->a.ns >= NS_PER_S) m->a.ns -= NS_PER_S, m->a.s++; + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef HOURGLASS_RATE + if( ( state->NumScycles & HOURGLASS_RATE ) == 0 ) { + armsd_hourglass(); + } +#endif + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_PREFETCHABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAPH(address) ; + return((ARMword)GetHalfWord(state,temp)) ; +} + +/***************************************************************************\ +* Load 16 bit Instruction, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstr16N(ARMul_State *state,ARMword address) +{ + MemDescr *m; + ARMword temp ; + + state->NumNcycles++ ; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nreads++; + if (m->md.width == 0) m->a.Sreads++; + ADDNS(m, ns_LoadInstr16N); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_PREFETCHABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAPH(address) ; + return((ARMword)GetHalfWord(state,temp)) ; + } + +/***************************************************************************\ +* Load Word, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadWordS(ARMul_State *state,ARMword address) +{ + MemDescr *m; + + state->NumScycles++ ; +#ifdef RUN_IN_16_BIT_MEMORY_HACK +state->NumFcycles++ ; +#endif + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Sreads += 4L >> m->md.width; + ADDNS(m, ns_LoadWordS); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(0) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + return(GetWord(state,address)) ; + } + +/***************************************************************************\ +* Load Word, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadWordN(ARMul_State *state,ARMword address) +{ + MemDescr *m; + + state->NumNcycles++ ; +#ifdef RUN_IN_16_BIT_MEMORY_HACK +state->NumFcycles++ ; +#endif + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nreads++; + m->a.Sreads += (4L >> m->md.width) - 1; + ADDNS(m, ns_LoadWordN); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(0) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + return(GetWord(state,address)) ; + } + +/***************************************************************************\ +* Load Halfword, (Non Sequential Cycle) * +\***************************************************************************/ + +ARMword ARMul_LoadHalfWord(ARMul_State *state,ARMword address) +{ + MemDescr *m; + ARMword temp ; + + state->NumNcycles++ ; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nreads++; + if (m->md.width == 0) m->a.Sreads++; + ADDNS(m, ns_LoadHalfWord); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(0) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAPH(address) ; + return((ARMword)GetHalfWord(state,temp)) ; + } + +/***************************************************************************\ +* Load Byte, (Non Sequential Cycle) * +\***************************************************************************/ + +ARMword ARMul_LoadByte(ARMul_State *state,ARMword address) +{ + MemDescr *m; + ARMword temp ; + + state->NumNcycles++ ; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nreads++; + ADDNS(m, ns_LoadByte); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(0) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAP(address) ; + return((ARMword)GetByte(state,temp)) ; + } + +/***************************************************************************\ +* Store Word, Sequential Cycle * +\***************************************************************************/ + +void ARMul_StoreWordS(ARMul_State *state,ARMword address, ARMword data) +{ + MemDescr *m; + + state->NumScycles++ ; +#ifdef RUN_IN_16_BIT_MEMORY_HACK +state->NumFcycles++ ; +#endif + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Swrites += 4L >> m->md.width; + ADDNS(m, ns_StoreWordS); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + PutWord(state,address,data) ; + } + +/***************************************************************************\ +* Store Word, Non Sequential Cycle * +\***************************************************************************/ + +void ARMul_StoreWordN(ARMul_State *state, ARMword address, ARMword data) +{ + MemDescr *m; + + state->NumNcycles++ ; +#ifdef RUN_IN_16_BIT_MEMORY_HACK +state->NumFcycles++ ; +#endif + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nwrites++; + m->a.Swrites += (4L >> m->md.width) - 1; + ADDNS(m, ns_StoreWordN); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + PutWord(state,address,data) ; + } + +/***************************************************************************\ +* Store HalfWord, Non Sequential Cycle * +\***************************************************************************/ + +void ARMul_StoreHalfWord(ARMul_State *state, ARMword address, ARMword data) +{ + MemDescr *m; + ARMword temp ; + + state->NumNcycles++ ; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nwrites++; + if (m->md.width == 0) m->a.Swrites++; + ADDNS(m, ns_StoreHalfWord); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAPH(address) ; + PutHalfWord(state,temp,data) ; +} + +/***************************************************************************\ +* Store Byte, (Non Sequential Cycle) * +\***************************************************************************/ + +void ARMul_StoreByte(ARMul_State *state, ARMword address, ARMword data) +{ + MemDescr *m; + + ARMword temp ; + + state->NumNcycles++ ; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nwrites++; + ADDNS(m, ns_StoreByte); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef VALIDATE + if (address == TUBE) { + if (data == 4) + state->Emulate = FALSE ; + else + (void)putc((char)data,stderr) ; /* Write Char */ + return ; + } +#endif + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAP(address) ; + PutByte(state,temp,(unsigned char)data) ; + } + +/***************************************************************************\ +* Swap Word, (Two Non Sequential Cycles) * +\***************************************************************************/ + +ARMword ARMul_SwapWord(ARMul_State *state, ARMword address, ARMword data) +{ + MemDescr *m; + ARMword temp ; + + state->NumNcycles+=2; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nreads++; + m->a.Nwrites++; + m->a.Sreads += (4L >> m->md.width) - 1; + m->a.Swrites += (4L >> m->md.width) - 1; + ADDNS(m, ns_SwapWord); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = GetWord(state,address) ; + PutWord(state,address,data) ; + return(temp) ; +} + +/***************************************************************************\ +* Swap Byte, (Two Non Sequential Cycles) * +\***************************************************************************/ + +ARMword ARMul_SwapByte(ARMul_State *state, ARMword address, ARMword data) +{ + MemDescr *m; + ARMword temp ; + + state->NumNcycles+=2; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nreads++; + m->a.Nwrites++; + ADDNS(m, ns_SwapByte); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = ARMul_LoadByte(state,address) ; + ARMul_StoreByte(state,address,data) ; + return(temp) ; + } + +/***************************************************************************\ +* Count I Cycles * +\***************************************************************************/ + +void ARMul_Icycles(ARMul_State *state, unsigned number, ARMword address) +{ + state->NumIcycles += number ; + state->ns += state->cpu_ns * number; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + ARMul_CLEARABORT ; + } + +/***************************************************************************\ +* Count C Cycles * +\***************************************************************************/ + +void ARMul_Ccycles(ARMul_State *state, unsigned number, ARMword address) +{ + state->NumCcycles += number ; + state->ns += state->cpu_ns * number; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + ARMul_CLEARABORT ; + } + +/***************************************************************************\ +* Read Word (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadWord(ARMul_State *state, ARMword address) +{ +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + return(GetWord(state,address)) ; + } + +/***************************************************************************\ +* Read HalfWord (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadHalfWord(ARMul_State *state, ARMword address) +{ARMword temp; +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAPH(address) ; + return((ARMword)GetHalfWord(state,temp)) ; + } + +/***************************************************************************\ +* Read Byte (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadByte(ARMul_State *state, ARMword address) +{ARMword temp ; + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAP(address) ; + return((ARMword)GetByte(state,temp)) ; + } + +/***************************************************************************\ +* Write Word (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteWord(ARMul_State *state, ARMword address, ARMword data) +{ +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + PutWord(state,address,data) ; + } + +/***************************************************************************\ +* Write HalfWord (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteHalfWord(ARMul_State *state, ARMword address, ARMword data) +{ARMword temp; +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAPH(address) ; + PutHalfWord(state,temp,data) ; + } + +/***************************************************************************\ +* Write Byte (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteByte(ARMul_State *state, ARMword address, ARMword data) +{ARMword temp ; + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAP(address) ; + PutByte(state,temp,(unsigned char)data) ; + } + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/DLL/ARMULATE.MAK b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/DLL/ARMULATE.MAK new file mode 100644 index 0000000..ea2eb90 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/DLL/ARMULATE.MAK @@ -0,0 +1,29 @@ +SRCDIR1=..\.. +EXTDIR1=..\..\..\clx +EXTDIR2=..\..\..\armdbg +CFLAGS= -O2 -c -D__STDC__ -D_WINDOWS -DCODE16 /MT -DWIN32 -I$(SRCDIR1) -I$(EXTDIR1) -I$(EXTDIR2) -DHOURGLASS_RATE=8191 -DRDI_VERBOSE +CC=cl +TOLOCAL=copy +OBJALL=ARMULDLL.OBJ ARMCOPRO.OBJ ARMOS.OBJ ARMVIRT.OBJ +ARMULLIB=..\iarm.lib +WINLIBS=user32.lib +RC=rc + +#rules +armulate.dll: $(OBJALL) +armulate.dll: $(ARMULLIB) + del $@ + link.exe /DEFAULTLIB:$(WINLIBS) /DLL /DEF:"..\..\armulate.def" /SUBSYSTEM:CONSOLE /INCREMENTAL:no /OUT:"armulate.dll" $(OBJALL) $(ARMULLIB) + +armuldll.obj: ..\..\armuldll.c +armuldll.obj: ..\..\armuldll.h + $(CC) $(CFLAGS) ..\..\armuldll.c + +armcopro.obj: $(SRCDIR1)\armcopro.c + $(CC) $(CFLAGS) $(SRCDIR1)\armcopro.c + +armos.obj: $(SRCDIR1)\armos.c + $(CC) $(CFLAGS) $(SRCDIR1)\armos.c + +armvirt.obj: $(SRCDIR1)\armvirt.c + $(CC) $(CFLAGS) $(SRCDIR1)\armvirt.c diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/IARM.LIB b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/IARM.LIB new file mode 100644 index 0000000..d5b167d Binary files /dev/null and b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/IARM.LIB differ -- cgit v1.2.3