From 33613a85afc4b1481367fbe92a17ee59c240250b Mon Sep 17 00:00:00 2001 From: Sven Eisenhauer Date: Fri, 10 Nov 2023 15:11:48 +0100 Subject: add new repo --- .../ARM202U/SOURCE/WIN32/ARMDBG/ARMDBG.H | 1137 +++++++++++++ .../ARM202U/SOURCE/WIN32/ARMDBG/DBG_CONF.H | 47 + .../ARM202U/SOURCE/WIN32/ARMDBG/DBG_CP.H | 57 + .../ARM202U/SOURCE/WIN32/ARMDBG/DBG_HIF.H | 46 + .../ARM202U/SOURCE/WIN32/ARMDBG/DBG_RDI.H | 614 +++++++ .../ARM202U/SOURCE/WIN32/ARMDBG/DBG_STAT.H | 37 + .../ARM202U/SOURCE/WIN32/ARMUL/ARMCOPRO.C | 360 +++++ .../ARM202U/SOURCE/WIN32/ARMUL/ARMDEFS.H | 509 ++++++ .../ARM202U/SOURCE/WIN32/ARMUL/ARMFAST.C | 365 +++++ .../ARM202U/SOURCE/WIN32/ARMUL/ARMFPE.H | 1701 ++++++++++++++++++++ .../ARM202U/SOURCE/WIN32/ARMUL/ARMOS.C | 828 ++++++++++ .../ARM202U/SOURCE/WIN32/ARMUL/ARMOS.H | 64 + .../ARM202U/SOURCE/WIN32/ARMUL/ARMPROTO.C | 512 ++++++ .../ARM202U/SOURCE/WIN32/ARMUL/ARMULATE.DEF | 28 + .../ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.C | 122 ++ .../ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.H | 62 + .../ARM202U/SOURCE/WIN32/ARMUL/ARMVIRT.C | 871 ++++++++++ .../SOURCE/WIN32/ARMUL/MSVC20/DLL/ARMULATE.MAK | 29 + .../ARM202U/SOURCE/WIN32/ARMUL/MSVC20/IARM.LIB | Bin 0 -> 175136 bytes .../ARM202U/SOURCE/WIN32/CLX/AIF.H | 52 + .../ARM202U/SOURCE/WIN32/CLX/ASDFMT.H | 473 ++++++ .../ARM202U/SOURCE/WIN32/CLX/HOST.H | 279 ++++ .../ARM202U/SOURCE/WIN32/CLX/IEEEFLT.H | 75 + .../ARM202U/SOURCE/WIN32/CLX/MSG.H | 104 ++ .../ARM202U/SOURCE/WIN32/CLX/MSVC20/CLX.LIB | Bin 0 -> 143530 bytes 25 files changed, 8372 insertions(+) create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/ARMDBG.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_CONF.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_CP.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_HIF.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_RDI.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_STAT.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMCOPRO.C create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMDEFS.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFAST.C create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFPE.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.C create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMPROTO.C create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULATE.DEF create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.C create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMVIRT.C create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/DLL/ARMULATE.MAK create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/IARM.LIB create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/AIF.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/ASDFMT.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/HOST.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/IEEEFLT.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/MSG.H create mode 100644 Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/MSVC20/CLX.LIB (limited to 'Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE') diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/ARMDBG.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/ARMDBG.H new file mode 100644 index 0000000..93ec407 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/ARMDBG.H @@ -0,0 +1,1137 @@ +/* + * ARM symbolic debugger toolbox interface + * Copyright (C) 1992 Advanced Risc Machines Ltd. All rights reserved. + */ + +/* + * RCS $Revision: 1.62.2.8 $ + * Checkin $Date: 1995/06/09 15:38:00 $ + * Revising $Author: plg $ + */ + +/* Minor points of uncertainty are indicated by a question mark in the + LH margin. + + Wherever an interface is required to iterate over things of some class, + I prefer something of the form EnumerateXXs(..., XXProc *p, void *arg) + which results in a call of p(xx, arg) for each xx, rather than something + of the form + for (xxh = StartIterationOverXXs(); (xx = Next(xxh)) != 0; ) { ... } + EndIterationOverXXs(xxh); + Others may disagree. + (Each XXProc returns an Error value: if this is not Err_OK, iteration + stops immediately and the EnumerateXXs function returns that value). + + ptrace has been retired as of insufficient utility. If such fuctionality is + required, it can be constructed using breakpoints. + + The file form of all name fields in debug areas is in-line, with a length + byte and no terminator. The debugger toolbox makes an in-store translation, + where the strings are out of line (the namep variant in asdfmt.h) and have a + terminating zero byte: the pointer is to the first character of the string + with the length byte at ...->n.namep[-1]. + */ + +#ifndef armdbg__h +#define armdbg__h + +#include + +#include "asdfmt.h" +#include "host.h" +#include "ieeeflt.h" +#include "msg.h" + +typedef unsigned32 ARMaddress; +typedef unsigned32 ARMword; +typedef unsigned16 ARMhword; + +#include "dbg_conf.h" +#include "dbg_rdi.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef unsigned char Dbg_Byte; + +typedef int Dbg_Error; + +typedef struct Dbg_MCState Dbg_MCState; +/* A representation of the state of the target. The structure is not revealed. + A pointer to one of these is returned by Dbg_Initialise(), is passed to all + toolbox calls which refer to the state of the target, and is discarded + by Dbg_Finalise(). + Nothing in the toolbox itself precludes there being multiple targets, each + with its own state. + */ + +/* Most toolbox interfaces return an error status. Only a few of the status + values are expected to be interesting to clients and defined here; the + rest are private (but a textual form can be produced by ErrorToChars()). + */ + +#define Error_OK 0 + +/* Partitioning of the error code space: errors below Dbg_Error_Base are RDI + errors (as defined in dbg_rdi.h). Codes above Dbg_Error_Limit are + available to clients, who may impose some further structure. + */ +#define Dbg_Error_Base 0x1000 +#define Dbg_Error_Limit 0x2000 + +#define DbgError(n) ((Dbg_Error)(Dbg_Error_Base+(n))) + +#define Dbg_Err_OK Error_OK +#define Dbg_Err_Interrupted (DbgError(1)) +#define Dbg_Err_Overflow (DbgError(2)) +#define Dbg_Err_FileNotFound (DbgError(3)) +#define Dbg_Err_ActivationNotPresent (DbgError(4)) +#define Dbg_Err_OutOfHeap (DbgError(5)) +#define Dbg_Err_TypeNotSimple (DbgError(6)) +#define Dbg_Err_BufferFull (DbgError(7)) +#define Dbg_Err_AtStackBase (DbgError(8)) +#define Dbg_Err_AtStackTop (DbgError(9)) +#define Dbg_Err_DbgTableFormat (DbgError(10)) +#define Dbg_Err_NotVariable (DbgError(11)) +#define Dbg_Err_NoSuchBreakPoint (DbgError(12)) +#define Dbg_Err_NoSuchWatchPoint (DbgError(13)) +#define Dbg_Err_FileLineNotFound (DbgError(14)) +#define Dbg_Err_DbgTableVersion (DbgError(15)) +#define Dbg_Err_NoSuchPath (DbgError(16)) +#define Dbg_Err_StateChanged (DbgError(17)) +#define Dbg_Err_SoftInitialiseError (DbgError(18)) +#define Dbg_Err_CoProRegNotWritable (DbgError(19)) +#define Dbg_Err_NotInHistory (DbgError(20)) + + /* functions which evaluate expressions may return this value, to indicate + that execution became suspended within a function called in the debugee */ + +/* Functions returning characters take a BufDesc argument, with fields buffer + and bufsize being input arguments describing the buffer to be filled, and + filled being set on return to the number of bytes written to the buffer + (omitting the terminating 0). + */ + +typedef struct Dbg_BufDesc Dbg_BufDesc; + +typedef void Dbg_BufferFullProc(Dbg_BufDesc *bd); + +struct Dbg_BufDesc { + char *buffer; + size_t size, + filled; + Dbg_BufferFullProc *p; + void *arg; +}; + +#define Dbg_InitBufDesc(bd, buf, bytes) \ + ((bd).buffer = (buf), (bd).size = (bytes), (bd).filled = 0,\ + (bd).p = NULL, (bd).arg = NULL) + +#define Dbg_InitBufDesc_P(bd, buf, bytes, fn, a) \ + ((bd).buffer = (buf), (bd).size = (bytes), (bd).filled = 0,\ + (bd).p = (fn), (bd).arg = (a)) + +Dbg_Error Dbg_StringToBuf(Dbg_BufDesc *buf, char const *s); +Dbg_Error Dbg_BufPrintf(Dbg_BufDesc *buf, char const *form, ...); +#ifdef NLS +Dbg_Error Dbg_MsgToBuf(Dbg_BufDesc *buf, msg_t t); +Dbg_Error Dbg_BufMsgPrintf(Dbg_BufDesc *buf, msg_t form, ...); +#else +#define Dbg_MsgToBuf Dbg_StringToBuf +#define Dbg_BufMsgPrintf Dbg_BufPrintf +#endif +Dbg_Error Dbg_CharToBuf(Dbg_BufDesc *buf, int ch); + +int Dbg_CIStrCmp(char const *s1, char const *s2); +/* Case-independent string comparison, interface as for strcmp */ + +void Dbg_ErrorToChars(Dbg_MCState *state, Dbg_Error err, Dbg_BufDesc *buf); + +typedef int Dbg_RDIResetCheckProc(int); +/* Type of a function to be called after each RDI operation performed by the + toolbox, with the status from the operation as argument. The value returned + is treated as the status. (The intent is to allow the toolbox's client to + take special action to handle RDIDbg_Error_Reset). + */ + +typedef struct Dbg_CoProDesc Dbg_CoProDesc; + +typedef Dbg_Error Dbg_CoProFoundProc(Dbg_MCState *state, int cpno, Dbg_CoProDesc const *cpd); +/* Type of a function to be called when the shape of a coprocessor is discovered + by enquiry of the target or agent (via RequestCoProDesc) + */ + +typedef struct RDIProcVec RDIProcVec; + +Dbg_Error Dbg_Initialise( + Dbg_ConfigBlock *config, Dbg_HostosInterface const *i, + Dbg_RDIResetCheckProc *checkreset, Dbg_CoProFoundProc *coprofound, + RDIProcVec const *rdi, Dbg_MCState **statep); +/* values in config are updated if they call for default values */ + +void Dbg_Finalise(Dbg_MCState *state); + +typedef struct { + char name[16]; + RDI_MemDescr md; + RDI_MemAccessStats a; +} Dbg_MemStats; + +/*--------------------------------------------------------------------------*/ + +/* Symbol table management. + The structure of a Dbg_SymTable is not revealed. It is created by + Dbg_ReadSymbols() or by Dbg_LoadFile(), and associated with the argument + Dbg_MCState. + Many symbol tables may be concurrently active. + A Dbg_SymTable is removed either explicitly (by call to Dbg_DeleteSymbols) + or implicitly when a symbol table for an overlapping address range is read. + + There is a pre-defined symbol table containing entries for ARM registers, + co-processor registers and the like. + */ + +typedef struct Dbg_SymTable Dbg_SymTable; + +typedef struct Dbg_ImageFragmentDesc { + ARMaddress base, limit; +} Dbg_ImageFragmentDesc; + +typedef struct Dbg_ImageDesc { + int lang; + int executable; + ARMaddress robase, rolimit, rwbase, rwlimit; + int nfrags; + Dbg_ImageFragmentDesc *fragments; +} Dbg_ImageDesc; + +Dbg_ImageDesc *Dbg_ImageAreas(Dbg_SymTable *st); + +Dbg_SymTable *Dbg_NewSymTable(Dbg_MCState *state, const char *name); + +Dbg_Error Dbg_ReadSymbols(Dbg_MCState *state, const char *filename, Dbg_SymTable **st); +/* Just read the symbols from the named image. is set to the allocated + symbol table. +? Maybe we could usefully allow other formats than AIF images to describe + the symbols (eg) of shared libraries + */ + +typedef struct Dbg_SymInfo { + int isize; + ARMaddress addr; + char *name; +} Dbg_SymInfo; + +Dbg_SymInfo *Dbg_AsmSym(Dbg_SymTable *st, ARMaddress addr); +int32 Dbg_AsmAddr(Dbg_SymTable *st, int32 line); +int32 Dbg_AsmLine(Dbg_SymTable *st, ARMaddress addr); +int32 Dbg_AsmLinesInRange(Dbg_SymTable *st, ARMaddress start, ARMaddress end); + +Dbg_Error Dbg_LoadFile(Dbg_MCState *state, const char *filename, Dbg_SymTable **st); +/* load the image into target memory, and read its symbols. is set to + the allocated symbol table. + A null filename reloads the most recently loaded file (and rereads its + symbols). + Loading an image leaves breakpoints unchanged. If a client wishes + otherwise, it must remove the breakpoints explicitly. +*/ + +Dbg_Error Dbg_CallGLoadFile(Dbg_MCState *state, const char *filename, Dbg_SymTable **st); + +Dbg_Error Dbg_LoadAgent(Dbg_MCState *state, const char *filename); +/* Load a debug agent, and start it. + Symbols in the image for the agent are ignored. +*/ + +Dbg_Error Dbg_RelocateSymbols(Dbg_SymTable *st, ARMaddress reloc); +/* add to the value of all symbols in describing absolute memory + locations. The intent is to allow the symbols in a load-time relocating + image (for example) to be useful. + */ + +Dbg_Error Dbg_DeleteSymbols(Dbg_MCState *state, Dbg_SymTable **st); + +typedef enum Dbg_LLSymType { + llst_code, + llst_code16, + llst_data, + llst_const +} Dbg_LLSymType; +/* Since AIF images contain no type information for low-level symbols, this + classification is only a guess, and some symbols describing constants will + incorrectly be described as code or data. + */ + +typedef Dbg_Error Dbg_SymProc( + Dbg_MCState *state, + const char *symbol, Dbg_LLSymType symtype, ARMaddress value, + void *arg); + +Dbg_Error Dbg_EnumerateLowLevelSymbols( + Dbg_MCState *state, const char *match, Dbg_SymProc *p, + void *arg); +/* Call p(name, value) for each low level symbol in the tables of + whose name matches the regular expression (a NULL matches + any name). Symbols are enumerated in no particular order. + */ + +/*--------------------------------------------------------------------------*/ + +/* Functions are provided here to allow quick mass access to register values + for display. There is no comparable need for quick mass update, so writing + should be via Assign(). + */ + +typedef struct Dbg_RegSet { + ARMword + user[15], + pc, + psr, + fiq[7], + spsr_fiq, + irq[2], + spsr_irq, + svc[2], + spsr_svc, + abort[2], + spsr_abort, + undef[2], + spsr_undef; +} Dbg_RegSet; + +/* bits in the modemask argument for ReadRegisters */ + +#define Dbg_MM_User 1 +#define Dbg_MM_FIQ 2 +#define Dbg_MM_IRQ 4 +#define Dbg_MM_SVC 8 +#define Dbg_MM_Abort 0x10 +#define Dbg_MM_Undef 0x20 +#define Dbg_MM_System 0x40 + +Dbg_Error Dbg_ReadRegisters(Dbg_MCState *state, Dbg_RegSet *regs, int modemask); + +Dbg_Error Dbg_WriteRegister(Dbg_MCState *state, int rno, int modemask, ARMword val); + +int Dbg_StringToMode(const char *name); + +int Dbg_ModeToModeMask(ARMword mode); + +/* Some implementations of the FP instruction set keep FP values loaded into + registers in their unconverted format, converting only when necessary. + Some RDI implementations deliver these values uninterpreted. + (For the rest, register values will always have type F_Extended). + */ + +typedef enum { F_Single, F_Double, F_Extended, F_Packed, /* fpe340 values */ + F_Internal, /* new fpe : mostly as extended */ + F_None } Dbg_FPType; + +typedef struct { ARMword w[3]; } Dbg_TargetExtendedVal; +typedef struct { ARMword w[3]; } Dbg_TargetPackedVal; +typedef struct { ARMword w[2]; } Dbg_TargetDoubleVal; +typedef struct { ARMword w[1]; } Dbg_TargetFloatVal; + +typedef union { Dbg_TargetExtendedVal e; Dbg_TargetPackedVal p; + Dbg_TargetDoubleVal d; Dbg_TargetFloatVal f; } Dbg_TargetFPVal; + +#define TargetSizeof_Extended 12 +#define TargetSizeof_Packed 12 +#define TargetSizeof_Double 8 +#define TargetSizeof_Float 4 + +typedef struct Dbg_FPRegVal { + Dbg_FPType type; + Dbg_TargetFPVal v; +} Dbg_FPRegVal; + +typedef struct Dbg_FPRegSet { + Dbg_FPRegVal f[8]; + ARMword fpsr, fpcr; +} Dbg_FPRegSet; + +Dbg_Error Dbg_ReadFPRegisters(Dbg_MCState *state, Dbg_FPRegSet *regs); + +Dbg_Error Dbg_WriteFPRegisters(Dbg_MCState *state, int32 mask, Dbg_FPRegSet *regs); + +Dbg_Error Dbg_FPRegToDouble(DbleBin *d, Dbg_FPRegVal const *f); +/* Converts from a FP register value (in any format) to a double with + approximately the same value (or returns Dbg_Err_Overflow) + */ + +void Dbg_DoubleToFPReg(Dbg_FPRegVal *f, DbleBin const *d); +/* Converts the double to a Dbg_FPRegVal with type F_Extended */ + +/*--------------------------------------------------------------------------*/ + +#include "dbg_cp.h" + +Dbg_Error Dbg_DescribeCoPro(Dbg_MCState *state, int cpnum, Dbg_CoProDesc *p); + +Dbg_Error Dbg_DescribeCoPro_RDI(Dbg_MCState *state, int cpnum, Dbg_CoProDesc *p); + +Dbg_Error Dbg_ReadCPRegisters(Dbg_MCState *state, int cpnum, ARMword *regs); + +Dbg_Error Dbg_WriteCPRegisters(Dbg_MCState *state, int cpnum, int32 mask, ARMword *regs); + +/*--------------------------------------------------------------------------*/ + +Dbg_Error Dbg_ReadWords( + Dbg_MCState *state, + ARMword *words, ARMaddress addr, unsigned count); +/* Reads a number of (32-bit) words from target store. The values are in host + byte order; if they are also to be interpreted as bytes Dbg_SwapByteOrder() + must be called to convert to target byte order. + */ + +Dbg_Error Dbg_WriteWords( + Dbg_MCState *state, + ARMaddress addr, const ARMword *words, unsigned count); +/* Writes a number of (32-bit) words to target store. The values are in host + byte order (if what is being written is actually a byte string it must be + converted by Dbg_SwapByteOrder()). + */ + +Dbg_Error Dbg_ReadHalf(Dbg_MCState *state, ARMhword *val, ARMaddress addr); +Dbg_Error Dbg_WriteHalf(Dbg_MCState *state, ARMaddress addr, ARMword val); + +Dbg_Error Dbg_ReadBytes(Dbg_MCState *state, Dbg_Byte *val, ARMaddress addr, unsigned count); +Dbg_Error Dbg_WriteBytes(Dbg_MCState *state, ARMaddress addr, const Dbg_Byte *val, unsigned count); + +void Dbg_HostWords(Dbg_MCState *state, ARMword *words, unsigned wordcount); +/* (A noop unless host and target bytesexes differ) */ + +ARMword Dbg_HostWord(Dbg_MCState *state, ARMword v); + +ARMhword Dbg_HostHalf(Dbg_MCState *state, ARMword v); + +/*--------------------------------------------------------------------------*/ + +/* Types describing various aspects of position within code. + There are rather a lot of these, in the interests of describing precisely + what fields must be present (rather than having a single type with many + fields which may or may not be valid according to context). + */ + +typedef struct Dbg_LLPos { + Dbg_SymTable *st; + char *llsym; + ARMaddress offset; +} Dbg_LLPos; + +typedef struct Dbg_File { + Dbg_SymTable *st; + char *file; +} Dbg_File; + +typedef struct Dbg_Line { + unsigned32 line; /* linenumber in the file */ + unsigned16 statement, /* within the line (1-based) */ + charpos; /* ditto */ +} Dbg_Line; +/* As an output value from toolbox functions, both statement and charpos are set + if the version of the debugger tables for the section concerned permits. + On input, is used only if is 0 (in which case, if + is non-0, Dbg_Err_DbgTableVersion is returned if the version of + the debugger tables concerned is too early. + */ + +typedef struct Dbg_FilePos { + Dbg_File f; + Dbg_Line line; +} Dbg_FilePos; + +typedef struct Dbg_ProcDesc { + Dbg_File f; + char *name; +} Dbg_ProcDesc; + +typedef struct Dbg_ProcPos { + Dbg_ProcDesc p; + Dbg_Line line; +} Dbg_ProcPos; + +/* Support for conversions between position representations */ + +Dbg_Error Dbg_ProcDescToLine(Dbg_MCState *state, Dbg_ProcDesc *proc, Dbg_Line *line); +/* If proc->f.file is null (and there is just one function proc->name), it is + updated to point to the name of the file containing (the start of) + proc->name. + */ + +Dbg_Error Dbg_FilePosToProc(Dbg_MCState *state, const Dbg_FilePos *pos, char **procname); + +/* Conversions from position representations to and from code addresses */ + +Dbg_Error Dbg_AddressToProcPos( + Dbg_MCState *state, ARMaddress addr, + Dbg_ProcPos *pos); +Dbg_Error Dbg_AddressToLLPos( + Dbg_MCState *state, ARMaddress addr, + Dbg_LLPos *pos, Dbg_LLSymType *res_type, int system_names); + +Dbg_Error Dbg_ProcPosToAddress( + Dbg_MCState *state, const Dbg_ProcPos *pos, + ARMaddress *res); +Dbg_Error Dbg_LLPosToAddress( + Dbg_MCState *state, const Dbg_LLPos *pos, + ARMaddress *res); + +typedef struct { + ARMaddress start, end; +} Dbg_AddressRange; + +Dbg_Error Dbg_FileRangeToAddressRange( + Dbg_SymTable *st, const char *f, int32 first, int32 last, Dbg_AddressRange *res); + +typedef struct Dbg_Environment Dbg_Environment; +/* A Dbg_Environment describes the context required to make sense of a variable + name and access its value. Its format is not revealed. Dbg_Environment + values are allocated by Dbg_NewEnvironment() and discarded by + Dbg_DeleteEnvironment(). + */ + +Dbg_Environment *Dbg_NewEnvironment(Dbg_MCState *state); +void Dbg_DeleteEnvironment(Dbg_MCState *state, Dbg_Environment *env); + +Dbg_Error Dbg_StringToEnv( + Dbg_MCState *state, char *str, Dbg_Environment *resenv, + int forcontext, Dbg_Environment const *curenv); + +Dbg_Error Dbg_ProcPosToEnvironment( + Dbg_MCState *state, const Dbg_ProcPos *pos, int activation, + const Dbg_Environment *current, Dbg_Environment *res); + +/* Conversion from a position representation to an Dbg_Environment (as required + to access variable values). Only a Dbg_ProcPos argument here; other + representations need to be converted first. + + Returns describing the th instance of the function + described by , up from the stack base if is negative, + else down from . + If this function returns Dbg_Err_ActivationNotPresent, the result + Dbg_Environment is still valid for accessing non-auto variables. + */ + +typedef struct Dbg_DeclSpec Dbg_DeclSpec; + +Dbg_Error Dbg_EnvToProcItem( + Dbg_MCState *state, Dbg_Environment const *env, Dbg_DeclSpec *proc); + +Dbg_Error Dbg_ContainingEnvironment( + Dbg_MCState *state, const Dbg_Environment *context, Dbg_Environment *res); +/* Set to describe the containing function, file if is within + a top-level function (or error if already describes a file). + */ + +/*--------------------------------------------------------------------------*/ + +/* ASD debug table pointers are not by themselves sufficient description, + since there's an implied section context. Hence the DeclSpec and TypeSpec + structures. + */ + +struct Dbg_DeclSpec { + ItemSection *section; + union { + ItemVar *var; + ItemType *type; + ItemProc *proc; + } item; +}; + +typedef struct Dbg_TypeSpec { + ItemSection *section; + asd_Type type; +} Dbg_TypeSpec; + +typedef Dbg_Error Dbg_FileProc(Dbg_MCState *state, const char *name, const Dbg_DeclSpec *procdef, void *arg); + +Dbg_Error Dbg_EnumerateFiles(Dbg_MCState *state, Dbg_SymTable *st, Dbg_FileProc *p, void *arg); +/* The top level for a high level enumerate. Lower levels are performed by + EnumerateDeclarations (below). + */ + +typedef struct Dbg_DComplex { DbleBin r, i; } Dbg_DComplex; + +typedef union Dbg_ConstantVal { + int32 l; + unsigned32 u; + DbleBin d; + Dbg_DComplex fc; + ARMaddress a; + char *s; +} Dbg_ConstantVal; + +typedef struct Dbg_Constant { + asd_Type typecode; /* not a Dbg_TypeSpec since only primitive types are + possible here */ + Dbg_ConstantVal val; +} Dbg_Constant; + +typedef enum Dbg_ValueSort { + vs_register, + vs_store, + vs_constant, + vs_local, + vs_filtered, + vs_none, + vs_error +} Dbg_ValueSort; + +/* vs_local allows the use of symbol table entries to describe entities within + the debugger's own address space, accessed in the same way as target + variables. + vs_filtered describes entities which may be read or written only via an + access function (eg r15) + */ + +#define fpr_base 16 +/* There's only one register ValueSort (reflecting asd table StgClass); + fp register n is encoded as register n+fpr_base. + */ + +typedef struct Dbg_Value Dbg_Value; + +typedef Dbg_Error Dbg_AccessFn(Dbg_MCState *state, int write, Dbg_Value *self, Dbg_Constant *c); +/* == 0: read a vs_filtered value, updating the value self. + == 1: update a vs_filtered value, with the value described by c. + allows use of the same Dbg_AccessFn for several different entities + (using different val.f.id fields). + */ + +typedef Dbg_Error Dbg_FormatFn(int decode, char *b, ARMword *valp, void *formatarg); + +typedef struct { Dbg_AccessFn *f; int id; } Dbg_AccessFnRec; + +typedef Dbg_Error Dbg_ValueChangedFn(Dbg_MCState *state, Dbg_Value const *val, void *arg); + +typedef struct { Dbg_ValueChangedFn *f; void *arg; } Dbg_ValueChangedFnRec; + +struct Dbg_Value { + Dbg_TypeSpec type; + Dbg_ValueSort sort; + Dbg_FormatFn *formatp; + void *formatarg; + Dbg_ValueChangedFnRec const *valuechanged; + int f77csize; + union { + struct { int no; ARMaddress frame; } r; + ARMaddress ptr; + Dbg_ConstantVal c; + void *localp; + Dbg_AccessFnRec f; + Dbg_Error err; + } val; +}; + +Dbg_Error Dbg_AddLLSymbol(Dbg_SymTable *st, char const *name, Dbg_LLSymType type, ARMword val); + +Dbg_Error Dbg_AddSymbol(Dbg_SymTable *st, char const *name, Dbg_Value const *val); + +Dbg_Error Dbg_AttachValueChangedRec( + Dbg_MCState *state, char const *name, Dbg_Environment const *context, + Dbg_ValueChangedFnRec const *vc); + +typedef struct Dbg_DeclSpecF { + Dbg_DeclSpec decl; + Dbg_FormatFn *formatp; + void *formatarg; +} Dbg_DeclSpecF; + +typedef Dbg_Error Dbg_DeclProc(Dbg_MCState *state, const Dbg_Environment *context, + const Dbg_DeclSpecF *var, int decltype, int masked, + void *arg); + +Dbg_Error Dbg_EnumerateDeclarations(Dbg_MCState *state, const Dbg_Environment *context, + Dbg_DeclProc *p, void *arg); +/* call p once for every declaration local to the function described by + (or file if describes a place outside a function). + p's argument is true if the variable is not visible, thanks to + a declaration in an inner scope. decltype has one of the values + ITEMVAR, ITEMTYPE or ITEMFUNCTION. + */ + +Dbg_Error Dbg_ValueOfVar(Dbg_MCState *state, const Dbg_Environment *context, + const Dbg_DeclSpec *var, Dbg_Value *val); +/* Different from Dbg_EvalExpr() in that the thing being evaluated is described + by a Dbg_DeclSpec (which must be for a variable), rather than a string + needing to be decoded and associated with a symbol-table item. Intended to + be called from a Dbg_DeclProc called from Dbg_EnumerateDeclarations. + */ + +Dbg_Error Dbg_EvalExpr(Dbg_MCState *state, Dbg_Environment const *context, + char const *expr, int flags, Dbg_Value *val); + +Dbg_Error Dbg_EvalExpr_ep(Dbg_MCState *state, Dbg_Environment const *context, + char const *expr, char **exprend, int flags, Dbg_Value *val); + +/* Both Dbg_ValueOfVar and Dbg_EvalExpr mostly deliver a value still containing + an indirection (since it may be wanted as the lhs of an assignment) + */ + +void Dbg_RealLocation(Dbg_MCState *state, Dbg_Value *val); +/* If val describes a register, this may really be a register, or a place on + the stack where the register's value is saved. In the latter case, val + is altered to describe the save place. (In all others, it remains + unchanged). + */ + +Dbg_Error Dbg_DereferenceValue(Dbg_MCState *state, const Dbg_Value *value, Dbg_Constant *c); +/* This fails if describes a structure or array, returning + Dbg_Err_TypeNotSimple + */ + +typedef struct Dbg_Expr Dbg_Expr; +/* The result of parsing an expression in an environment: its structure is not + revealed. (Clients may wish to parse just once an expression which may be + evaluated often). In support of which, the following two functions partition + the work of Dbg_EvalExpr(). + */ + +#define Dbg_exfl_heap 1 /* allocate Expr on the heap (FreeExpr must then be + called to discard it). Otherwise, it goes in a + place overwritten by the next call to ParseExpr + or EvalExpr + */ +#define Dbg_exfl_needassign 2 +#define Dbg_exfl_lowlevel 4 + +int Dbg_SetInputRadix(Dbg_MCState *state, int radix); +char *Dbg_SetDefaultIntFormat(Dbg_MCState *state, char *format); + +Dbg_Error Dbg_ParseExpr( + Dbg_MCState *state, Dbg_Environment const *env, char *string, + char **end, Dbg_Expr **res, int flags); +/* Just parse the argument string, returning a pointer to a parsed expression + and a pointer to the first non-white space character in the input string + which is not part of the parsed expression. (If macro expansion has taken + place, the returned pointer will not be into the argument string at all, + rather into the expanded version of it). + */ + +Dbg_Error Dbg_ParseExprCheckEnd( + Dbg_MCState *state, Dbg_Environment const *env, char *string, + Dbg_Expr **res, int flags); +/* As Dbg_ParseExpr, but the parsed expression is required completely to fill + the argument string (apart possibly for trailing whitespace), and an error + is returned if it does not. + */ + +Dbg_Error Dbg_ParsedExprToValue( + Dbg_MCState *state, const Dbg_Environment *env, Dbg_Expr *expr, Dbg_Value *v); + +Dbg_Error Dbg_ReadDecl( + Dbg_MCState *state, Dbg_Environment const *env, char *string, + Dbg_TypeSpec *p, char **varp, int flags); +/* Read a variable declaration, returing a description of the type of the + variable to p, and a pointer to its name to varp. + */ + +void Dbg_FreeExpr(Dbg_Expr *expr); + +Dbg_Error Dbg_ExprToVar(const Dbg_Expr *expr, Dbg_DeclSpec *var, Dbg_Environment *env); + +Dbg_Error Dbg_Assign(Dbg_MCState *state, const Dbg_Value *lv, const Dbg_Value *rv); + +typedef enum Dbg_TypeSort { + ts_simple, + ts_union, + ts_struct, + ts_array +} Dbg_TypeSort; + +Dbg_TypeSort Dbg_TypeSortOfValue(Dbg_MCState *state, const Dbg_Value *val, int *fieldcount); + +Dbg_Error Dbg_TypeToChars(const Dbg_TypeSpec *var, Dbg_BufDesc *buf); + +Dbg_Error Dbg_TypeSize(Dbg_MCState *state, const Dbg_TypeSpec *type, int32 *res); + +typedef int Dbg_ValToChars_cb(Dbg_MCState *state, Dbg_Value *subval, const char *fieldname, + Dbg_BufDesc *buf, void *arg); + +Dbg_Error Dbg_ValToChars(Dbg_MCState *state, Dbg_Value *val, int base, + Dbg_ValToChars_cb *cb, void *arg, + const char *form, Dbg_BufDesc *buf); +/* + is used for (any size) integer values. + If is of an array or structure type, is called for each element, + with as its last parameter, and describing the space remaining + in . If returns 0, conversion ceases. + */ + +Dbg_Error Dbg_NthElement( + Dbg_MCState *state, + const Dbg_Value *val, unsigned32 n, char **fieldname, Dbg_Value *subval); + +typedef Dbg_Error Dbg_HistoryProc(void *, int, Dbg_Value *); + +Dbg_Error Dbg_RegisterHistoryProc(Dbg_MCState *state, Dbg_HistoryProc *p, void *arg); + +/*--------------------------------------------------------------------------*/ + +/* Control of target program execution. + Currently, only synchronous operation is provided. + Execution could possibly be asynchronous where the target is a seperate + processor, but is necessarily synchronous if the target is Armulator. + Unfortunately, this may require modification to the RDI implementation + if multitasking is required but the the host system provides it only + cooperatively, or if there is no system-provided way to generate SIGINT. + */ + +Dbg_Error Dbg_SetCommandline(Dbg_MCState *state, const char *args); +/* Set the argument string to the concatenation of the name of the most + recently loaded image and args. + */ + +typedef enum Dbg_ProgramState { + ps_notstarted, + /* Normal ways of stopping */ + ps_atbreak, ps_atwatch, ps_stepdone, + ps_interrupted, + ps_stopped, + /* abnormal (but unsurprising) ways of stopping */ + ps_lostwatch, + ps_branchthrough0, ps_undef, ps_caughtswi, ps_prefetch, + ps_abort, ps_addrexcept, ps_caughtirq, ps_caughtfiq, + ps_error, + /* only as a return value from Call() */ + ps_callfailed, ps_callreturned, + /* internal inconsistencies */ + ps_unknownbreak, + ps_unknown +} Dbg_ProgramState; + +Dbg_ProgramState Dbg_Call(Dbg_MCState *state, ARMaddress target, + int argcount, const ARMword *args); +Dbg_ProgramState Dbg_Call16(Dbg_MCState *state, ARMaddress target, + int argcount, const ARMword *args); +Dbg_ProgramState Dbg_CallNaturalSize(Dbg_MCState *state, ARMaddress target, + int argcount, const ARMword *args); +/* Call a function in the debuggee, address with integer + arguments (values in the array ). + Any Dbg_ProgramState value may be returned, not just ps_callreturned (the + called function may abort, hit breakpoints, or whatever). + */ + +int Dbg_IsCallLink(Dbg_MCState *state, ARMaddress pc); + +typedef struct { + ARMword intres; + Dbg_FPRegVal fpres; +} Dbg_CallResults; + +Dbg_CallResults *Dbg_GetCallResults(Dbg_MCState *state); + +#define Dbg_S_STATEMENTS 0 +#define Dbg_S_INSTRUCTIONS 1 +#define Dbg_S_STEPINTOPROCS 2 + +Dbg_Error Dbg_Step(Dbg_MCState *state, int32 stepcount, int stepby, Dbg_ProgramState *status); +/* is a combination of the Dbg_S_... values above */ + +Dbg_Error Dbg_StepOut(Dbg_MCState *state, Dbg_ProgramState *status); + +int Dbg_CanGo(Dbg_MCState *state); + +Dbg_Error Dbg_Go(Dbg_MCState *state, Dbg_ProgramState *status); + +Dbg_Error Dbg_Stop(Dbg_MCState *state); +/* Asynchronous Stop request, for call from SIGINT handler. On return to the + caller, the call of Dbg_Go, Dbg_Step or Dbg_Call which started execution + should return ps_interrupted. + */ + +Dbg_Error Dbg_SetReturn(Dbg_MCState *state, + const Dbg_Environment *context, const Dbg_Value *value); +/* Prepare continuation by returning from the function activation + described by . (Dbg_Go() or Dbg_Step() actually perform the + continuation). + */ + +Dbg_Error Dbg_SetExecution(Dbg_MCState *state, Dbg_Environment *context); +/* Set the pc in a high-level fashion */ + +Dbg_Error Dbg_ProgramStateToChars(Dbg_MCState *state, Dbg_ProgramState event, Dbg_BufDesc *buf); +/* This is guaranteed to give a completely accurate description of if + this was the value returned by the most recent call of Dbg_Go, Dbg_Step, + or Dbg_Call. + */ + +/*--------------------------------------------------------------------------*/ + +Dbg_Error Dbg_CurrentEnvironment(Dbg_MCState *state, Dbg_Environment *context); + +Dbg_Error Dbg_PrevFrame(Dbg_MCState *state, Dbg_Environment *context); +/* towards the base of the stack */ + +Dbg_Error Dbg_NextFrame(Dbg_MCState *state, Dbg_Environment *context); +/* away from the base of the stack */ + +typedef struct Dbg_AnyPos { + enum { pos_source, pos_ll, pos_none } postype; + ARMaddress pc; + union { + Dbg_ProcPos source; + Dbg_LLPos ll; + ARMaddress none; + } pos; +} Dbg_AnyPos; + +Dbg_Error Dbg_EnvironmentToPos(Dbg_MCState *state, const Dbg_Environment *context, Dbg_AnyPos *pos); +/* is set to a Dbg_ProcPos if these is one corresponding to + else a Dbg_LLPos if there is one. + */ + +/*--------------------------------------------------------------------------*/ + +/* Source file management. + Pretty vestigial. Handles source path (per loaded image), + and translates from line-number (as given in debugger tables) to character + position (as required to access files) + */ + +Dbg_Error Dbg_ClearPaths(Dbg_SymTable *st); +Dbg_Error Dbg_AddPath(Dbg_SymTable *st, const char *path); +Dbg_Error Dbg_DeletePath(Dbg_SymTable *st, const char *path); + +Dbg_Error Dbg_GetFileLine(Dbg_MCState *state, const Dbg_FilePos *pos, Dbg_BufDesc *buf); + +typedef struct Dbg_FileRec Dbg_FileRec; +typedef struct { + unsigned32 linecount; + Dbg_FileRec *handle; + Dbg_BufDesc *fullname; +} Dbg_FileDetails; + +Dbg_Error Dbg_GetFileDetails(Dbg_MCState *state, const Dbg_File *fname, Dbg_FileDetails *res); +Dbg_Error Dbg_FinishedWithFile(Dbg_MCState *state, Dbg_FileRec *handle); +Dbg_Error Dbg_FileLineLength(Dbg_MCState *state, Dbg_FileRec *handle, int32 lineno, int32 *len); +Dbg_Error Dbg_GetFileLine_fr(Dbg_MCState *state, Dbg_FileRec *handle, int32 lineno, Dbg_BufDesc *buf); + +/*--------------------------------------------------------------------------*/ + +/* disassembly */ + +/* + ? More exact control is wanted here, but that requires a more complicated + ? disass callback interface. + */ + +typedef const char *Dbg_SWI_Decode(Dbg_MCState *state, ARMword swino); + +Dbg_Error Dbg_InstructionAt(Dbg_MCState *state, ARMaddress addr, + int isize, ARMhword *inst, Dbg_SymTable *st, + Dbg_SWI_Decode *swi_name, Dbg_BufDesc *buf, int *length); +/* describes the form of disassembly wanted: 2 for 16-bit, 4 for 32-bit, + * 0 for 16- or 32-bit depending whether addr addresses 16- or 32-bit code. + * is a pointer to a pair of halfwords *in target byte order* + * Possibly only the first halfword will be consumed: the number of bytes used + * is returned via . + */ + +/*--------------------------------------------------------------------------*/ + +int Dbg_RDIOpen(Dbg_MCState *state, unsigned type); +int Dbg_RDIInfo(Dbg_MCState *state, unsigned type, ARMword *arg1, ARMword *arg2); + +/*--------------------------------------------------------------------------*/ + +typedef enum { + Dbg_Point_Toolbox, + Dbg_Point_RDI_Unknown, + Dbg_Point_RDI_SW, + Dbg_Point_RDI_HW +} Dbg_PointType; + +/* breakpoint management + Associated with a breakpoint there may be any of + a count + an expression + a function + the breakpoint is activated if + the expression evaluates to a non-zero value (or fails to evaluate). + && decrementing the count reaches zero (the count is then reset to its + initial value). + && the function, called with the breakpoint address as argument, returns + a non-zero value. +? (The order here may be open to debate. Note that the first two are in + the opposite order in armsd, but I think this order more rational) + */ + +typedef enum Dbg_BreakPosType { + bt_procpos, + bt_procexit, + bt_address +} Dbg_BreakPosType; + +typedef struct Dbg_BreakPos { + Dbg_BreakPosType sort; + union { + Dbg_ProcPos procpos; + Dbg_ProcDesc procexit; + ARMaddress address; + } loc; +} Dbg_BreakPos; + +typedef int Dbg_BPProc(Dbg_MCState *state, void *BPArg, Dbg_BreakPos *where); + +typedef struct Dbg_BreakStatus { + int index; + int initcount, countnow; + Dbg_BreakPos where; + char *expr; + Dbg_BPProc *p; void *p_arg; + int incomplete; + Dbg_PointType type; + ARMword hwresource; +} Dbg_BreakStatus; + +Dbg_Error Dbg_SetBreakPoint(Dbg_MCState *state, Dbg_BreakPos *where, + int count, + const char *expr, + Dbg_BPProc *p, void *arg); +Dbg_Error Dbg_SetBreakPoint16(Dbg_MCState *state, Dbg_BreakPos *where, + int count, + const char *expr, + Dbg_BPProc *p, void *arg); +Dbg_Error Dbg_SetBreakPointNaturalSize(Dbg_MCState *state, Dbg_BreakPos *where, + int count, + const char *expr, + Dbg_BPProc *p, void *arg); +/* Setting a breakpoint at the same address as a previous breakpoint + completely removes the previous one. + */ + +Dbg_Error Dbg_DeleteBreakPoint(Dbg_MCState *state, Dbg_BreakPos *where); + +Dbg_Error Dbg_SuspendBreakPoint(Dbg_MCState *state, Dbg_BreakPos *where); +/* Temporarily remove the break point (until Reinstated) but leave intact + its associated expr, the value its count has reached, etc. +? The debugger toolbox itself wants this, but I'm not sure what use a client + could have for it. Ditto Reinstate... + */ + +Dbg_Error Dbg_ReinstateBreakPoint(Dbg_MCState *state, Dbg_BreakPos *where); +/* Undo the effect of Dbg_SuspendBreakPoint + */ + +Dbg_Error Dbg_DeleteAllBreakPoints(Dbg_MCState *state); + +Dbg_Error Dbg_SuspendAllBreakPoints(Dbg_MCState *state); + +Dbg_Error Dbg_ReinstateAllBreakPoints(Dbg_MCState *state); + +typedef Dbg_Error Dbg_BPEnumProc(Dbg_MCState *state, Dbg_BreakStatus *status, void *arg); + +Dbg_Error Dbg_EnumerateBreakPoints(Dbg_MCState *state, Dbg_BPEnumProc *p, void *arg); + +Dbg_Error Dbg_BreakPointStatus(Dbg_MCState *state, + const Dbg_BreakPos *where, Dbg_BreakStatus *status); + +/*--------------------------------------------------------------------------*/ + +typedef struct { + Dbg_Value val; + char *name; +} Dbg_WatchPos; + +typedef int Dbg_WPProc(Dbg_MCState *state, void *WPArg, Dbg_WatchPos *where); + +typedef struct Dbg_WPStatus { + int index; + int initcount, countnow; + Dbg_WatchPos what, target; + char *expr; + Dbg_WPProc *p; void *p_arg; + Dbg_PointType type; + ARMword hwresource; + int skip; +} Dbg_WPStatus; + +Dbg_Error Dbg_SetWatchPoint( + Dbg_MCState *state, Dbg_Environment *context, char const *watchee, + char const *target, + int count, + char const *expr, + Dbg_WPProc *p, void *arg); + +/* Cause a watchpoint event if the value of changes to the value of + (or changes at all if is NULL). should + evaluate either to an L-value (when the size of the object being watched is + determined by its type) or to an integer constant (when the word with this + address is watched). + */ + +Dbg_Error Dbg_DeleteWatchPoint(Dbg_MCState *state, Dbg_Environment *context, char const *watchee); + + +Dbg_Error Dbg_SetWatchPoint_V( + Dbg_MCState *state, + char const *name, Dbg_Value const *val, char const *tname, Dbg_Value const *tval, + int count, + char const *expr, + Dbg_WPProc *p, void *arg); + +Dbg_Error Dbg_DeleteWatchPoint_V(Dbg_MCState *state, Dbg_Value const *val); + + +Dbg_Error Dbg_DeleteAllWatchPoints(Dbg_MCState *state); + +typedef Dbg_Error Dbg_WPEnumProc(Dbg_MCState *state, Dbg_WPStatus const *watchee, void *arg); + +Dbg_Error Dbg_EnumerateWatchPoints(Dbg_MCState *state, Dbg_WPEnumProc *p, void *arg); + +Dbg_Error Dbg_WatchPointStatus(Dbg_MCState *state, + Dbg_WatchPos const *where, Dbg_WPStatus *status); + +typedef void Dbg_WPRemovedProc(void *arg, Dbg_WPStatus const *wp); +Dbg_Error Dbg_RegisterWPRemovalProc(Dbg_MCState *state, Dbg_WPRemovedProc *p, void *arg); +/* When a watchpoint goes out of scope it is removed by the toolbox, and the + function registered here gets called back to adjust its view + */ + +/*--------------------------------------------------------------------------*/ + +Dbg_Error Dbg_ProfileLoad(Dbg_MCState *state); + +Dbg_Error Dbg_ProfileStart(Dbg_MCState *state, ARMword interval); +Dbg_Error Dbg_ProfileStop(Dbg_MCState *state); + +Dbg_Error Dbg_ProfileClear(Dbg_MCState *state); + +Dbg_Error Dbg_WriteProfile(Dbg_MCState *state, char const *filename, + char const *toolid, char const *arg); + +/*--------------------------------------------------------------------------*/ + +Dbg_Error Dbg_ConnectChannel_ToHost(Dbg_MCState *state, RDICCProc_ToHost *p, void *arg); +Dbg_Error Dbg_ConnectChannel_FromHost(Dbg_MCState *state, RDICCProc_FromHost *p, void *arg); + +/*--------------------------------------------------------------------------*/ + +/* Configuration data management */ + +Dbg_Error Dbg_LoadConfigData(Dbg_MCState *state, char const *filename); + +Dbg_Error Dbg_SelectConfig( + Dbg_MCState *state, + RDI_ConfigAspect aspect, char const *name, RDI_ConfigMatchType matchtype, + unsigned versionreq, unsigned *versionp); + +Dbg_Error Dbg_ParseConfigVersion( + char const *s, RDI_ConfigMatchType *matchp, unsigned *versionp); + +typedef Dbg_Error Dbg_ConfigEnumProc(Dbg_MCState *state, RDI_ConfigDesc const *desc, void *arg); + +Dbg_Error Dbg_EnumerateConfigs(Dbg_MCState *state, Dbg_ConfigEnumProc *p, void *arg); + +#ifdef __cplusplus +} +#endif + +#endif + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_CONF.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_CONF.H new file mode 100644 index 0000000..912ce94 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_CONF.H @@ -0,0 +1,47 @@ +/* + * ARM symbolic debugger toolbox: dbg_conf.h + * Copyright (C) 1992 Advanced Risc Machines Ltd. All rights reserved. + */ + +/* + * RCS $Revision: 1.11 $ + * Checkin $Date: 1995/04/06 14:09:05 $ + * Revising $Author: mwilliam $ + */ + +#ifndef Dbg_Conf__h + +#define Dbg_Conf__h + +typedef struct Dbg_ConfigBlock { + int bytesex; + int fpe; /* Target should initialise FPE */ + long memorysize; + unsigned long cpu_speed;/* Cpu speed (HZ) */ + int serialport; /*) remote connection parameters */ + int seriallinespeed; /*) (serial connection) */ + int parallelport; /*) ditto */ + int parallellinespeed; /*) (parallel connection) */ + int processor; /* processor the armulator is to emulate (eg ARM60) */ + int rditype; /* armulator / remote processor */ + int drivertype; /* parallel / serial / etc */ + char const *configtoload; + char const *memconfigtoload; + int flags; +} Dbg_ConfigBlock; + +#define Dbg_ConfigFlag_Reset 1 +#define Dbg_ConfigFlag_LLSymsNeedPrefix 2 + +typedef struct Dbg_HostosInterface Dbg_HostosInterface; +/* This structure allows access by the (host-independent) C-library support + module of armulator or pisd (armos.c) to host-dependent functions for + which there is no host-independent interface. Its contents are unknown + to the debugger toolbox. + The assumption is that, in a windowed system, fputc(stderr) for example + may not achieve the desired effect of the character appearing in some + window. + */ + +#endif + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_CP.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_CP.H new file mode 100644 index 0000000..777a269 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_CP.H @@ -0,0 +1,57 @@ +/* + * ARM symbolic debugger toolbox: dbg_cp.h + * Copyright (C) 1992 Advanced Risc Machines Ltd. All rights reserved. + */ + +/* + * RCS $Revision: 1.4 $ + * Checkin $Date: 1994/09/01 10:42:16 $ + * Revising $Author: hmeekings $ + */ + +#ifndef Dbg_CP__h + +#define Dbg_CP__h + +#define Dbg_Access_Readable 1 +#define Dbg_Access_Writable 2 +#define Dbg_Access_CPDT 4 /* else CPRT */ + +typedef struct { + unsigned short rmin, rmax; + /* a single description can be used for a range of registers with + the same properties *accessed via CPDT instructions* + */ + unsigned char nbytes; /* size of register */ + unsigned char access; /* see above (Access_xxx) */ + union { + struct { /* CPDT instructions do not allow the coprocessor much freedom: + only bit 22 ('N') and 12-15 ('CRd') are free for the + coprocessor to use as it sees fit. + */ + unsigned char nbit; + unsigned char rdbits; + } cpdt; + struct { /* CPRT instructions have much more latitude. The bits fixed + by the ARM are 24..31 (condition mask & opcode) + 20 (direction) + 8..15 (cpnum, arm register) + 4 (CPRT not CPDO) + leaving 14 bits free to the coprocessor (fortunately + falling within two bytes). + */ + unsigned char read_b0, read_b1, + write_b0, write_b1; + } cprt; + } accessinst; +} Dbg_CoProRegDesc; + +struct Dbg_CoProDesc { + int entries; + Dbg_CoProRegDesc regdesc[1/* really nentries */]; +}; + +#define Dbg_CoProDesc_Size(n) (sizeof(struct Dbg_CoProDesc) + ((n)-1)*sizeof(Dbg_CoProRegDesc)) + +#endif + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_HIF.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_HIF.H new file mode 100644 index 0000000..fef46d1 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_HIF.H @@ -0,0 +1,46 @@ +/* + * ARM debugger toolbox : dbg_hif.c + * Copyright (C) 1992 Advanced Risc Machines Ltd. All rights reserved. + * Description of the Dbg_HostosInterface structure. This is *NOT* + * part of the debugger toolbox, but it is required by 2 back ends + * (armul & pisd) and two front ends (armsd & wdbg), so putting it + * in the toolbox is the only way of avoiding multiple copies. + */ + +/* + * RCS $Revision: 1.3 $ + * Checkin $Date: 1993/10/22 17:41:07 $ + * Revising $Author: hmeekings $ + */ + +#ifdef __STDC__ +# include +#else +# include +#endif + +typedef void Hif_DbgPrint(void *arg, const char *format, va_list ap); +typedef void Hif_DbgPause(void *arg); + +typedef void Hif_WriteC(void *arg, int c); +typedef int Hif_ReadC(void *arg); +typedef int Hif_Write(void *arg, char const *buffer, int len); +typedef char *Hif_GetS(void *arg, char *buffer, int len); + +typedef void Hif_RDIResetProc(void *arg); + +struct Dbg_HostosInterface { + Hif_DbgPrint *dbgprint; + Hif_DbgPause *dbgpause; + void *dbgarg; + + Hif_WriteC *writec; + Hif_ReadC *readc; + Hif_Write *write; + Hif_GetS *gets; + void *hostosarg; + + Hif_RDIResetProc *reset; + void *resetarg; +}; + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_RDI.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_RDI.H new file mode 100644 index 0000000..1611b0c --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_RDI.H @@ -0,0 +1,614 @@ +/* + * ARM debugger toolbox : dbg_rdi.h + * Copyright (C) 1992 Advanced Risc Machines Ltd. All rights reserved. + */ + +/* + * RCS $Revision: 1.36.2.3 $ + * Checkin $Date: 1995/05/18 13:35:04 $ + * Revising $Author: plg $ + */ + +#ifndef dbg_rdi__h +#define dbg_rdi__h + +#include "dbg_stat.h" + +/***************************************************************************\ +* Error Codes * +\***************************************************************************/ + +#define RDIError_NoError 0 + +#define RDIError_Reset 1 +#define RDIError_UndefinedInstruction 2 +#define RDIError_SoftwareInterrupt 3 +#define RDIError_PrefetchAbort 4 +#define RDIError_DataAbort 5 +#define RDIError_AddressException 6 +#define RDIError_IRQ 7 +#define RDIError_FIQ 8 +#define RDIError_Error 9 +#define RDIError_BranchThrough0 10 + +#define RDIError_NotInitialised 128 +#define RDIError_UnableToInitialise 129 +#define RDIError_WrongByteSex 130 +#define RDIError_UnableToTerminate 131 +#define RDIError_BadInstruction 132 +#define RDIError_IllegalInstruction 133 +#define RDIError_BadCPUStateSetting 134 +#define RDIError_UnknownCoPro 135 +#define RDIError_UnknownCoProState 136 +#define RDIError_BadCoProState 137 +#define RDIError_BadPointType 138 +#define RDIError_UnimplementedType 139 +#define RDIError_BadPointSize 140 +#define RDIError_UnimplementedSize 141 +#define RDIError_NoMorePoints 142 +#define RDIError_BreakpointReached 143 +#define RDIError_WatchpointAccessed 144 +#define RDIError_NoSuchPoint 145 +#define RDIError_ProgramFinishedInStep 146 +#define RDIError_UserInterrupt 147 +#define RDIError_CantSetPoint 148 +#define RDIError_IncompatibleRDILevels 149 + +#define RDIError_CantLoadConfig 150 +#define RDIError_BadConfigData 151 +#define RDIError_NoSuchConfig 152 +#define RDIError_BufferFull 153 +#define RDIError_OutOfStore 154 +#define RDIError_NotInDownload 155 +#define RDIError_PointInUse 156 +#define RDIError_BadImageFormat 157 +#define RDIError_TargetRunning 158 +#define RDIError_DeviceWouldNotOpen 159 +#define RDIError_NoSuchHandle 160 +#define RDIError_ConflictingPoint 161 + +#define RDIError_LittleEndian 240 +#define RDIError_BigEndian 241 +#define RDIError_SoftInitialiseError 242 + +#define RDIError_InsufficientPrivilege 253 +#define RDIError_UnimplementedMessage 254 +#define RDIError_UndefinedMessage 255 + + +/***************************************************************************\ +* RDP Message Numbers * +\***************************************************************************/ + +/********* host -> agent *********/ + +#define RDP_Start (unsigned char)0x0 +/* byte type, word memorysize {, byte speed (if (type & 2)) } */ +/* returns byte status */ + +#define RDP_End (unsigned char)0x1 +/* no argument */ +/* returns byte status */ + +#define RDP_Read (unsigned char)0x2 +/* word address, word nbytes */ +/* returns bytes data, byte status {, word count } */ +/* The count value is returned only if status != 0, and is the number */ +/* of bytes successfully read */ + +#define RDP_Write (unsigned char)0x3 +/* word address, word nbytes, bytes data */ +/* returns byte status {, word count } */ +/* The count value is returned only if status != 0, and is the number */ +/* of bytes successfully written */ + +#define RDP_CPUread (unsigned char)0x4 +/* byte mode, word mask */ +/* returns words data, byte status */ + +#define RDP_CPUwrite (unsigned char)0x5 +/* byte mode, word mask, words data */ +/* returns byte status */ + +#define RDP_CPread (unsigned char)0x6 +/* byte cpnum, word mask */ +/* returns words data, byte status */ + +#define RDP_CPwrite (unsigned char)0x7 +/* byte cpnum, word mask, words data */ +/* returns byte status */ + +#define RDP_SetBreak (unsigned char)0xa +/* word address, byte type {, word bound } */ +/* if !(type & RDIPoint_Inquiry) */ +/* returns {word pointhandle, } byte status */ +/* if (type & RDIPoint_Inquiry) */ +/* returns word address {, word bound }, byte status */ +/* pointhandle is present if type & RDIPoint_Handle */ +/* bound arguments and replies are present if */ +/* (type & 7) == RDIPoint_IN, RDIPoint_OUT or RDIPoint_MASK */ + +#define RDP_ClearBreak (unsigned char)0xb +/* word pointhandle */ +/* returns byte status */ + +#define RDP_SetWatch (unsigned char)0xc +/* word address, byte type, byte datatype {, word bound } */ +/* if !(type & RDIPoint_Inquiry) */ +/* returns {word pointhandle, } byte status */ +/* if (type & RDIPoint_Inquiry) */ +/* returns word address {, word bound }, byte status */ +/* pointhandle is present if type & RDIPoint_Handle */ +/* bound arguments and replies are present if */ +/* (type & 7) == RDIPoint_IN or RDIPoint_OUT */ + +#define RDP_ClearWatch (unsigned char)0xd +/* word pointhandle */ +/* returns byte status */ + +#define RDP_Execute (unsigned char)0x10 +/* byte type */ +/* returns {word pointhandle, } byte status */ +/* pointhandle is returned if (type & RDIPoint_Handle); type also has: */ +# define RDIExecute_Async 1 + +#define RDP_Step (unsigned char)0x11 +/* byte type, word stepcount */ +/* returns {word pointhandle, } byte status */ +/* (type as for RDP_Execute) */ + +#define RDP_Info (unsigned char)0x12 +/* argument and return type different for each operation: see below */ + +#define RDP_OSOpReply (unsigned char)0x13 + +#define RDP_AddConfig (unsigned char)0x14 +/* word nbytes */ +/* returns byte status */ + +#define RDP_LoadConfigData (unsigned char)0x15 +/* word nbytes, nbytes * bytes data */ +/* returns byte status */ + +#define RDP_SelectConfig (unsigned char)0x16 +/* byte aspect, byte namelen, byte matchtype, word version, */ +/* namelen * bytes name */ +/* returns word version selected, byte status */ + +#define RDP_LoadAgent (unsigned char)0x17 +/* word loadaddress, word size */ +/* followed by a number of messages: */ +/* byte = RDP_LoadConfigData, word size, size * bytes data */ +/* returns byte status */ + +#define RDP_Interrupt (unsigned char)0x18 + +#define RDP_CCToHostReply (unsigned char)0x19 +#define RDP_CCFromHostReply (unsigned char)0x1a + +/********* agent -> host *********/ + +#define RDP_Stopped (unsigned char)0x20 +/* reply to step or execute with RDIExecute_Async */ + +#define RDP_OSOp (unsigned char)0x21 +#define RDP_CCToHost (unsigned char)0x22 +#define RDP_CCFromHost (unsigned char)0x23 + +#define RDP_Fatal (unsigned char)0x5e +#define RDP_Return (unsigned char)0x5f +#define RDP_Reset (unsigned char)0x7f + +/***************************************************************************\ +* Other RDI values * +\***************************************************************************/ + +#define RDISex_Little 0 /* the byte sex of the debuggee */ +#define RDISex_Big 1 +#define RDISex_DontCare 2 + +#define RDIPoint_EQ 0 /* the different types of break/watchpoints */ +#define RDIPoint_GT 1 +#define RDIPoint_GE 2 +#define RDIPoint_LT 3 +#define RDIPoint_LE 4 +#define RDIPoint_IN 5 +#define RDIPoint_OUT 6 +#define RDIPoint_MASK 7 + +#define RDIPoint_16Bit 16 /* 16-bit breakpoint */ +#define RDIPoint_Conditional 32 + +/* ORRed with point type in extended RDP break and watch messages */ +#define RDIPoint_Inquiry 64 +#define RDIPoint_Handle 128 /* messages */ + +#define RDIWatch_ByteRead 1 /* types of data accesses to watch for*/ +#define RDIWatch_HalfRead 2 +#define RDIWatch_WordRead 4 +#define RDIWatch_ByteWrite 8 +#define RDIWatch_HalfWrite 16 +#define RDIWatch_WordWrite 32 + +#define RDIReg_R15 (1L << 15) /* mask values for CPU */ +#define RDIReg_PC (1L << 16) +#define RDIReg_CPSR (1L << 17) +#define RDIReg_SPSR (1L << 18) +#define RDINumCPURegs 19 + +#define RDINumCPRegs 10 /* current maximum */ + +#define RDIMode_Curr 255 + +/* RDI_Info subcodes */ +/* rdp in parameters are all preceded by */ +/* in byte = RDP_Info, word = info subcode */ +/* out parameters are all preceded by */ +/* out byte = RDP_Return */ + +#define RDIInfo_Target 0 +/* rdi: out ARMword *targetflags, out ARMword *processor id */ +/* rdp: in none, out word targetflags, word processorid, byte status */ +/* the following bits are defined in targetflags */ +# define RDITarget_LogSpeed 0x0f +# define RDITarget_HW 0x10 /* else emulator */ +# define RDITarget_AgentMaxLevel 0xe0 +# define RDITarget_AgentLevelShift 5 +# define RDITarget_DebuggerMinLevel 0x700 +# define RDITarget_DebuggerLevelShift 8 +# define RDITarget_CanReloadAgent 0x800 +# define RDITarget_CanInquireLoadSize 0x1000 +# define RDITarget_UnderstandsRDPInterrupt 0x2000 +# define RDITarget_CanProfile 0x4000 +# define RDITarget_Code16 0x8000 +# define RDITarget_HasCommsChannel 0x10000 + +#define RDIInfo_Points 1 +/* rdi: out ARMword *pointcapabilities */ +/* rdp: in none, out word pointcapabilities, byte status */ +/* the following bits are defined in pointcapabilities */ +# define RDIPointCapability_Comparison 1 +# define RDIPointCapability_Range 2 +/* 4 to 128 are RDIWatch_xx{Read,Write} left-shifted by two */ +# define RDIPointCapability_Mask 0x100 +# define RDIPointCapability_ThreadBreak 0x200 +# define RDIPointCapability_ThreadWatch 0x400 +# define RDIPointCapability_CondBreak 0x800 +# define RDIPointCapability_Status 0x1000 /* status enquiries available */ + +#define RDIInfo_Step 2 +/* rdi: out ARMword *stepcapabilities */ +/* rdp: in none, out word stepcapabilities, byte status */ +/* the following bits are defined in stepcapabilities */ +# define RDIStep_Multiple 1 +# define RDIStep_PCChange 2 +# define RDIStep_Single 4 + +#define RDIInfo_MMU 3 +/* rdi: out ARMword *mmuidentity */ +/* rdp: in none, out word mmuidentity, byte status */ + +#define RDIInfo_DownLoad 4 +/* Inquires whether configuration download and selection is available. */ +/* rdp: in none, out byte status */ +/* No argument, no return value. status == ok if available */ + +#define RDIInfo_SemiHosting 5 +/* Inquires whether RDISemiHosting_* RDI_Info calls are available. */ +/* rdp: in none, out byte status */ +/* No argument, no return value. status == ok if available */ + +#define RDIInfo_CoPro 6 +/* Inquires whether CoPro RDI_Info calls are available. */ +/* rdp: in none, out byte status */ +/* No argument, no return value. status == ok if available */ + +#define RDIInfo_Icebreaker 7 +/* Inquires whether debuggee controlled by IceBreaker. */ +/* rdp: in none, out byte status */ +/* No argument, no return value. status == ok if available */ + +#define RDIMemory_Access 8 +/* rdi: out RDI_MemAccessStats *p, in ARMword *handle */ +/* rdp: in word handle */ +/* out word nreads, word nwrites, word sreads, word swrites, */ +/* word ns, word s, byte status */ + +/* Get memory access information for memory block with specified handle */ + +#define RDIMemory_Map 9 +/* rdi: in RDI_MemDescr md[n], in ARMword *n */ +/* rdp: in word n, n * { */ +/* word handle, word start, word limit, */ +/* byte width, byte access */ +/* word Nread_ns, word Nwrite_ns, */ +/* word Sread_ns, word Swrite_ns} */ +/* out byte status */ +/* Sets memory characteristics. */ + +#define RDISet_CPUSpeed 10 +/* rdi: in ARMword *speed */ +/* rdp: in word speed, out byte status */ +/* Sets CPU speed (in ns) */ + +#define RDIRead_Clock 12 +/* rdi: out ARMword *ns, out ARMword *s */ +/* rdp: in none, out word ns, word s, byte status */ +/* Reads simulated time */ + +#define RDIInfo_Memory_Stats 13 +/* Inquires whether RDI_Info codes 8-12 are available */ +/* rdp: in none, out byte status */ +/* No argument, no return value. status == ok if available */ + +/* The next two are only to be used if RDIInfo_DownLoad returned no */ +/* error */ +#define RDIConfig_Count 14 +/* rdi: out ARMword *count */ +/* rdp: out byte status, word count (if status == OK) */ + +/* In addition, the next one is only to be used if RDIConfig_Count */ +/* returned no error */ +typedef struct { unsigned32 version; char name[32]; } RDI_ConfigDesc; +#define RDIConfig_Nth 15 +/* rdi: in ARMword *n, out RDI_ConfigDesc * */ +/* rdp: in word n */ +/* out word version, byte namelen, bytes * bytelen name, */ +/* byte status */ + +/* The next two are only to be used if the value returned by */ +/* RDIInfo_Points has RDIPointCapability_Status set. */ +#define RDIPointStatus_Watch 0x80 +#define RDIPointStatus_Break 0x81 +/* rdi: inout ARMword * (in handle, out hwresource), out ARMword *type */ +/* rdp: in word handle, out word hwresource, word type, byte status */ + +#define RDISignal_Stop 0x100 +/* Requests that the debuggee stop */ +/* No arguments, no return value */ +/* rdp: no reply (when the debuggee stops, there will be a reply to the */ +/* step or execute request which started it) */ + +#define RDIVector_Catch 0x180 +/* rdi: in ARMword *bitmap */ +/* rdp: int word bitmap, out byte status */ +/* bit i in bitmap set to cause vector i to cause entry to debugger */ + +/* The next four are only to be used if RDIInfo_Semihosting returned */ +/* no error */ +#define RDISemiHosting_SetState 0x181 +/* rdi: in ARMword *semihostingstate */ +/* rdp: in word semihostingstate, out byte status */ +#define RDISemiHosting_GetState 0x182 +/* rdi: out ARMword *semihostingstate */ +/* rdp: in none, out word semihostingstate, byte status */ +#define RDISemiHosting_SetVector 0x183 +/* rdi: in ARMword *semihostingvector */ +/* rdp: in word semihostingvector, out byte status */ +#define RDISemiHosting_GetVector 0x184 +/* rdi: out ARMword *semihostingvector */ +/* rdp: in none, out word semihostingvector, byte status */ + +/* The next two are only to be used if RDIInfo_Icebreaker returned */ +/* no error */ +#define RDIIcebreaker_GetLocks 0x185 +/* rdi: out ARMword *lockedstate */ +/* rdp: in none, out word lockedstate, byte status */ + +#define RDIIcebreaker_SetLocks 0x186 +/* rdi: in ARMword *lockedstate */ +/* rdp: in word lockedstate, out byte status */ + +/* lockedstate is a bitmap of the icebreaker registers locked against */ +/* use by IceMan (because explicitly written by the user) */ + +#define RDIInfo_GetLoadSize 0x187 +/* rdi: out ARMword *maxloadsize */ +/* rdp: in none, out word maxloadsize, byte status */ +/* Inquires the maximum length of data transfer the agent is prepared */ +/* to receive */ +/* Only usable if RDIInfo_Target returned RDITarget_CanInquireLoadSize */ +/* rdi: out ARMword *size */ + +/* Only to be used if the value returned by RDIInfo_Target had */ +/* RDITarget_HasCommsChannel set */ +typedef void RDICCProc_ToHost(void *arg, ARMword data); +typedef void RDICCProc_FromHost(void *arg, ARMword *data, int *valid); + +#define RDICommsChannel_ToHost 0x188 +/* rdi: in RDICCProc_ToHost *, in void *arg */ +/* rdp: in byte connect, out byte status */ +#define RDICommsChannel_FromHost 0x189 +/* rdi: in RDICCProc_FromHost *, in void *arg */ +/* rdp: in byte connect, out byte status */ + +#define RDICycles 0x200 +/* rdi: out ARMword cycles[12] */ +/* rdp: in none, out 6 words cycles, byte status */ +/* the rdi result represents 6 big-endian doublewords; the rdp results */ +/* return values for the ls halves of these */ +# define RDICycles_Size 48 + +#define RDIErrorP 0x201 +/* rdi: out ARMaddress *errorp */ +/* rdp: in none, out word errorp, byte status */ +/* Returns the error pointer associated with the last return from step */ +/* or execute with status RDIError_Error. */ + +#define RDISet_Cmdline 0x300 +/* rdi: in char *commandline (a null-terminated string) */ +/* No corresponding RDP operation (cmdline is sent to the agent in */ +/* response to SWI_GetEnv) */ + +#define RDISet_RDILevel 0x301 +/* rdi: in ARMword *level */ +/* rdp: in word level, out byte status */ +/* Sets the RDI/RDP protocol level to be used (must lie between the */ +/* limits returned by RDIInfo_Target). */ + +#define RDISet_Thread 0x302 +/* rdi: in ARMword *threadhandle */ +/* rdp: in word threadhandle, out byte status */ +/* Sets the thread context for subsequent thread-sensitive operations */ +/* (null value sets no thread) */ + +/* The next two are only to be used if RDIInfo_CoPro returned no error */ +#define RDIInfo_DescribeCoPro 0x400 +/* rdi: in int *cpno, Dbg_CoProDesc *cpd */ +/* rdp: in byte cpno, */ +/* cpd->entries * { */ +/* byte rmin, byte rmax, byte nbytes, byte access, */ +/* byte cprt_r_b0, cprt_r_b1, cprt_w_b0, cprt_w_b1} */ +/* byte = 255 */ +/* out byte status */ + +#define RDIInfo_RequestCoProDesc 0x401 +/* rdi: in int *cpno, out Dbg_CoProDesc *cpd */ +/* rpd: in byte cpno */ +/* out nentries * { */ +/* byte rmin, byte rmax, byte nbytes, byte access, */ +/* } */ +/* byte = 255, byte status */ + +#define RDIInfo_Log 0x800 +/* rdi: out ARMword *logsetting */ +/* No corresponding RDP operation */ +#define RDIInfo_SetLog 0x801 +/* rdi: in ARMword *logsetting */ +/* No corresponding RDP operation */ + +#define RDIProfile_Stop 0x500 +/* No arguments, no return value */ +/* rdp: in none, out byte status */ +/* Requests that pc sampling stop */ + +#define RDIProfile_Start 0x501 +/* rdi: in ARMword *interval */ +/* rdp: in word interval, out byte status */ +/* Requests that pc sampling start, with period usec */ + +#define RDIProfile_WriteMap 0x502 +/* rdi: in ARMword map[] */ +/* map[0] is the length of the array, subsequent elements are sorted */ +/* and are the base of ranges for pc sampling (so if the sampled pc */ +/* lies between map[i] and map[i+1], count[i] is incremented). */ +/* rdp: a number of messages, each of form: */ +/* in word len, word size, word offset, words map data */ +/* out status */ +/* len, size and offset are all word counts. */ + +#define RDIProfile_ReadMap 0x503 +/* rdi: in ARMword *len, out ARMword counts[len] */ +/* Requests that the counts array be set to the accumulated pc sample */ +/* counts */ +/* rdp: a number of messages, each of form: */ +/* in word offset, word size */ +/* out words, status */ +/* len, size and offset are all word counts. */ + +#define RDIProfile_ClearCounts 0x504 +/* No arguments, no return value */ +/* rdp: in none, out byte status */ +/* Requests that pc sample counts be set to zero */ + +typedef struct { + ARMword len; + ARMword map[1]; +} RDI_ProfileMap; + +typedef unsigned32 PointHandle; +typedef unsigned32 ThreadHandle; +#define RDINoPointHandle ((PointHandle)-1L) +#define RDINoHandle ((ThreadHandle)-1L) + +struct Dbg_ConfigBlock; +struct Dbg_HostosInterface; +struct Dbg_MCState; +typedef int rdi_open_proc(unsigned type, struct Dbg_ConfigBlock const *config, + struct Dbg_HostosInterface const *i, + struct Dbg_MCState *dbg_state); +typedef int rdi_close_proc(void); +typedef int rdi_read_proc(ARMword source, void *dest, unsigned *nbytes); +typedef int rdi_write_proc(const void *source, ARMword dest, unsigned *nbytes); +typedef int rdi_CPUread_proc(unsigned mode, unsigned32 mask, ARMword *state); +typedef int rdi_CPUwrite_proc(unsigned mode, unsigned32 mask, ARMword const *state); +typedef int rdi_CPread_proc(unsigned CPnum, unsigned32 mask, ARMword *state); +typedef int rdi_CPwrite_proc(unsigned CPnum, unsigned32 mask, ARMword const *state); +typedef int rdi_setbreak_proc(ARMword address, unsigned type, ARMword bound, + PointHandle *handle); +typedef int rdi_clearbreak_proc(PointHandle handle); +typedef int rdi_setwatch_proc(ARMword address, unsigned type, unsigned datatype, + ARMword bound, PointHandle *handle); +typedef int rdi_clearwatch_proc(PointHandle handle); +typedef int rdi_execute_proc(PointHandle *handle); +typedef int rdi_step_proc(unsigned ninstr, PointHandle *handle); +typedef int rdi_info_proc(unsigned type, ARMword *arg1, ARMword *arg2); +typedef int rdi_pointinq_proc(ARMword *address, unsigned type, + unsigned datatype, ARMword *bound); + +typedef enum { + RDI_ConfigCPU, + RDI_ConfigSystem +} RDI_ConfigAspect; + +typedef enum { + RDI_MatchAny, + RDI_MatchExactly, + RDI_MatchNoEarlier +} RDI_ConfigMatchType; + +typedef int rdi_addconfig_proc(unsigned32 nbytes); +typedef int rdi_loadconfigdata_proc(unsigned32 nbytes, char const *data); +typedef int rdi_selectconfig_proc(RDI_ConfigAspect aspect, char const *name, + RDI_ConfigMatchType matchtype, unsigned versionreq, + unsigned *versionp); + +typedef char *getbufferproc(void *getbarg, unsigned32 *sizep); +typedef int rdi_loadagentproc(ARMword dest, unsigned32 size, getbufferproc *getb, void *getbarg); + +typedef struct { + int itemmax; + char const * const *names; +} RDI_NameList; + +typedef RDI_NameList const *rdi_namelistproc(void); + +typedef int rdi_errmessproc(char *buf, int buflen, int errno); + +struct RDIProcVec { + char rditypename[12]; + + rdi_open_proc *open; + rdi_close_proc *close; + rdi_read_proc *read; + rdi_write_proc *write; + rdi_CPUread_proc *CPUread; + rdi_CPUwrite_proc *CPUwrite; + rdi_CPread_proc *CPread; + rdi_CPwrite_proc *CPwrite; + rdi_setbreak_proc *setbreak; + rdi_clearbreak_proc *clearbreak; + rdi_setwatch_proc *setwatch; + rdi_clearwatch_proc *clearwatch; + rdi_execute_proc *execute; + rdi_step_proc *step; + rdi_info_proc *info; + /* V2 RDI */ + rdi_pointinq_proc *pointinquiry; + + /* These three useable only if RDIInfo_DownLoad returns no error */ + rdi_addconfig_proc *addconfig; + rdi_loadconfigdata_proc *loadconfigdata; + rdi_selectconfig_proc *selectconfig; + + rdi_namelistproc *drivernames; + rdi_namelistproc *cpunames; + + rdi_errmessproc *errmess; + + /* Only if RDIInfo_Target returns a value with RDITarget_LoadAgent set */ + rdi_loadagentproc *loadagent; +}; + +#endif + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_STAT.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_STAT.H new file mode 100644 index 0000000..a29976c --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMDBG/DBG_STAT.H @@ -0,0 +1,37 @@ +/* + * ARM debugger toolbox : dbg_stat.h + * Copyright (C) 1992 Advanced Risc Machines Ltd. All rights reserved. + */ + +/* + * RCS $Revision: 1.1 $ + * Checkin $Date: 1995/02/01 14:39:25 $ + * Revising $Author: hmeekings $ + */ + +#ifndef dbg_stat__h +#define dbg_stat__h + +typedef struct { + ARMword handle; + ARMword start, limit; /* start & limit of this region */ + unsigned char width; /* memory width 0,1,2 => 8,16,32 bit */ + unsigned char access; /* Bit 0 => read access */ + /* Bit 1 => write access */ + /* Bit 2 => latched 32 bit memory */ + unsigned char d1, d2; /* ensure padding */ + /* Access times for R/W N/S cycles */ + unsigned long Nread_ns, Nwrite_ns, Sread_ns, Swrite_ns; +} RDI_MemDescr; + +typedef struct { + ARMword Nreads, /* Counts for R/W N/S cycles */ + Nwrites, + Sreads, + Swrites; + ARMword ns, /* Time (nsec, sec) */ + s; +} RDI_MemAccessStats; + +#endif + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMCOPRO.C b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMCOPRO.C new file mode 100644 index 0000000..15afbc6 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMCOPRO.C @@ -0,0 +1,360 @@ +/***************************************************************************\ +* armcopro.c * +* ARMulator II co-processor interface. * +* Copyright (C) 1991 Advanced RISC Machines Limited. All rights reserved. * +* Written by Dave Jaggar. * +* Project started on 1st July 1991. * +\***************************************************************************/ + +/* RCS $Revision: 1.13 $ + * Checkin $Date: 1994/02/28 11:33:39 $ + * Revising $Author: hmeekings $ + */ + +#include "armdefs.h" + +extern unsigned ARMul_CoProInit(ARMul_State *state) ; +extern void ARMul_CoProExit(ARMul_State *state) ; +extern void ARMul_CoProAttach(ARMul_State *state, unsigned number, + ARMul_CPInits *init, ARMul_CPExits *exit, + ARMul_LDCs *ldc, ARMul_STCs *stc, + ARMul_MRCs *mrc, ARMul_MCRs *mcr, + ARMul_CDPs *cdp, + ARMul_CPReads *read, ARMul_CPWrites *write, + unsigned char const *regwords) ; +extern void ARMul_CoProDetach(ARMul_State *state, unsigned number) ; + + +/***************************************************************************\ +* Dummy Co-processors * +\***************************************************************************/ + +static unsigned NoCoPro3R(ARMul_State *state,unsigned,ARMword) ; +static unsigned NoCoPro4R(ARMul_State *state,unsigned,ARMword,ARMword) ; +static unsigned NoCoPro4W(ARMul_State *state,unsigned,ARMword,ARMword *) ; + +/***************************************************************************\ +* Define Co-Processor instruction handlers here * +\***************************************************************************/ + +/* Here's ARMulator's MMU definition. A few things to note: +1) it has eight registers, but only two are defined. +2) you can only access its registers with MCR and MRC. +3) MMU Register 0 (ID) returns 0x41440110 +4) Register 1 only has 4 bits defined. Bits 0 to 3 are unused, bit 4 +controls 32/26 bit program space, bit 5 controls 32/26 bit data space, +bit 6 controls late abort timimg and bit 7 controls big/little endian. +*/ + +static ARMword MMUReg[8] ; +static const unsigned char MMURegWords[] = {8,1,1,1,1,1,1,1,1}; + +static unsigned MMUInit(ARMul_State *state) +{MMUReg[1] = state->prog32Sig << 4 | + state->data32Sig << 5 | + state->lateabtSig << 6 | + state->bigendSig << 7 ; + ARMul_ConsolePrint(state, ", MMU present") ; + return(TRUE) ; +} + +static unsigned MMUMRC(ARMul_State *state, unsigned type, ARMword instr,ARMword *value) +{int reg = (int)(BITS(16,19) & 7) ; + + if (reg == 0) + *value = 0x41440110 ; + else + *value = MMUReg[reg] ; + return(ARMul_DONE) ; + } + +static unsigned MMUMCR(ARMul_State *state, unsigned type, ARMword instr, ARMword value) +{int reg = (int)(BITS(16,19) & 7) ; + + MMUReg[reg] = value ; + if (reg == 1) { + state->prog32Sig = (unsigned)((value >> 4) & 1) ; + state->data32Sig = (unsigned)((value >> 5) & 1) ; + state->lateabtSig = (unsigned)((value >> 6) & 1) ; + state->bigendSig = (unsigned)((value >> 7) & 1) ; + state->Emulate = TRUE ; /* force ARMulator to notice these now !*/ + } + return(ARMul_DONE) ; + } + + +static unsigned MMURead(ARMul_State *state, unsigned reg, ARMword *value) +{if (reg == 0) + *value = 0x41440110 ; + else if (reg < 8) + *value = MMUReg[reg] ; + return(TRUE) ; + } + +static unsigned MMUWrite(ARMul_State *state, unsigned reg, ARMword const *valp) +{ARMword value = *valp; + if (reg < 8) + MMUReg[reg] = value ; + if (reg == 1) { + state->prog32Sig = (unsigned)((value >> 4) & 1) ; + state->data32Sig = (unsigned)((value >> 5) & 1) ; + state->lateabtSig = (unsigned)((value >> 6) & 1) ; + state->bigendSig = (unsigned)((value >> 7) & 1) ; + state->Emulate = TRUE ; /* force ARMulator to notice these now !*/ + } + return(TRUE) ; + } + + +/* What follows is the Validation Suite Coprocessor. It uses two +co-processor numbers (4 and 5) and has the follwing functionality. +Sixteen registers. Both co-processor nuimbers can be used in an MCR and +MRC to access these registers. CP 4 can LDC and STC to and from the +registers. CP 4 and CP 5 CDP 0 will busy wait for the number of cycles +specified by a CP register. CP 5 CDP 1 issues a FIQ after a number of +cycles (specified in a CP register), CDP 2 issues an IRQW in the same +way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5 stores a 32 +bit time value in a CP register (actually it's the total number of N, S, +I, C and F cyles) */ + +static ARMword ValReg[16] ; + +static unsigned ValLDC(ARMul_State *state, unsigned type, + ARMword instr, ARMword data) +{static unsigned words ; + + if (type != ARMul_DATA) { + words = 0 ; + return(ARMul_DONE) ; + } + if (BIT(22)) { /* it's a long access, get two words */ + ValReg[BITS(12,15)] = data ; + if (words++ == 4) + return(ARMul_DONE) ; + else + return(ARMul_INC) ; + } + else { /* get just one word */ + ValReg[BITS(12,15)] = data ; + return(ARMul_DONE) ; + } + } + +static unsigned ValSTC(ARMul_State *state, unsigned type, + ARMword instr, ARMword *data) +{static unsigned words ; + + if (type != ARMul_DATA) { + words = 0 ; + return(ARMul_DONE) ; + } + if (BIT(22)) { /* it's a long access, get two words */ + *data = ValReg[BITS(12,15)] ; + if (words++ == 4) + return(ARMul_DONE) ; + else + return(ARMul_INC) ; + } + else { /* get just one word */ + *data = ValReg[BITS(12,15)] ; + return(ARMul_DONE) ; + } + } + +static unsigned ValMRC(ARMul_State *state, unsigned type, ARMword instr,ARMword *value) +{ + *value = ValReg[BITS(16,19)] ; + return(ARMul_DONE) ; + } + +static unsigned ValMCR(ARMul_State *state, unsigned type, ARMword instr, ARMword value) +{ + ValReg[BITS(16,19)] = value ; + return(ARMul_DONE) ; + } + +static unsigned ValCDP(ARMul_State *state, unsigned type, ARMword instr) +{ + static unsigned long finish = 0 ; + ARMword howlong ; + + howlong = ValReg[BITS(0,3)] ; + if (BITS(20,23)==0) { + if (type == ARMul_FIRST) { /* First cycle of a busy wait */ + finish = ARMul_Time(state) + howlong ; + if (howlong == 0) + return(ARMul_DONE) ; + else + return(ARMul_BUSY) ; + } + else if (type == ARMul_BUSY) { + if (ARMul_Time(state) >= finish) + return(ARMul_DONE) ; + else + return(ARMul_BUSY) ; + } + } + return(ARMul_CANT) ; + } + +static unsigned DoAFIQ(ARMul_State *state) +{state->NfiqSig = LOW ; + state->Exception++ ; + return(0) ; +} + +static unsigned DoAIRQ(ARMul_State *state) +{state->NirqSig = LOW ; + state->Exception++ ; + return(0) ; +} + +static unsigned IntCDP(ARMul_State *state, unsigned type, ARMword instr) +{static unsigned long finish ; + ARMword howlong ; + + howlong = ValReg[BITS(0,3)] ; + switch((int)BITS(20,23)) { + case 0 : if (type == ARMul_FIRST) { /* First cycle of a busy wait */ + finish = ARMul_Time(state) + howlong ; + if (howlong == 0) + return(ARMul_DONE) ; + else + return(ARMul_BUSY) ; + } + else if (type == ARMul_BUSY) { + if (ARMul_Time(state) >= finish) + return(ARMul_DONE) ; + else + return(ARMul_BUSY) ; + } + return(ARMul_DONE) ; + case 1 : if (howlong == 0) + ARMul_Abort(state,ARMul_FIQV) ; + else + ARMul_ScheduleEvent(state,howlong,DoAFIQ) ; + return(ARMul_DONE) ; + case 2 : if (howlong == 0) + ARMul_Abort(state,ARMul_IRQV) ; + else + ARMul_ScheduleEvent(state,howlong,DoAIRQ) ; + return(ARMul_DONE) ; + case 3 : state->NfiqSig = HIGH ; + state->Exception-- ; + return(ARMul_DONE) ; + case 4 : state->NirqSig = HIGH ; + state->Exception-- ; + return(ARMul_DONE) ; + case 5 : ValReg[BITS(0,3)] = ARMul_Time(state) ; + return(ARMul_DONE) ; + } + return(ARMul_CANT) ; + } + +/***************************************************************************\ +* Install co-processor instruction handlers in this routine * +\***************************************************************************/ + +unsigned ARMul_CoProInit(ARMul_State *state) +{register unsigned i ; + + for (i = 0 ; i < 16 ; i++) /* initialise tham all first */ + ARMul_CoProDetach(state, i) ; + + /* Install CoPro Instruction handlers here + The format is + ARMul_CoProAttach(state, CP Number, Init routine, Exit routine + LDC routine, STC routine, MRC routine, MCR routine, + CDP routine, Read Reg routine, Write Reg routine, + Register size array) ; + */ + + ARMul_CoProAttach(state, 4, NULL, NULL, + ValLDC, ValSTC, ValMRC, ValMCR, + ValCDP, NULL, NULL, NULL) ; + + ARMul_CoProAttach(state, 5, NULL, NULL, + NULL, NULL, ValMRC, ValMCR, + IntCDP, NULL, NULL, NULL) ; + + ARMul_CoProAttach(state, 15, MMUInit, NULL, + NULL, NULL, MMUMRC, MMUMCR, + NULL, MMURead, MMUWrite, MMURegWords) ; + + + /* No handlers below here */ + + for (i = 0 ; i < 16 ; i++) /* Call all the initialisation routines */ + if (state->CPInit[i]) + (state->CPInit[i])(state) ; + return(TRUE) ; + } + +/***************************************************************************\ +* Install co-processor finalisation routines in this routine * +\***************************************************************************/ + +void ARMul_CoProExit(ARMul_State *state) +{register unsigned i ; + + for (i = 0 ; i < 16 ; i++) + if (state->CPExit[i]) + (state->CPExit[i])(state) ; + for (i = 0 ; i < 16 ; i++) /* Detach all handlers */ + ARMul_CoProDetach(state, i) ; + } + +/***************************************************************************\ +* Routines to hook Co-processors into ARMulator * +\***************************************************************************/ + +void ARMul_CoProAttach(ARMul_State *state, unsigned number, + ARMul_CPInits *init, ARMul_CPExits *exit, + ARMul_LDCs *ldc, ARMul_STCs *stc, + ARMul_MRCs *mrc, ARMul_MCRs *mcr, ARMul_CDPs *cdp, + ARMul_CPReads *read, ARMul_CPWrites *write, + unsigned char const *regwords) +{if (init != NULL) + state->CPInit[number] = init ; + if (exit != NULL) + state->CPExit[number] = exit ; + if (ldc != NULL) + state->LDC[number] = ldc ; + if (stc != NULL) + state->STC[number] = stc ; + if (mrc != NULL) + state->MRC[number] = mrc ; + if (mcr != NULL) + state->MCR[number] = mcr ; + if (cdp != NULL) + state->CDP[number] = cdp ; + if (read != NULL) + state->CPRead[number] = read ; + if (write != NULL) + state->CPWrite[number] = write ; + state->CPRegWords[number] = regwords == NULL ? NULL : regwords+1; +} + +void ARMul_CoProDetach(ARMul_State *state, unsigned number) +{ARMul_CoProAttach(state, number, NULL, NULL, + NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R, + NoCoPro3R, NULL, NULL, NULL) ; + state->CPInit[number] = NULL ; + state->CPExit[number] = NULL ; + state->CPRead[number] = NULL ; + state->CPWrite[number] = NULL ; +} + +/***************************************************************************\ +* There is no CoPro around, so Undefined Instruction trap * +\***************************************************************************/ + +static unsigned NoCoPro3R(ARMul_State *state,unsigned a,ARMword b) +{return(ARMul_CANT) ;} + +static unsigned NoCoPro4R(ARMul_State *state, unsigned a,ARMword b,ARMword c) +{return(ARMul_CANT) ;} + +static unsigned NoCoPro4W(ARMul_State *state, unsigned a,ARMword b,ARMword *c) +{return(ARMul_CANT) ;} + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMDEFS.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMDEFS.H new file mode 100644 index 0000000..8f35bfa --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMDEFS.H @@ -0,0 +1,509 @@ +/***************************************************************************\ +* armdefs.h * +* ARMulator II environment definitions. * +* Copyright (C) Advanced RISC Machines Limited. All rights reserved. * +* Written by Dave Jaggar. * +\***************************************************************************/ + +/* RCS $Revision: 1.30.2.1 $ + * Checkin $Date: 1995/05/14 13:00:08 $ + * Revising $Author: plg $ + */ + +#include +#include + +#define LOW 0 +#define HIGH 1 +#define LOWHIGH 1 +#define HIGHLOW 2 + +#include "host.h" + +typedef unsigned32 ARMword; /* must be 32 bits wide */ + +typedef struct ARMul_State ARMul_State ; +typedef struct MemDescr MemDescr; + +typedef struct EventNode EventNode; + +typedef unsigned ARMul_CPInits(ARMul_State *state) ; +typedef unsigned ARMul_CPExits(ARMul_State *state) ; +typedef unsigned ARMul_LDCs(ARMul_State *state,unsigned type,ARMword instr,ARMword value) ; +typedef unsigned ARMul_STCs(ARMul_State *state,unsigned type,ARMword instr,ARMword *value) ; +typedef unsigned ARMul_MRCs(ARMul_State *state,unsigned type,ARMword instr,ARMword *value) ; +typedef unsigned ARMul_MCRs(ARMul_State *state,unsigned type,ARMword instr,ARMword value) ; +typedef unsigned ARMul_CDPs(ARMul_State *state,unsigned type,ARMword instr) ; +typedef unsigned ARMul_CPReads(ARMul_State *state,unsigned reg,ARMword *value) ; +typedef unsigned ARMul_CPWrites(ARMul_State *state,unsigned reg,ARMword const *value) ; +typedef void ARMul_ModeChangeUpcall(ARMul_State *state, ARMword oldmode, ARMword newmode); + +#include "dbg_stat.h" + +struct MemDescr { + MemDescr *next; + RDI_MemDescr md; + RDI_MemAccessStats a; + int ns_LoadInstrS; + int ns_LoadInstrN; + int ns_LoadInstr16S; + int ns_LoadInstr16N; + int ns_LoadWordS; + int ns_LoadWordN; + int ns_LoadHalfWord; + int ns_LoadByte; + int ns_StoreWordS; + int ns_StoreWordN; + int ns_StoreHalfWord; + int ns_StoreByte; + int ns_SwapWord; + int ns_SwapByte; +}; + +struct ARMul_State { + unsigned Processor ; /* type of ARM we are emulating */ + unsigned Instruction_set ; /* 1=16 bits or 0=32, added for thumb */ + ARMword Emulate ; /* to start and stop emulation */ + unsigned EndCondition ; /* reason for stopping */ + unsigned ErrorCode ; /* type of illegal instruction */ + ARMword Reg[16] ; /* the current register file */ + ARMword RegBank[7][16] ; /* all the registers */ + ARMword Cpsr ; /* the current psr */ + ARMword Spsr[7] ; /* the exception psr's */ + ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags ; /* dummy flags for speed */ + ARMword Bank ; /* the current register bank */ + ARMword Mode ; /* the current mode */ + ARMword instr, pc, temp ; /* saved register state */ + ARMword loaded, decoded ; /* saved pipeline state */ + unsigned long NumScycles, + NumNcycles, + NumIcycles, + NumCcycles, + NumFcycles ; /* emulated cycles used */ + unsigned long NumInstrs ; /* the number of instructions executed */ + unsigned long cpu_ns; + unsigned long ns, s; + unsigned NextInstr ; + unsigned VectorCatch ; /* caught exception mask */ + unsigned CallDebug ; /* set to call the debugger */ + unsigned CanWatch ; /* set by memory interface if its willing to suffer the + overhead of checking for watchpoints on each memory + access */ + unsigned MemReadDebug, MemWriteDebug ; + unsigned long StopHandle ; + + unsigned char *MemDataPtr ; /* admin data */ + MemDescr *MemInfoPtr ; + unsigned char *MemInPtr ; /* the Data In bus */ + unsigned char *MemOutPtr ; /* the Data Out bus (which you may not need */ + unsigned char *MemSparePtr ; /* extra space */ + ARMword MemSize ; + + unsigned char *OSptr ; /* OS Handle */ + char *CommandLine ; /* Command Line from ARMsd */ + + ARMul_CPInits *CPInit[16] ; /* coprocessor initialisers */ + ARMul_CPExits *CPExit[16] ; /* coprocessor finalisers */ + ARMul_LDCs *LDC[16] ; /* LDC instruction */ + ARMul_STCs *STC[16] ; /* STC instruction */ + ARMul_MRCs *MRC[16] ; /* MRC instruction */ + ARMul_MCRs *MCR[16] ; /* MCR instruction */ + ARMul_CDPs *CDP[16] ; /* CDP instruction */ + ARMul_CPReads *CPRead[16] ; /* Read CP register */ + ARMul_CPWrites *CPWrite[16] ; /* Write CP register */ + unsigned char *CPData[16] ; /* Coprocessor data */ + unsigned char const *CPRegWords[16] ; /* map of coprocessor register sizes */ + + unsigned EventSet ; /* the number of events in the queue */ + unsigned long Now ; /* time to the nearest cycle */ + EventNode **EventPtr ; /* the event list */ + + unsigned Exception ; /* enable the next four values */ + unsigned Debug ; /* show instructions as they are executed */ + unsigned NresetSig ; /* reset the processor */ + unsigned NfiqSig ; + unsigned NirqSig ; + + unsigned abortSig ; + unsigned NtransSig ; + unsigned bigendSig ; + unsigned prog32Sig ; + unsigned data32Sig ; + unsigned lateabtSig ; + ARMword Vector ; /* synthesize aborts in cycle modes */ + ARMword Aborted ; /* sticky flag for aborts */ + ARMword Reseted ; /* sticky flag for Reset */ + ARMword Inted, LastInted ; /* sticky flags for interrupts */ + ARMword Base ; /* extra hand for base writeback */ + ARMword AbortAddr ; /* to keep track of Prefetch aborts */ + +#ifdef CYCLEBASED + unsigned NextCycle ; /* the position in the state machine */ + ARMword TempReg[16] ; /* undo aborts with these */ + unsigned NumCycles ; /* counter for state iterations */ + ARMword Temp ; /* sometimes you just need an extra hand */ + + ARMword addrBus ; + ARMword datainBus ; + ARMword dataoutBus ; + unsigned mas0Sig; /* Thumb memory access size mas[0] */ + unsigned NbwSig ; /* = mas[1] */ + unsigned NrwSig ; + unsigned seqSig ; + unsigned NmreqSig ; + unsigned NopcSig ; + unsigned NexecSig ; + unsigned lockSig ; + unsigned NmBus ; + unsigned NcpiSig ; + unsigned cpaSig ; + unsigned cpbSig ; + unsigned doutenSig ; /* synthesize NENOUT with this plus DBE */ + + unsigned LSCActive ; /* LDC or STC is happening */ + ARMword addr01Bus ; /* used to fake the bottom two bits of address */ + unsigned LastCycle ; /* so you can know what you did last */ + ARMword NextaddrBus ; /* extra hands for the coprocessor fix up routine */ + unsigned NextNrwSig ; + unsigned NextseqSig ; + unsigned NextNmreqSig ; + unsigned NextNopcSig ; + ARMword PrevaddrBus ; + unsigned PrevNrwSig ; + ARMword OldBase ; /* undo aborts with this */ + + unsigned mclkSig ; + unsigned NwaitSig ; + unsigned tdiSig, tdoSig, tmsSig, NtrstSig ; /* Boundary scan interface */ + char *TAPDataPtr ; + struct ARMul_State *Core ; /* used when in BS test mode */ + ARMword BSID ; /* the boundary scan identification number */ +#endif + + const struct Dbg_HostosInterface *hostif; + + ARMul_ModeChangeUpcall *ModeChange; + unsigned clearAborts; /* Set this <>0 to have aborts cleared for you */ + + unsigned fpe; /* 0 if fpe shouldn't be/isn't loaded */ + } ; + +#define ResetPin NresetSig +#define FIQPin NfiqSig +#define IRQPin NirqSig +#define AbortPin abortSig +#define TransPin NtransSig +#define BigEndPin bigendSig +#define Prog32Pin prog32Sig +#define Data32Pin data32Sig +#define LateAbortPin lateabtSig +#ifdef CYCLEBASED +#define AddrBus addrBus +#define DataInBus datainBus +#define DataOutBus dataoutBus +#define BWPin NbwSig +#define RWPin NrwSig +#define SeqPin seqSig +#define MreqPin NmreqSig +#define OpcPin NopcSig +#define ExecPin NexecSig +#define LockPin lockSig +#define ModePins NmBus +#define CPIPin NcpiSig +#define CPAPin cpaSig +#define CPBPin cpbSig +#define TDIPin tdiSig +#define TDOPin tdoSig +#define TMSPin tmsSig +#define NTRSTPin NtrstSig +#endif + +/***************************************************************************\ +* Types of ARM we know about * +\***************************************************************************/ + +/* The bitflags */ +#define ARM_Fix26_Prop 0x01 +#define ARM_Nexec_Prop 0x02 +#define ARM_Abort7_Prop 0x04 +#define ARM_Mult64_Prop 0x08 +#define ARM_Debug_Prop 0x10 +#define ARM_Isync_Prop ARM_Debug_Prop +#define ARM_Lock_Prop 0x20 +#define ARM_Halfword_Prop 0x40 +#define ARM_Code16_Prop 0x80 +#define ARM_System32_Prop 0x100 + +/* ARM2 family */ +#define ARM2 (ARM_Fix26_Prop) +#define ARM2as ARM2 +#define ARM61 ARM2 +#define ARM3 ARM2 + +/* ARM6 family */ +#define ARM6 (ARM_Lock_Prop) +#define ARM60 ARM6 +#define ARM600 ARM6 +#define ARM610 ARM6 +#define ARM620 ARM6 + +/* ARM7 family */ +#define ARM7 (ARM_Nexec_Prop | ARM_Abort7_Prop) +#define ARM70 ARM7 +#define ARM700 ARM7 +/* ...with debug */ +#define ARM7d (ARM7 | ARM_Debug_Prop) +#define ARM70d ARM7d +/* ...with extended multiply */ +#define ARM7dm (ARM7d | ARM_Mult64_Prop) +#define ARM70dm ARM7dm +/* ...with halfwords and 16 bit instruction set and system mode */ +#define ARM7tdm (ARM7dm | ARM_Halfword_Prop | ARM_Code16_Prop | ARM_System32_Prop) + +/***************************************************************************\ +* Macros to extract instruction fields * +\***************************************************************************/ + +#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */ +#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */ +#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */ + +/***************************************************************************\ +* The hardware vector addresses * +\***************************************************************************/ + +#define ARMResetV 0L +#define ARMUndefinedInstrV 4L +#define ARMSWIV 8L +#define ARMPrefetchAbortV 12L +#define ARMDataAbortV 16L +#define ARMAddrExceptnV 20L +#define ARMIRQV 24L +#define ARMFIQV 28L +#define ARMErrorV 32L /* This is an offset, not an address ! */ + +#define ARMul_ResetV ARMResetV +#define ARMul_UndefinedInstrV ARMUndefinedInstrV +#define ARMul_SWIV ARMSWIV +#define ARMul_PrefetchAbortV ARMPrefetchAbortV +#define ARMul_DataAbortV ARMDataAbortV +#define ARMul_AddrExceptnV ARMAddrExceptnV +#define ARMul_IRQV ARMIRQV +#define ARMul_FIQV ARMFIQV + +/***************************************************************************\ +* Mode and Bank Constants * +\***************************************************************************/ + +#define USER26MODE 0L +#define FIQ26MODE 1L +#define IRQ26MODE 2L +#define SVC26MODE 3L +#define USER32MODE 16L +#define FIQ32MODE 17L +#define IRQ32MODE 18L +#define SVC32MODE 19L +#define ABORT32MODE 23L +#define UNDEF32MODE 27L +#define SYSTEM32MODE 31L + +#define ARM32BITMODE (state->Mode > 3) +#define ARM26BITMODE (state->Mode <= 3) +#define ARMMODE (state->Mode) +#define ARMul_MODEBITS 0x1fL +#define ARMul_MODE32BIT ARM32BITMODE +#define ARMul_MODE26BIT ARM26BITMODE + +#define USERBANK 0 +#define FIQBANK 1 +#define IRQBANK 2 +#define SVCBANK 3 +#define ABORTBANK 4 +#define UNDEFBANK 5 +#define DUMMYBANK 6 + +/***************************************************************************\ +* Definitions of things in the emulator * +\***************************************************************************/ + +extern void ARMul_EmulateInit(void) ; +extern ARMul_State *ARMul_NewState(void) ; +extern void ARMul_Reset(ARMul_State *state) ; +extern void ARMul_SelectProcessor(ARMul_State *state, unsigned processor) ; +#ifdef CYCLEBASED +extern ARMword ARMul_DoCycle(ARMul_State *state) ; +extern unsigned ARMul_DoCoPro(ARMul_State *state) ; +#else +extern ARMword ARMul_DoProg(ARMul_State *state) ; +extern ARMword ARMul_DoInstr(ARMul_State *state) ; +#endif + +/***************************************************************************\ +* Definitions of things for event handling * +\***************************************************************************/ + +extern void ARMul_ScheduleEvent(ARMul_State *state, unsigned long delay, unsigned (*func)() ) ; +extern void ARMul_InvokeEvent(ARMul_State *state) ; +extern unsigned long ARMul_Time(ARMul_State *state) ; + +/***************************************************************************\ +* Useful support routines * +\***************************************************************************/ + +extern ARMword ARMul_GetReg(ARMul_State *state, unsigned mode, unsigned reg) ; +extern void ARMul_SetReg(ARMul_State *state, unsigned mode, unsigned reg, ARMword value) ; +extern ARMword ARMul_GetPC(ARMul_State *state) ; +extern ARMword ARMul_GetNextPC(ARMul_State *state) ; +extern void ARMul_SetPC(ARMul_State *state, ARMword value) ; +extern ARMword ARMul_GetR15(ARMul_State *state) ; +extern void ARMul_SetR15(ARMul_State *state, ARMword value) ; + +extern ARMword ARMul_GetCPSR(ARMul_State *state) ; +extern void ARMul_SetCPSR(ARMul_State *state, ARMword value) ; +extern ARMword ARMul_GetSPSR(ARMul_State *state, ARMword mode) ; +extern void ARMul_SetSPSR(ARMul_State *state, ARMword mode, ARMword value) ; + +/***************************************************************************\ +* Definitions of things to handle aborts * +\***************************************************************************/ + +extern void ARMul_Abort(ARMul_State *state, ARMword address) ; +#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */ +#ifdef CODE16 +#define ARMul_PREFETCHABORT(address) \ + if (state->AbortAddr == 1) \ + state->AbortAddr = (address & (INSTRUCTION16STATE ? ~1L : ~3L)) +#else +#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \ + state->AbortAddr = (address & ~3L) +#endif +#define ARMul_DATAABORT(address) state->abortSig = HIGH ; \ + state->Aborted = ARMul_DataAbortV ; +#define ARMul_CLEARABORT state->abortSig = LOW + +#ifndef CYCLEBASED + +/***************************************************************************\ +* Definitions of things in the memory interface * +\***************************************************************************/ + +extern unsigned ARMul_MemoryInit(ARMul_State *state,unsigned long initmemsize) ; +extern void ARMul_MemoryExit(ARMul_State *state) ; + +extern ARMword ARMul_LoadInstrS(ARMul_State *state,ARMword address) ; +extern ARMword ARMul_LoadInstrN(ARMul_State *state,ARMword address) ; + +extern ARMword ARMul_LoadWordS(ARMul_State *state,ARMword address) ; +extern ARMword ARMul_LoadWordN(ARMul_State *state,ARMword address) ; +extern ARMword ARMul_LoadByte(ARMul_State *state,ARMword address) ; + +extern void ARMul_StoreWordS(ARMul_State *state,ARMword address, ARMword data) ; +extern void ARMul_StoreWordN(ARMul_State *state,ARMword address, ARMword data) ; +extern void ARMul_StoreByte(ARMul_State *state,ARMword address, ARMword data) ; + +extern ARMword ARMul_LoadInstr16S(ARMul_State *state,ARMword address) ; +extern ARMword ARMul_LoadInstr16N(ARMul_State *state,ARMword address) ; +extern ARMword ARMul_LoadHalfWord(ARMul_State *state,ARMword address) ; +extern void ARMul_StoreHalfWord(ARMul_State *state,ARMword address, ARMword data) ; +extern ARMword ARMul_ReadHalfWord(ARMul_State *state,ARMword address) ; +extern void ARMul_WriteHalfWord(ARMul_State *state,ARMword address, ARMword data) ; + +extern ARMword ARMul_SwapWord(ARMul_State *state,ARMword address, ARMword data) ; +extern ARMword ARMul_SwapByte(ARMul_State *state,ARMword address, ARMword data) ; + +extern void ARMul_Icycles(ARMul_State *state,unsigned number, ARMword address) ; +extern void ARMul_Ccycles(ARMul_State *state,unsigned number, ARMword address) ; + +extern ARMword ARMul_ReadWord(ARMul_State *state,ARMword address) ; +extern ARMword ARMul_ReadByte(ARMul_State *state,ARMword address) ; +extern void ARMul_WriteWord(ARMul_State *state,ARMword address, ARMword data) ; +extern void ARMul_WriteByte(ARMul_State *state,ARMword address, ARMword data) ; + +extern ARMword ARMul_MemAccess(ARMul_State *state,ARMword,ARMword,ARMword, + ARMword,ARMword,ARMword,ARMword,ARMword,ARMword,ARMword,ARMword) ; + +/***************************************************************************\ +* Definitions of things in the co-processor interface * +\***************************************************************************/ + +#define ARMul_FIRST 0 +#define ARMul_TRANSFER 1 +#define ARMul_BUSY 2 +#define ARMul_DATA 3 +#define ARMul_INTERRUPT 4 +#define ARMul_DONE 0 +#define ARMul_CANT 1 +#define ARMul_INC 3 + +extern unsigned ARMul_CoProInit(ARMul_State *state) ; +extern void ARMul_CoProExit(ARMul_State *state) ; +extern void ARMul_CoProAttach(ARMul_State *state, unsigned number, + ARMul_CPInits *init, ARMul_CPExits *exit, + ARMul_LDCs *ldc, ARMul_STCs *stc, + ARMul_MRCs *mrc, ARMul_MCRs *mcr, + ARMul_CDPs *cdp, + ARMul_CPReads *read, ARMul_CPWrites *write, + unsigned char const *regwords) ; +extern void ARMul_CoProDetach(ARMul_State *state, unsigned number) ; + +/***************************************************************************\ +* Definitions of things in the host environment * +\***************************************************************************/ + +extern unsigned ARMul_OSInit(ARMul_State *state) ; +extern void ARMul_OSExit(ARMul_State *state) ; +extern unsigned ARMul_OSHandleSWI(ARMul_State *state,ARMword number) ; +extern ARMword ARMul_OSLastErrorP(ARMul_State *state) ; +#else +char *ARMul_Disass(ARMword instr, ARMword address, ARMword cpsr) ; +extern char *ARMul_ErrorMess(ARMul_State *state,unsigned number) ; +#define UNDEF_BadInstruction 132 +#define UNDEF_IllInstruction 133 +#endif /* CYCLEBASED */ + +extern ARMword ARMul_Debug(ARMul_State *state, ARMword pc, ARMword instr) ; +extern void ARMul_CheckWatch(ARMul_State *state, ARMword addr, int access) ; + +extern unsigned ARMul_OSException(ARMul_State *state, ARMword vector, ARMword pc) ; +extern void ARMul_DebugPrint(ARMul_State *state, const char *format, ...); +extern void ARMul_DebugPause(ARMul_State *state); +extern void ARMul_ConsolePrint(ARMul_State *state, const char *format, ...); + +/* IF the macro HOURGLASS_RATE is defined, then you must provide this fn */ +#ifdef HOURGLASS_RATE +extern void armsd_hourglass(void); +#endif + +/***************************************************************************\ +* ARM / THUMB differences * +\***************************************************************************/ + +#define INSTRUCTION32SIZE (4) +#define INSTRUCTION32 (0) + +#ifdef CODE16 +/* state->Instruction_set values */ + +#define INSTRUCTION16 (1) + +#define INSTRUCTION16STATE (state->Instruction_set == INSTRUCTION16) + +#define INSTRUCTION16SIZE (2) +#define INSTRUCTIONSIZE (INSTRUCTION16STATE ? INSTRUCTION16SIZE : INSTRUCTION32SIZE) + +/* bits in registers */ + +#define BXINSTRUCTIONSETBITS (0x1) +#define CPSRINSTRUCTIONSETBITPOSN (5) +#define CPSRINSTRUCTIONSETBITS (0x1 << CPSRINSTRUCTIONSETBITPOSN) + +#define BXINSTRUCTIONSET(r) ((r & BXINSTRUCTIONSETBITS) ? INSTRUCTION16 : INSTRUCTION32) +#define CPSRINSTRUCTIONSET(r) ((r & CPSRINSTRUCTIONSETBITS) ? INSTRUCTION16 : INSTRUCTION32) +#define CPSRINSTRUCTIONSIZE(r) ((r & CPSRINSTRUCTIONSETBITS) ? INSTRUCTION16SIZE : INSTRUCTION32SIZE) + +#else +#define INSTRUCTIONSIZE INSTRUCTION32SIZE +#define CPSRINSTRUCTIONSET(r) (INSTRUCTION32) +#define CPSRINSTRUCTIONSIZE(r) (INSTRUCTION32SIZE) +#endif + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFAST.C b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFAST.C new file mode 100644 index 0000000..4f31123 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFAST.C @@ -0,0 +1,365 @@ +/***************************************************************************\ +* armfast.c * +* Version 1.20 * +* ARMulator II Simple Memory Interface. * +* Copyright (C) 1991 Advanced RISC Machines Limited. All rights reserved. * +* Written by Dave Jaggar. * +* Project started on 1st July 1991. * +\***************************************************************************/ + +/* + * RCS $Revision: 1.14 $ + * Checkin $Date: 1995/01/18 12:26:52 $ + * Revising $Author: hmeekings $ + */ + +/* This file contains the fastest of example ARMulator memory systems. +It implements the ARM's memory as a fixed size block of host memory, and +does endian switching for byte accesses only. Memory accesses outside +the memory block are truncated to the size of the memory block. Each +routine is almost a cut-and-paste of some other, it's all quite simple */ +/* Halfwords added 940909 by Andy Chapman */ + +#include "armdefs.h" + +#define DEFMEMSIZE (512 * 1024) /* default memory size, must be a power of 2 */ +#define WORDWRAP (DEFMEMSIZE - 4) +#define HWORDWRAP (DEFMEMSIZE - 2) +#define BYTEWRAP (DEFMEMSIZE - 1) + +#define WORDMASK(addr) (addr & WORDWRAP) +#define HWORDMASK(addr) (addr & HWORDWRAP) +#define BYTEMASK(addr) (addr & BYTEWRAP) +#define ENDSWAP(addr) (addr ^ 3) +#define ENDSWAPH(addr) (addr ^ 2) +#define ENDSWAPB(addr) (addr ^ 1) +static unsigned HostEndian ; + +#ifdef DOWATCH +#include "dbg_rdi.h" +#endif + +/***************************************************************************\ +* Initialise the memory interface * +\***************************************************************************/ + +unsigned ARMul_MemoryInit(ARMul_State *state, unsigned long initmemsize) +{unsigned char *Memory ; + + if (initmemsize == 0 || initmemsize > DEFMEMSIZE) + initmemsize = DEFMEMSIZE ; + state->MemSize = initmemsize ; + Memory = (unsigned char *)malloc(DEFMEMSIZE) ; + if (Memory == NULL) + return(FALSE) ; + state->MemInPtr = Memory ; + *(ARMword *)Memory = 1 ; + HostEndian = (*Memory != 1) ; /* 1 for big endian, 0 for little */ +#ifdef BIGEND + state->bigendSig = HIGH ; +#endif +#ifdef LITTLEEND + state->bigendSig = LOW ; +#endif + ARMul_ConsolePrint(state, ", %d Kb RAM",state->MemSize/1024) ; +#ifdef DOWATCH + state->CanWatch = TRUE ; +#endif + return(TRUE) ; +} + +/***************************************************************************\ +* Remove the memory interface * +\***************************************************************************/ + +void ARMul_MemoryExit(ARMul_State *state) +{free((char *)state->MemInPtr) ; + return ; + } + +/***************************************************************************\ +* Load Instruction, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstrS(ARMul_State *state,ARMword address) +{state->NumScycles++ ; + +#ifdef DOWATCH + if (state->MemReadDebug) ARMul_CheckWatch(state, address, RDIWatch_WordRead); +#endif + +#ifdef HOURGLASS_RATE + if( (state->NumScycles & HOURGLASS_RATE) == 0 ) { + armsd_hourglass(); + } +#endif + + return( *(ARMword *)(state->MemInPtr + WORDMASK(address)) ) ; +} + +/***************************************************************************\ +* Load Instruction, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstrN(ARMul_State *state,ARMword address) +{state->NumNcycles++ ; +#ifdef DOWATCH + if (state->MemReadDebug) ARMul_CheckWatch(state, address, RDIWatch_WordRead); +#endif + return( *(ARMword *)(state->MemInPtr + WORDMASK(address)) ) ; +} + +/***************************************************************************\ +* Load 16 Bit Instruction, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstr16S(ARMul_State *state,ARMword address) +{state->NumScycles++ ; + +#ifdef HOURGLASS_RATE + if( (state->NumScycles & HOURGLASS_RATE) == 0 ) { + armsd_hourglass(); + } +#endif + + return( (*(ARMword *)(state->MemInPtr + WORDMASK(address))) >> + ((((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3) & + 0xffffL ) ; +} + +/***************************************************************************\ +* Load 16 Bit Instruction, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstr16N(ARMul_State *state,ARMword address) +{state->NumNcycles++ ; + return( (*(ARMword *)(state->MemInPtr + WORDMASK(address))) >> + ((((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3) & + 0xffffL ) ; +} + +/***************************************************************************\ +* Load Word, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadWordS(ARMul_State *state,ARMword address) +{state->NumScycles++ ; +#ifdef DOWATCH + if (state->MemReadDebug) ARMul_CheckWatch(state, address, RDIWatch_WordRead); +#endif + return( *(ARMword *)(state->MemInPtr + WORDMASK(address)) ) ; +} + +/***************************************************************************\ +* Load Word, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadWordN(ARMul_State *state,ARMword address) +{state->NumNcycles++ ; +#ifdef DOWATCH + if (state->MemReadDebug) ARMul_CheckWatch(state, address, RDIWatch_WordRead); +#endif + return( *(ARMword *)(state->MemInPtr + WORDMASK(address)) ) ; +} + +/***************************************************************************\ +* Load Halfword, (Non Sequential Cycle) * +\***************************************************************************/ + +ARMword ARMul_LoadHalfWord(ARMul_State *state,ARMword address) +{state->NumNcycles++ ; + address = BYTEMASK(address); + if (HostEndian == state->bigendSig) { + return( (ARMword)((*(state->MemInPtr + address) << 8) + + *(state->MemInPtr + ENDSWAPB(address)))) ; + } else { + return( (ARMword)((*(state->MemInPtr + ENDSWAPH(address)) << 8)+ + *(state->MemInPtr + ENDSWAPB(ENDSWAPH(address))))) ; + } +} + +/***************************************************************************\ +* Load Byte, (Non Sequential Cycle) * +\***************************************************************************/ + +ARMword ARMul_LoadByte(ARMul_State *state,ARMword address) +{state->NumNcycles++ ; +#ifdef DOWATCH + if (state->MemReadDebug) ARMul_CheckWatch(state, address, RDIWatch_ByteRead); +#endif + if (HostEndian == state->bigendSig) + return( (ARMword)*(state->MemInPtr + BYTEMASK(address)) ) ; + else + return( (ARMword)*(state->MemInPtr + ENDSWAP(BYTEMASK(address))) ) ; +} + +/***************************************************************************\ +* Store Word, Sequential Cycle * +\***************************************************************************/ + +void ARMul_StoreWordS(ARMul_State *state,ARMword address, ARMword data) +{state->NumScycles++ ; +#ifdef DOWATCH + if (state->MemWriteDebug) ARMul_CheckWatch(state, address, RDIWatch_WordWrite); +#endif + *(ARMword *)(state->MemInPtr + WORDMASK(address)) = data ; +} +/***************************************************************************\ +* Store Word, Sequential Cycle * +\***************************************************************************/ + +void ARMul_StoreWordN(ARMul_State *state,ARMword address, ARMword data) +{state->NumNcycles++ ; +#ifdef DOWATCH + if (state->MemWriteDebug) ARMul_CheckWatch(state, address, RDIWatch_WordWrite); +#endif + *(ARMword *)(state->MemInPtr + WORDMASK(address) ) = data ; +} + +/***************************************************************************\ +* Store HalfWord, (Non Sequential Cycle) * +\***************************************************************************/ + +void ARMul_StoreHalfWord(ARMul_State *state,ARMword address, ARMword data) +{state->NumNcycles++ ; + + address = HWORDMASK(address); + if (HostEndian == state->bigendSig) { + *(state->MemInPtr + address) = (unsigned char)((data & 0xff00) >> 8); + *(state->MemInPtr + address + 1) = (unsigned char)data ; + } else { + *(state->MemInPtr + ENDSWAPH(address)) = (unsigned char)((data & 0xff00) >> 8); + *(state->MemInPtr + ENDSWAPH(address) + 1) = (unsigned char)data ; + } +} + +/***************************************************************************\ +* Store Byte, (Non Sequential Cycle) * +\***************************************************************************/ + +void ARMul_StoreByte(ARMul_State *state,ARMword address, ARMword data) +{state->NumNcycles++ ; +#ifdef DOWATCH + if (state->MemWriteDebug) ARMul_CheckWatch(state, address, RDIWatch_ByteWrite); +#endif + if (HostEndian == state->bigendSig) + *(state->MemInPtr + BYTEMASK(address)) = (unsigned char)data ; + else + *(state->MemInPtr + ENDSWAP(BYTEMASK(address))) = (unsigned char)data ; +} + +/***************************************************************************\ +* Swap Word, (Two Non Sequential Cycles) * +\***************************************************************************/ + +ARMword ARMul_SwapWord(ARMul_State *state,ARMword address, ARMword data) +{ARMword temp ; + + temp = ARMul_LoadWordN(state,address) ; + ARMul_StoreWordN(state,address,data) ; + return(temp) ; +} + +/***************************************************************************\ +* Swap Byte, (Two Non Sequential Cycles) * +\***************************************************************************/ + +ARMword ARMul_SwapByte(ARMul_State *state,ARMword address, ARMword data) +{ARMword temp ; + + temp = ARMul_LoadByte(state,address) ; + ARMul_StoreByte(state,address,data) ; + return(temp) ; +} + +/***************************************************************************\ +* Count I Cycles * +\***************************************************************************/ + +void ARMul_Icycles(ARMul_State *state,unsigned number, ARMword address) +{state->NumIcycles += number ; +} + +/***************************************************************************\ +* Count C Cycles * +\***************************************************************************/ + +void ARMul_Ccycles(ARMul_State *state,unsigned number, ARMword address) +{state->NumCcycles += number ; +} + +/***************************************************************************\ +* Read Word (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadWord(ARMul_State *state,ARMword address) +{ + return( *(ARMword *)(state->MemInPtr + WORDMASK(address)) ) ; +} + +/***************************************************************************\ +* Read Halfword (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadHalfWord(ARMul_State *state,ARMword address) +{ + address = BYTEMASK(address); + if (HostEndian == state->bigendSig) { + return( (ARMword)((*(state->MemInPtr + address) << 8) + + *(state->MemInPtr + ENDSWAPB(address)))) ; + } else { + return( (ARMword)((*(state->MemInPtr + ENDSWAPH(address)) << 8)+ + *(state->MemInPtr + ENDSWAPB(ENDSWAPH(address))))) ; + } +} + +/***************************************************************************\ +* Read Byte (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadByte(ARMul_State *state,ARMword address) +{ + if (HostEndian == state->bigendSig) + return( (ARMword)*(state->MemInPtr + BYTEMASK(address)) ) ; + else + return( (ARMword)*(state->MemInPtr + ENDSWAP(BYTEMASK(address))) ) ; +} + +/***************************************************************************\ +* Write Word (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteWord(ARMul_State *state,ARMword address, ARMword data) +{ + *(ARMword *)(state->MemInPtr + WORDMASK(address)) = data ; +} + +/***************************************************************************\ +* Write Halfword (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteHalfWord(ARMul_State *state,ARMword address, ARMword data) +{ + address = HWORDMASK(address); + if (HostEndian == state->bigendSig) { + *(state->MemInPtr + address) = (unsigned char)((data & 0xff00) >> 8); + *(state->MemInPtr + address + 1) = (unsigned char)data ; + } else { + *(state->MemInPtr + ENDSWAPH(address)) = (unsigned char)((data & 0xff00) >> 8); + *(state->MemInPtr + ENDSWAPH(address) + 1) = (unsigned char)data ; + } +} + +/***************************************************************************\ +* Write Byte (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteByte(ARMul_State *state,ARMword address, ARMword data) +{ + if (HostEndian == state->bigendSig) + *(state->MemInPtr + BYTEMASK(address)) = (unsigned char)data ; + else + *(state->MemInPtr + ENDSWAP(BYTEMASK(address))) = (unsigned char)data ; +} + + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFPE.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFPE.H new file mode 100644 index 0000000..eefaeef --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMFPE.H @@ -0,0 +1,1701 @@ +/* + * RCS $Revision: 1.3.2.1 $ + * Checkin $Date: 1995/05/25 08:35:07 $ + * Revising $Author: plg $ + */ + +#include "aif.h" + +static struct { + struct aif_hdr hdr; + unsigned32 code[6698]; +} fpe = { + { +0xe1a00000,0xe1a00000,0xeb00000c,0x00000000, +0xef000011,0x000068a4,0x00000000,0x000001c4, +0x00000000,0x00000001,0x00001400,0x00000000, +0x00000020,0x00000000,0x00000000,0x00000000, +0xe1a00000,0xe04ec00f,0xe08fc00c,0xe99c000f, +0xe24cc010,0xe59c2030,0xe3120c01,0x159cc034, +0x008cc000,0xe08cc001,0xe3a00000,0xe3530000, +0xd1a0f00e,0xe48c0004,0xe2533004,0xeafffffb, + }, + { +0xeb00192d,0xef000011,0x00000000,0x00000000, +0x00000000,0xe24dd040,0xe8cd7fff,0xe58de03c, +0xe1a0c00d,0xe10fa000,0xe14f9000,0xe92d0600, +0xe319000f,0xe24e9004,0x04b9b000,0x1599b000, +0xe28faa06,0xe28aae62,0xe31b0302,0x0a0005b7, +0xe20b9c0f,0xe3590c01,0x1a0004b9,0xe59a8084, +0xe3380000,0x1a0004b0,0xe10f8000,0xe3c88080, +0xe129f008,0xe1a00000,0xe59a7080,0xe31b0402, +0x1a0003ee,0xe1a0948b,0xe209920a,0xe31b0902, +0x13899101,0xe20b380f,0xe353080f,0x23899201, +0xe51c8008,0xe218800f,0x13899302,0xe2095103, +0xe08ffca9,0x00000000,0xea00001e,0xea00003c, +0xea000074,0xea000081,0xea0001c2,0xea0001e6, +0xea000224,0xea00022b,0xea00008a,0xea0000a9, +0xea0000d3,0xea0000e1,0xea00022f,0xea000257, +0xea000298,0xea00029f,0xea0000ea,0xea00010a, +0xea000134,0xea000143,0xea0002a3,0xea0002c9, +0xea000307,0xea00030e,0xea00014c,0xea00015f, +0xea00018c,0xea00019c,0xea000312,0xea000324, +0xea00034c,0xea000353,0xe20b8a07,0xe08a8428, +0xe8980007,0xe1a05ba5,0xeb000581,0xe20b380f, +0xe79c4723,0xe20b80ff,0xe31b0502,0x10848108, +0x00448108,0xe31b0401,0x11a04008,0xe31b0602, +0x178c8723,0xe4a40000,0xe58a7080,0xe59c903c, +0xe3390000,0x14b9b000,0x100b808b,0x13180302, +0x1b000540,0xe91c0300,0xe129f009,0xe169f008, +0xe1a0d00c,0xe8dc7fff,0xe1a00000,0xe28dd03c, +0xe8fd8000,0xe20b8a07,0xe08a8428,0xe8980007, +0xe1a05ba5,0xeb000562,0xe20b380f,0xe353080d, +0x2a000018,0xe79c4723,0xe20b80ff,0xe31b0502, +0x10848108,0x00448108,0xe31b0401,0x11a04008, +0xe31b0602,0x178c8723,0xe8840001,0xe58a7080, +0xe59c903c,0xe3390000,0x1599b000,0x100b808b, +0x13180302,0x1b00051f,0xe91c0300,0xe129f009, +0xe169f008,0xe1a0d00c,0xe8dc7fff,0xe1a00000, +0xe28dd03c,0xe8fd8000,0xe51c8008,0xe218800f, +0xe10f9000,0xe3888090,0xe3c9401f,0xe1848008, +0xe129f008,0xe353080d,0x01a0400d,0x11a0400e, +0xe20b80ff,0xe31b0502,0x10848108,0x00448108, +0xe31b0401,0x11a04008,0xe31b0602,0x0a000002, +0xe353080d,0x01a0d008,0x11a0e008,0xe129f009, +0xe8840001,0xeaffffd8,0xe20b8a07,0xe08a8428, +0xe8980007,0xe1a05ba5,0xeb000529,0xe59c403c, +0xe2844004,0xe31b0401,0x120b80ff,0x10444108, +0x131b0502,0x10844188,0xe4a40000,0xeaffffa9, +0xe20b8a07,0xe08a8428,0xe8980007,0xe1a05ba5, +0xeb00051b,0xe59c403c,0xe2844004,0xe31b0401, +0x120b80ff,0x10444108,0x131b0502,0x10844188, +0xe8840001,0xeaffffbc,0xe20b8a07,0xe08a8428, +0xe8980007,0xe1a05ba5,0xeb000560,0xe20b380f, +0xe79c4723,0xe20b80ff,0xe31b0502,0x10848108, +0x00448108,0xe31b0401,0x11a04008,0xe31b0602, +0x178c8723,0xe4a40004,0xe4241004,0xe58a7080, +0xe59c903c,0xe3390000,0x14b9b000,0x100b808b, +0x13180302,0x1b0004cb,0xe91c0300,0xe129f009, +0xe169f008,0xe1a0d00c,0xe8dc7fff,0xe1a00000, +0xe28dd03c,0xe8fd8000,0xe20b8a07,0xe08a8428, +0xe8980007,0xe1a05ba5,0xeb000540,0xe20b380f, +0xe353080d,0x2a00000a,0xe79c4723,0xe20b80ff, +0xe31b0502,0x10848108,0x00448108,0xe31b0401, +0x11a04008,0xe31b0602,0x178c8723,0xe8840003, +0xeaffff89,0xe51c8008,0xe218800f,0xe10f9000, +0xe3888090,0xe3c9401f,0xe1848008,0xe129f008, +0xe353080d,0x01a0400d,0x11a0400e,0xe20b80ff, +0xe31b0502,0x10848108,0x00448108,0xe31b0401, +0x11a04008,0xe31b0602,0x0a000002,0xe353080d, +0x01a0d008,0x11a0e008,0xe129f009,0xe8840003, +0xeaffff71,0xe20b8a07,0xe08a8428,0xe8980007, +0xe1a05ba5,0xeb000515,0xe59c403c,0xe2844004, +0xe31b0401,0x120b80ff,0x10444108,0x131b0502, +0x10844188,0xe4a40004,0xe4241004,0xeaffff41, +0xe20b8a07,0xe08a8428,0xe8980007,0xe1a05ba5, +0xeb000506,0xe59c403c,0xe2844004,0xe31b0401, +0x120b80ff,0x10444108,0x131b0502,0x10844188, +0xe8840003,0xeaffff54,0xe20b8a07,0xe08a8428, +0xe8980007,0xe1a05ba5,0xeb000551,0xe20b380f, +0xe79c4723,0xe20b80ff,0xe31b0502,0x10848108, +0x00448108,0xe31b0401,0x11a04008,0xe31b0602, +0x178c8723,0xe4a40004,0xe4a41004,0xe4242008, +0xe58a7080,0xe59c903c,0xe3390000,0x14b9b000, +0x100b808b,0x13180302,0x1b000462,0xe91c0300, +0xe129f009,0xe169f008,0xe1a0d00c,0xe8dc7fff, +0xe1a00000,0xe28dd03c,0xe8fd8000,0xe20b8a07, +0xe08a8428,0xe8980007,0xe1a05ba5,0xeb000530, +0xe20b380f,0xe353080d,0x2a00000a,0xe79c4723, +0xe20b80ff,0xe31b0502,0x10848108,0x00448108, +0xe31b0401,0x11a04008,0xe31b0602,0x178c8723, +0xe8840007,0xeaffff20,0xe51c8008,0xe218800f, +0xe10f9000,0xe3888090,0xe3c9401f,0xe1848008, +0xe129f008,0xe353080d,0x01a0400d,0x11a0400e, +0xe20b80ff,0xe31b0502,0x10848108,0x00448108, +0xe31b0401,0x11a04008,0xe31b0602,0x0a000002, +0xe353080d,0x01a0d008,0x11a0e008,0xe129f009, +0xe8840007,0xeaffff08,0xe20b8a07,0xe08a8428, +0xe8980007,0xe1a05ba5,0xeb000505,0xe59c403c, +0xe2844004,0xe31b0401,0x120b80ff,0x10444108, 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+0x00000000,0x00000000,0x00000000,0x00000000, +0x00000000,0x00000000,0x00000000,0x00000000, +0x00000000,0x00000000,0xffffffff,0x00003bc8, +0x00003c08,0x0000523c,0x000052bc,0x00000002, +0x00007a68,0xffffffff,0x80000204,0x616f6c46, +0x676e6974,0x696f5020,0x4520746e,0x70656378, +0x6e6f6974,0x49203a20,0x6178656e,0x52207463, +0x6c757365,0x00000074,0x80000203,0x616f6c46, +0x676e6974,0x696f5020,0x4520746e,0x70656378, +0x6e6f6974,0x55203a20,0x7265646e,0x776f6c66, +0x00000000,0x80000202,0x616f6c46,0x676e6974, +0x696f5020,0x4520746e,0x70656378,0x6e6f6974, +0x44203a20,0x64697669,0x79422065,0x72655a20, +0x0000006f,0x80000201,0x616f6c46,0x676e6974, +0x696f5020,0x4520746e,0x70656378,0x6e6f6974, +0x4f203a20,0x66726576,0x00776f6c,0x80000200, +0x616f6c46,0x676e6974,0x696f5020,0x4520746e, +0x70656378,0x6e6f6974,0x49203a20,0x6c61766e, +0x4f206469,0x61726570,0x6e6f6974,0x00000000, +0x80000280,0x20455046,0x65746e49,0x6c616e72, +0x72724520,0x3a20726f,0x726f4320,0x61462065, +0x79746c75,0x00000000,0x80000281,0x20455046, +0x65746e49,0x6c616e72,0x72724520,0x3a20726f, +0x726f4320,0x69442065,0x6c626173,0x00006465, +0xef000071,0 + } +}; + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.C b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.C new file mode 100644 index 0000000..cdc0115 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.C @@ -0,0 +1,828 @@ +/***************************************************************************\ +* armos.c * +* ARMulator II Prototype Operating System Interface. * +* Copyright (C) 1991 Advanced RISC Machines Limited. All rights reserved. * +* Written by Dave Jaggar. * +\***************************************************************************/ + +/* + * RCS $Revision: 1.51.2.2 $ + * Checkin $Date: 1995/06/08 18:45:22 $ + * Revising $Author: plg $ + */ + +/* This file contains a model of Demon, ARM Ltd's Debug Monitor, +including all the SWI's required to support the C library. The code in +it is not really for the faint-hearted (especially the abort handling +code), but it is a complete example. Defining NOOS will disable all the +fun, and definign VAILDATE will define SWI 1 to enter SVC mode, and SWI +0x11 to halt the emulator. */ + +#include +#include +#include + +#include "armdefs.h" +#include "armos.h" +#ifndef NOFPE +#ifndef NOOS +#ifndef VALIDATE +#include "armfpe.h" +#endif +#endif +#endif +#include "dbg_hif.h" + +struct fpedesc fpedesc; + +#ifndef __STDC__ +#define remove(s) unlink(s) +#endif + +#ifdef __riscos + extern int _fisatty(FILE *); +# define isatty_(f) _fisatty(f) +# define EMFILE -1 +# define EBADF -1 + int _kernel_escape_seen(void) { return 0 ;} +#else +# if defined(_WINDOWS) || defined(_CONSOLE) +# define isatty_(f) (f == stdin || f == stdout) +# else +# ifdef __ZTC__ +# include +# define isatty_(f) isatty((f)->_file) +# else +# ifdef macintosh +# include +# define isatty_(f) (~ioctl((f)->_file,FIOINTERACTIVE,NULL)) +# else +# define isatty_(f) isatty(fileno(f)) +# endif +# endif +# endif +#endif + +extern unsigned ARMul_OSInit(ARMul_State *state) ; +extern void ARMul_OSExit(ARMul_State *state) ; +extern unsigned ARMul_OSHandleSWI(ARMul_State *state,ARMword number) ; +extern unsigned ARMul_OSException(ARMul_State *state, ARMword vector, ARMword pc) ; +extern ARMword ARMul_OSLastErrorP(ARMul_State *state) ; +extern ARMword ARMul_Debug(ARMul_State *state, ARMword pc, ARMword instr) ; +extern ARMword ARMul_ReadClock(ARMul_State *state) ; + +#define BUFFERSIZE 4096 +#ifndef FOPEN_MAX +#define FOPEN_MAX 64 +#endif +#define UNIQUETEMPS 256 + +#ifndef NOOS +static void UnwindDataAbort(ARMul_State *state, ARMword addr, ARMword iset); +static void getstring(ARMul_State *state, ARMword from, char *to) ; +#endif + +#define OLDINSTRUCTIONSIZE (CPSRINSTRUCTIONSIZE(ARMul_GetSPSR(state, ARMul_GetCPSR(state)))) + +/***************************************************************************\ +* OS private Information * +\***************************************************************************/ + +struct OSblock { + ARMword Time0 ; + ARMword ErrorP ; + ARMword ErrorNo ; + FILE *FileTable[FOPEN_MAX] ; + char FileFlags[FOPEN_MAX] ; + char *tempnames[UNIQUETEMPS] ; + } ; + +#define NOOP 0 +#define BINARY 1 +#define READOP 2 +#define WRITEOP 4 + +#ifdef macintosh +#define FIXCRLF(t,c) ((t & BINARY)?c:((c=='\n'||c=='\r')?(c ^ 7):c)) +#else +#define FIXCRLF(t,c) c +#endif + +static ARMword softvectorcode[] = +{ /* basic: swi tidyexception + event; mov lr, pc; + ldmia r11,{r11,pc}; swi generateexception + event + */ + 0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /*Reset*/ + 0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /*Undef*/ + 0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /*SWI */ + 0xef000093, 0xe1a0e00f, 0xe89b8800, 0xef000083, /*Prefetch abort*/ + 0xef000094, 0xe1a0e00f, 0xe89b8800, 0xef000084, /*Data abort*/ + 0xef000095, 0xe1a0e00f, 0xe89b8800, 0xef000085, /*Address exception*/ + 0xef000096, 0xe1a0e00f, 0xe89b8800, 0xef000086, /*IRQ*/ + 0xef000097, 0xe1a0e00f, 0xe89b8800, 0xef000087, /*FIQ*/ + 0xef000098, 0xe1a0e00f, 0xe89b8800, 0xef000088, /*Error*/ + 0xe1a0f00e /* default handler */ +}; + +/***************************************************************************\ +* Time for the Operating System to initialise itself. * +\***************************************************************************/ + +unsigned ARMul_OSInit(ARMul_State *state) +{ +#ifndef NOOS +#ifndef VALIDATE + ARMword instr, i , j ; + struct OSblock* OSptr = (struct OSblock*)state->OSptr; + + if (state->OSptr == NULL) { + state->OSptr = (unsigned char *)malloc(sizeof(struct OSblock)); + if (state->OSptr == NULL) { + perror("OS Memory"); + exit(15); + } + } + OSptr = (struct OSblock*)state->OSptr; + OSptr->ErrorP = 0; + state->Reg[13] = ADDRSUPERSTACK; /* set up a stack for the current mode */ + ARMul_SetReg(state,(unsigned)SVC32MODE,13,ADDRSUPERSTACK); /* and for supervisor mode */ + ARMul_SetReg(state,(unsigned)ABORT32MODE,13,ADDRABORTSTACK); /* and for abort 32 mode */ + ARMul_SetReg(state,(unsigned)UNDEF32MODE,13,ADDRUNDEFSTACK); /* and for undef 32 mode */ + ARMul_SetReg(state,(unsigned)IRQ32MODE,13,ADDRIRQSTACK); /* and for IRQ 32 mode */ + ARMul_SetReg(state,(unsigned)FIQ32MODE,13,ADDRFIQSTACK); /* and for FIQ 32 mode */ + instr = 0xe59ff000 | (ADDRSOFTVECTORS - 8); /* load pc from soft vector */ + for (i = ARMul_ResetV ; i <= ARMFIQV ; i += 4) + ARMul_WriteWord(state, i, instr); /* write hardware vectors */ + for (i = ARMul_ResetV ; i <= ARMFIQV + 4 ; i += 4) { + ARMul_WriteWord(state, ADDRSOFTVECTORS + i, SOFTVECTORCODE + i * 4); + ARMul_WriteWord(state, ADDRSOFHANDLERS + 2*i + 4L, SOFTVECTORCODE + sizeof(softvectorcode) - 4L); + } + for (i = 0 ; i < sizeof(softvectorcode) ; i += 4) + ARMul_WriteWord(state, SOFTVECTORCODE + i, softvectorcode[i/4]); + for (i = 0 ; i < FOPEN_MAX ; i++) + OSptr->FileTable[i] = NULL ; + for (i = 0 ; i < UNIQUETEMPS ; i++) + OSptr->tempnames[i] = NULL ; + ARMul_ConsolePrint(state, ", soft DEMON vsn 1.3") ; + +#ifndef NOFPE + if (state->fpe) /* install fpe (conditionally) */ + { ARMword addr = fpe.hdr.imagebase; + fpedesc.base = addr; + fpedesc.regs = 0; + if (addr + sizeof(fpe.code) > FPEEND) + ARMul_ConsolePrint(state, ", FPE too big to load"); + else { + for (i = 0 ; i < sizeof(fpe.code) - 4; i += 4) /* copy the code */ + ARMul_WriteWord(state, addr + i, fpe.code[i >> 2]) ; + i = (sizeof(fpe.code) >> 2); + + while ((j = fpe.code[--i]) != 0xffffffff) + { + if (state->bigendSig && j < 0x80000000) { + /* it's part of the string so swap it */ + j = ((j >> 0x18) & 0x000000ff) | + ((j >> 0x08) & 0x0000ff00) | + ((j << 0x08) & 0x00ff0000) | + ((j << 0x18) & 0xff000000) ; + ARMul_WriteWord(state, addr + (i<<2), j) ; + } + } + + fpedesc.regs = fpe.code[--i]; + fpedesc.version = (int)fpe.code[--i]; + + if (fpedesc.version > 1) + { /* reverse FPE/FPASC byte tables for versions > 1 */ + ARMword start, end; /* region to be reversed */ + while ((end = fpe.code[--i]) != 0xffffffff) + { + start = fpe.code[--i]; + + if (state->bigendSig) + for (j = start; j < end; j += 4) + { + ARMword t = ARMul_ReadWord(state, j); + t = ((t >> 0x18) & 0x000000ff) | + ((t >> 0x08) & 0x0000ff00) | + ((t << 0x08) & 0x00ff0000) | + ((t << 0x18) & 0xff000000); + ARMul_WriteWord(state, j, t); + } + } + } + ARMul_ConsolePrint(state, ", FPE") ; + ARMul_SetPC(state, fpe.hdr.imagebase + fpe.hdr.entry_br); + state->EndCondition = 0; + ARMul_DoProg(state); + if (state->EndCondition != 0) { + ARMul_ConsolePrint(state, " initialisation failed"); + fpedesc.regs = 0; + } + } + } +#endif /* NOFPE */ + +#endif /* VALIDATE */ +#endif /* NOOS */ + + return(TRUE) ; +} + +void ARMul_OSExit(ARMul_State *state) +{ + free((char *)state->OSptr) ; +} + + +/***************************************************************************\ +* Return the last Operating System Error. * +\***************************************************************************/ + +ARMword ARMul_OSLastErrorP(ARMul_State *state) +{ + return ((struct OSblock *)state->OSptr)->ErrorP; +} + +/***************************************************************************\ +* The emulator calls this routine when a SWI instruction is encuntered. The * +* parameter passed is the SWI number (lower 24 bits of the instruction). * +\***************************************************************************/ + +unsigned ARMul_OSHandleSWI(ARMul_State *state,ARMword number) +{ +#ifdef NOOS + return(FALSE) ; +#else +#ifdef VALIDATE + switch (number) { + case 0x11 : + state->Emulate = FALSE ; + return(TRUE) ; + case 0x01 : + if (ARM32BITMODE) /* Stay in entry (ARM/THUMB) state */ + ARMul_SetCPSR(state, (ARMul_GetCPSR(state) & 0xffffffe0) | 0x13) ; + else + ARMul_SetCPSR(state, (ARMul_GetCPSR(state) & 0xffffffc0) | 0x3) ; + return(TRUE) ; + default : + return(FALSE) ; + } +#else + ARMword addr, temp ; + char buffer[BUFFERSIZE], *cptr ; + FILE *fptr ; + struct OSblock* OSptr = (struct OSblock*)state->OSptr ; + + switch (number) { + case SWI_WriteC : + state->hostif->writec(state->hostif->hostosarg,(int)state->Reg[0]); + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_Write0 : + addr = state->Reg[0] ; + while ((temp = ARMul_ReadByte(state,addr++)) != 0) + state->hostif->writec(state->hostif->hostosarg,(char)temp); + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_ReadC : + state->Reg[0] = (ARMword)state->hostif->readc(state->hostif->hostosarg) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_CLI : + addr = state->Reg[0] ; + getstring(state,state->Reg[0],buffer) ; + state->Reg[0] = (ARMword)system(buffer) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_GetEnv : + state->Reg[0] = ADDRCMDLINE ; + if (state->MemSize) + state->Reg[1] = state->MemSize ; + else + state->Reg[1] = ADDRUSERSTACK ; + + addr = state->Reg[0] ; + cptr = state->CommandLine ; + if (cptr == NULL) + cptr = "\0" ; + do { + temp = (ARMword)*cptr++ ; + ARMul_WriteByte(state,addr++,temp) ; + } while (temp != 0) ; + return(TRUE) ; + + case SWI_Exit : + state->Emulate = FALSE ; + return(TRUE) ; + + case SWI_EnterOS : + if (ARM32BITMODE) /* Stay in entry (ARM/THUMB) state */ + ARMul_SetCPSR(state, (ARMul_GetCPSR(state) & 0xffffffe0) | 0x13) ; + else + ARMul_SetCPSR(state, (ARMul_GetCPSR(state) & 0xffffffc0) | 0x3) ; + return(TRUE) ; + + case SWI_GetErrno : + state->Reg[0] = OSptr->ErrorNo ; + return(TRUE) ; + + case SWI_Clock : { + /* return muber of centi-seconds... */ + /* Only use the simulated clock if memory speed & cpu speed specified */ + /* This should be in the memory model, called via. ARMul_ReadClock() */ + if (state->MemInfoPtr != NULL && state->cpu_ns != 0) { + MemDescr *m; + unsigned long ns = state->ns, + s = state->s; + for (m = state->MemInfoPtr; m != NULL; m = m->next) { + ns += m->a.ns; + if (ns >= 1000000000) s++, ns -= 1000000000; + s += m->a.s; + } + state->Reg[0] = s * 100 + ns / 10000000; + } else { + state->Reg[0] = +#ifdef CLOCKS_PER_SEC + (CLOCKS_PER_SEC >= 100) + ? (ARMword) (clock() / (CLOCKS_PER_SEC / 100)) + : (ARMword) ((clock() * 100) / CLOCKS_PER_SEC) ; +#else + /* presume unix... clock() returns microseconds */ + (ARMword) (clock() / 10000) ; +#endif + OSptr->ErrorNo = errno ; + } + return(TRUE) ; + } + + case SWI_Time : + state->Reg[0] = (ARMword)time(NULL) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_Remove : + getstring(state,state->Reg[0],buffer) ; + state->Reg[0] = remove(buffer) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_Rename : { + char buffer2[BUFFERSIZE] ; + + getstring(state,state->Reg[0],buffer) ; + getstring(state,state->Reg[1],buffer2) ; + state->Reg[0] = rename(buffer,buffer2) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + } + + case SWI_Open : { + static char* fmode[] = {"r","rb","r+","r+b", + "w","wb","w+","w+b", + "a","ab","a+","a+b", + "r","r","r","r"} /* last 4 are illegal */ ; + unsigned type ; + + type = (unsigned)(state->Reg[1] & 15L) ; + getstring(state,state->Reg[0],buffer) ; + if (strcmp(buffer,":tt")==0 && (type == 0 || type == 1)) /* opening tty "r" */ + fptr = stdin ; + else if (strcmp(buffer,":tt")==0 && (type == 4 || type == 5)) /* opening tty "w" */ + fptr = stdout ; + else + fptr = fopen(buffer,fmode[type]) ; + + state->Reg[0] = 0 ; + if (fptr != NULL) { + for (temp = 0 ; temp < FOPEN_MAX ; temp++) + if (OSptr->FileTable[temp] == NULL || + (OSptr->FileTable[temp] == fptr && (OSptr->FileFlags[temp] & 1) == (type & 1))) { + OSptr->FileTable[temp] = fptr ; + OSptr->FileFlags[temp] = type & 1 ; /* preserve the binary bit */ + state->Reg[0] = (ARMword)(temp + 1) ; + break ; + } + if (state->Reg[0] == 0) + OSptr->ErrorNo = EMFILE ; /* too many open files */ + else + OSptr->ErrorNo = errno ; + } + else + OSptr->ErrorNo = errno ; + return(TRUE) ; + } + + case SWI_Close : + temp = state->Reg[0] ; + if (temp == 0 || temp > FOPEN_MAX || OSptr->FileTable[temp - 1] == 0) { + OSptr->ErrorNo = EBADF ; + state->Reg[0] = -1L ; + return(TRUE) ; + } + temp-- ; + fptr = OSptr->FileTable[temp] ; + if (fptr == stdin || fptr == stdout) + state->Reg[0] = 0 ; + else + state->Reg[0] = fclose(fptr) ; + OSptr->FileTable[temp] = NULL ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_Write : { + unsigned size, upto, type ; + char ch ; + + temp = state->Reg[0] ; + if (temp == 0 || temp > FOPEN_MAX || OSptr->FileTable[temp - 1] == 0) { + OSptr->ErrorNo = EBADF ; + state->Reg[0] = -1L ; + return(TRUE) ; + } + temp-- ; + fptr = OSptr->FileTable[temp] ; + type = OSptr->FileFlags[temp] ; + addr = state->Reg[1] ; + size = (unsigned)state->Reg[2] ; + + if (type & READOP) + fseek(fptr,0L,SEEK_CUR) ; + OSptr->FileFlags[temp] = (type & BINARY) | WRITEOP ; ; + while (size > 0) { + if (size >= BUFFERSIZE) + upto = BUFFERSIZE ; + else + upto = size ; + for (cptr = buffer ; (cptr - buffer) < upto ; cptr++) { + ch = (char)ARMul_ReadByte(state,(ARMword)addr++) ; + *cptr = FIXCRLF(type,ch) ; + } + temp = (fptr == stderr || fptr == stdout) + ? state->hostif->write(state->hostif->hostosarg, buffer, upto) + : fwrite(buffer,1,upto,fptr); + if (temp < upto) { + state->Reg[0] = (ARMword)(size - temp) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + } + size -= upto ; + } + state->Reg[0] = 0 ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + } + + case SWI_Read : { + unsigned size, upto, type ; + char ch ; + + temp = state->Reg[0] ; + if (temp == 0 || temp > FOPEN_MAX || OSptr->FileTable[temp - 1] == 0) { + OSptr->ErrorNo = EBADF ; + state->Reg[0] = -1L ; + return(TRUE) ; + } + temp-- ; + fptr = OSptr->FileTable[temp] ; + addr = state->Reg[1] ; + size = (unsigned)state->Reg[2] ; + type = OSptr->FileFlags[temp] ; + + if (type & WRITEOP) + fseek(fptr,0L,SEEK_CUR) ; + OSptr->FileFlags[temp] = (type & BINARY) | READOP ; ; + while (size > 0) { + if (isatty_(fptr)) { + upto = (size >= BUFFERSIZE)?BUFFERSIZE:size + 1 ; + if (state->hostif->gets(state->hostif->hostosarg, buffer, upto) != 0) + temp = strlen(buffer) ; + else + temp = 0 ; + upto-- ; /* 1 char used for terminating null */ + } + else { + upto = (size>=BUFFERSIZE)?BUFFERSIZE:size ; + temp = fread(buffer,1,upto,fptr) ; + } + for (cptr = buffer ; (cptr - buffer) < temp ; cptr++) { + ch = *cptr ; + ARMul_WriteByte(state,(ARMword)addr++,FIXCRLF(type,ch)) ; + } + if (temp < upto) { + state->Reg[0] = (ARMword)(size - temp) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + } + size -= upto ; + } + state->Reg[0] = 0 ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + } + + case SWI_Seek : + if (state->Reg[0] == 0 || state->Reg[0] > FOPEN_MAX + || OSptr->FileTable[state->Reg[0] - 1] == 0) { + OSptr->ErrorNo = EBADF ; + state->Reg[0] = -1L ; + return(TRUE) ; + } + fptr = OSptr->FileTable[state->Reg[0] - 1] ; + state->Reg[0] = fseek(fptr,(long)state->Reg[1],SEEK_SET) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_Flen : + if (state->Reg[0] == 0 || state->Reg[0] > FOPEN_MAX + || OSptr->FileTable[state->Reg[0] - 1] == 0) { + OSptr->ErrorNo = EBADF ; + state->Reg[0] = -1L ; + return(TRUE) ; + } + fptr = OSptr->FileTable[state->Reg[0] - 1] ; + addr = (ARMword)ftell(fptr) ; + if (fseek(fptr,0L,SEEK_END) < 0) + state->Reg[0] = -1 ; + else { + state->Reg[0] = (ARMword)ftell(fptr) ; + (void)fseek(fptr,addr,SEEK_SET) ; + } + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_IsTTY : + if (state->Reg[0] == 0 || state->Reg[0] > FOPEN_MAX + || OSptr->FileTable[state->Reg[0] - 1] == 0) { + OSptr->ErrorNo = EBADF ; + state->Reg[0] = -1L ; + return(TRUE) ; + } + fptr = OSptr->FileTable[state->Reg[0] - 1] ; + state->Reg[0] = isatty_(fptr) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + + case SWI_TmpNam :{ + ARMword size ; + + addr = state->Reg[0] ; + temp = state->Reg[1] & 0xff ; + size = state->Reg[2] ; + if (OSptr->tempnames[temp] == NULL) { + if ((OSptr->tempnames[temp] = (char *)malloc(L_tmpnam)) == NULL) { + state->Reg[0] = 0 ; + return(TRUE) ; + } + (void)tmpnam(OSptr->tempnames[temp]) ; + } + cptr = OSptr->tempnames[temp] ; + if (strlen(cptr) > state->Reg[2]) + state->Reg[0] = 0 ; + else + do { + ARMul_WriteByte(state,addr++,*cptr) ; + } while (*cptr++ != 0) ; + OSptr->ErrorNo = errno ; + return(TRUE) ; + } + + case SWI_InstallHandler: + { ARMword handlerp = ADDRSOFHANDLERS + state->Reg[0] * 8; + ARMword oldr1 = ARMul_ReadWord(state, handlerp), + oldr2 = ARMul_ReadWord(state, handlerp + 4); + ARMul_WriteWord(state, handlerp, state->Reg[1]); + ARMul_WriteWord(state, handlerp + 4, state->Reg[2]); + state->Reg[1] = oldr1; + state->Reg[2] = oldr2; + return(TRUE); + } + + case SWI_GenerateError: + ARMul_Abort(state, ARMSWIV) ; + if (state->Emulate) + ARMul_SetR15(state, ARMul_ReadWord(state, ADDRSOFTVECTORS + ARMErrorV)); + return(TRUE); + +/* SWI's 0x9x unwind the state of the CPU after an abort of type x */ + + case 0x90: /* Branch through zero */ + { ARMword oldpsr = ARMul_GetCPSR(state) ; + ARMul_SetCPSR(state, (oldpsr & 0xffffffc0) | 0x13) ; + ARMul_SetSPSR(state, SVC32MODE, oldpsr) ; + state->Reg[14] = 0; + goto TidyCommon; + } + + case 0x98: /* Error */ + { ARMword errorp = state->Reg[0], + regp = state->Reg[1]; + unsigned i; + ARMword errorpsr = ARMul_ReadWord(state, regp + 16*4); + for (i = 0; i < 15; i++) + ARMul_SetReg(state,(unsigned)errorpsr,i,ARMul_ReadWord(state, regp + i*4L)) ; + state->Reg[14] = ARMul_ReadWord(state, regp + 15*4L); + state->Reg[10] = errorp; + ARMul_SetSPSR(state,state->Mode,errorpsr) ; + OSptr->ErrorP = errorp; + goto TidyCommon; + } + + case 0x94: /* Data abort */ + { ARMword addr = state->Reg[14] - OLDINSTRUCTIONSIZE * 2; + ARMword cpsr = ARMul_GetCPSR(state) ; + if (ARM26BITMODE) + addr = addr & 0x3fffffc ; + ARMul_SetCPSR(state,ARMul_GetSPSR(state,cpsr)) ; + UnwindDataAbort(state, addr, CPSRINSTRUCTIONSET(ARMul_GetSPSR(state,cpsr))); +#ifndef NOFPE + if (addr >= fpedesc.base && addr < FPEEND) { /* in the FPE */ + ARMword regdump; + if (fpedesc.version == 0) { + /* fpe340. user's registers are the only things on the fpe's stack */ + ARMword sp = state->Reg[13] ; + state->Reg[13] += 64 ; /* fix the aborting mode sp */ + regdump = sp; + } else { + /* new fpe. r12 addresses a frame on the fpe's stack, immediately + above which are dumped the user's registers. The saved pc is for + the instruction after the one causing the fault. + */ + ARMword fp = state->Reg[12]; + state->Reg[13] = fp + 64; /* reset the fpe's stack */ + regdump = fp; + } + state->Reg[14] = ARMul_ReadWord(state,regdump + 15*4) ; /* and its lr */ + { ARMword spsr = ARMul_GetSPSR(state,state->Mode); + int i; + ARMul_SetCPSR(state,spsr) ; + for (i = 0 ; i < 15 ; i++) + ARMul_SetReg(state,(unsigned)spsr,i,ARMul_ReadWord(state,regdump + (ARMword)i*4)); + ARMul_SetCPSR(state,cpsr) ; + state->Reg[14] = ARMul_ReadWord(state,regdump + 15*4) + INSTRUCTION32SIZE ; /* botch it */ + ARMul_SetSPSR(state,state->Mode,spsr) ; + } + } else +#endif + ARMul_SetCPSR(state,cpsr) ; + + /* and fall through to correct r14 */ + } + case 0x95: /* Address Exception */ + state->Reg[14] -= OLDINSTRUCTIONSIZE; + case 0x91: /* Undefined instruction */ + case 0x92: /* SWI */ + case 0x93: /* Prefetch abort */ + case 0x96: /* IRQ */ + case 0x97: /* FIQ */ + state->Reg[14] -= OLDINSTRUCTIONSIZE; + TidyCommon: + if (state->VectorCatch & (1 << (number - 0x90))) { + ARMul_SetR15(state, state->Reg[14] + OLDINSTRUCTIONSIZE * 2) ; /* the pipelining the the RDI will undo */ + ARMul_SetCPSR(state,ARMul_GetSPSR(state,ARMul_GetCPSR(state))) ; + if (number == 0x90) + state->EndCondition = 10 ; /* Branch through Zero Error */ + else + state->EndCondition = (unsigned)number - 0x8f; + state->Emulate = FALSE ; + } + else { + ARMword sp = state->Reg[13]; + ARMul_WriteWord(state, sp - 4, state->Reg[14]); + ARMul_WriteWord(state, sp - 8, state->Reg[12]); + ARMul_WriteWord(state, sp - 12, state->Reg[11]); + ARMul_WriteWord(state, sp - 16, state->Reg[10]); + state->Reg[13] = sp - 16; + state->Reg[11] = ADDRSOFHANDLERS + 8 * (number - 0x90); + } + return(TRUE); + +/* SWI's 0x8x pass an abort of type x to the debugger if a handler returns */ + + case 0x80: case 0x81: case 0x82: case 0x83: + case 0x84: case 0x85: case 0x86: case 0x87: case 0x88: + { ARMword sp = state->Reg[13]; + state->Reg[10] = ARMul_ReadWord(state, sp); + state->Reg[11] = ARMul_ReadWord(state, sp + 4); + state->Reg[12] = ARMul_ReadWord(state, sp + 8); + state->Reg[14] = ARMul_ReadWord(state, sp + 12); + state->Reg[13] = sp + 16; + ARMul_SetR15(state, state->Reg[14] + OLDINSTRUCTIONSIZE * 2) ; /* the pipelining the the RDI will undo */ + ARMul_SetCPSR(state,ARMul_GetSPSR(state,ARMul_GetCPSR(state))) ; + if (number == 0x80) + state->EndCondition = 10 ; /* Branch through Zero Error */ + else + state->EndCondition = (unsigned)number - 0x7f; + state->Emulate = FALSE ; + return(TRUE); + } + + default : + return(FALSE) ; + } +#endif +#endif + } + +/***************************************************************************\ +* The emulator calls this routine when an Exception occurs. The second * +* parameter is the address of the relevant exception vector. Returning * +* FALSE from this routine causes the trap to be taken, TRUE causes it to * +* be ignored (so set state->Emulate to FALSE!). * +\***************************************************************************/ + +unsigned ARMul_OSException(ARMul_State *state, ARMword vector, ARMword pc) +{ /* don't use this here */ + return(FALSE) ; +} + +#ifndef NOOS + +/***************************************************************************\ +* Unwind a data abort * +\***************************************************************************/ + +static void UnwindDataAbort(ARMul_State *state, ARMword addr, ARMword iset) +{ +#ifdef CODE16 + if (iset == INSTRUCTION16) { + ARMword instr = ARMul_ReadWord(state, addr); + ARMword offset; + unsigned long regs; + if (state->bigendSig ^ ((addr & 2) == 2)) /* get instruction into low 16 bits */ + instr = instr >> 16; + switch (BITS(11,15)) { + case 0x16: + case 0x17: + if (BITS(9,10) == 2) { /* push/pop */ + regs = BITS(0, 8); + offset = 0; + for (; regs != 0; offset++) + regs ^= (regs & -regs); + if (BIT(11)) + state->Reg[13] -= offset * 4; /* pop */ + else + state->Reg[13] += offset * 4; /* push */ + } + break; + case 0x18: + case 0x19: + regs = BITS(0,7); + offset = 0; + for (; regs != 0; offset++) + regs ^= (regs & -regs); + if (BITS(11,15) == 0x19) { /* ldmia rb! */ + state->Reg[BITS(8,10)] -= offset * 4; + } else { /* stmia rb! */ + state->Reg[BITS(8,10)] += offset * 4; + } + break; + default: + break; + } + } else { +#endif + ARMword instr = ARMul_ReadWord(state, addr); + ARMword rn = BITS(16, 19); + ARMword itype = BITS(24, 27); + ARMword offset; + if (rn == 15) return; + if (itype == 8 || itype == 9) { + /* LDM or STM */ + unsigned long regs = BITS(0, 15); + offset = 0; + if (!BIT(21)) return; /* no wb */ + for (; regs != 0; offset++) + regs ^= (regs & -regs); + if (offset == 0) offset = 16; + } else if (itype == 12 || /* post-indexed CPDT */ + (itype == 13 && BIT(21))) { /* pre_indexed CPDT with WB */ + offset = BITS(0, 7); + } else + return; + + if (BIT(23)) + state->Reg[rn] -= offset * 4; + else + state->Reg[rn] += offset * 4; +#ifdef CODE16 + } +#endif +} + +/***************************************************************************\ +* Copy a string from the debuggee's memory to the host's * +\***************************************************************************/ + +static void getstring(ARMul_State *state, ARMword from, char *to) +{do { + *to = (char)ARMul_ReadByte(state,from++) ; + } while (*to++ != '\0') ; + } + +#endif /* NOOS */ + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.H new file mode 100644 index 0000000..d9508f5 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMOS.H @@ -0,0 +1,64 @@ +/***************************************************************************\ +* armos.h * +* Version 1.20 * +* ARMulator II Operating System Definitions. * +* Copyright (C) 1991 Advanced RISC Machines Limited. All rights reserved. * +* Written by Dave Jaggar. * +* Project started on 1st July 1991. * +* Last change was Friday 10th July 1992. * +\***************************************************************************/ + + +/***************************************************************************\ +* Define the initial layout of memory * +\***************************************************************************/ + +#define ADDRSUPERSTACK 0xA00L /* supervisor stack space */ +#define ADDRABORTSTACK 0x800L /* abort stack space */ +#define ADDRUNDEFSTACK 0x700L /* undef stack space */ +#define ADDRIRQSTACK 0x500L /* IRQ stack space */ +#define ADDRFIQSTACK 0x400L /* FIQ stack space */ +#define ADDRUSERSTACK 0x80000L /* default user stack start */ +#define ADDRSOFTVECTORS 0xA40L /* soft vectors are here */ +#define ADDRCMDLINE 0xf00L /* command line is here after a SWI GetEnv */ +#define ADDRSOFHANDLERS 0xad0L /* address and workspace for installed handlers */ +#define SOFTVECTORCODE 0xb80L /* default handlers */ + +/***************************************************************************\ +* SWI numbers * +\***************************************************************************/ + +#define SWI_WriteC 0x0 +#define SWI_Write0 0x2 +#define SWI_ReadC 0x4 +#define SWI_CLI 0x5 +#define SWI_GetEnv 0x10 +#define SWI_Exit 0x11 +#define SWI_EnterOS 0x16 + +#define SWI_GetErrno 0x60 +#define SWI_Clock 0x61 +#define SWI_Time 0x63 +#define SWI_Remove 0x64 +#define SWI_Rename 0x65 +#define SWI_Open 0x66 + +#define SWI_Close 0x68 +#define SWI_Write 0x69 +#define SWI_Read 0x6a +#define SWI_Seek 0x6b +#define SWI_Flen 0x6c + +#define SWI_IsTTY 0x6e +#define SWI_TmpNam 0x6f +#define SWI_InstallHandler 0x70 +#define SWI_GenerateError 0x71 + +#define FPEEND 0x8000L + +extern struct fpedesc { + ARMword base; + ARMword regs; + int version; +} fpedesc; + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMPROTO.C b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMPROTO.C new file mode 100644 index 0000000..5d7ec12 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMPROTO.C @@ -0,0 +1,512 @@ +/***************************************************************************\ +* armproto.c * +* Version 1.20 * +* ARMulator II Fast Prototype Memory Interface. * +* Copyright (C) 1991 Advanced RISC Machines Limited. All rights reserved. * +* Written by Dave Jaggar. * +* Project started on 1st July 1991. * +\***************************************************************************/ + +/* + * RCS $Revision: 1.12 $ + * Checkin $Date: 1995/01/18 12:27:02 $ + * Revising $Author: hmeekings $ + */ + +/* This file contains the ARMulator interface to the memory model +designed for fast prototyping. This model is also the closest to the +real ARM memory interface. Two routines must be written to build a +memory interface, ARMul_MemoryInit and ARMul_MemoryAccess. An example +memory interface is implemented, with 64K pages, allocated on demand +from a 64K entry page table. The routines PutWord and GetWord implement +this, lifted from armvirt.c, the virtual memory model. Pages are never +freed as they might be needed again. A single area of memory may be +defined to generate aborts. */ + +#include "armdefs.h" + +#ifdef VALIDATE /* for running the validate suite */ +#define TUBE 48 * 1024 * 1024 /* write a char on the screen */ +#define ABORTS +#endif + +#ifdef ABORTS /* the memory system will abort */ +/* For the old test suite Abort between 32 Kbytes and 32 Mbytes + For the new test suite Abort between 8 Mbytes and 26 Mbytes */ +/* #define LOWABORT 32 * 1024 + #define HIGHABORT 32 * 1024 * 1024 */ +#define LOWABORT 8 * 1024 * 1024 +#define HIGHABORT 26 * 1024 * 1024 +#endif + +/* #define TRACEBUS */ + +#define NUMPAGES 64 * 1024 +#define PAGESIZE 64 * 1024 +#define PAGEBITS 16 +#define OFFSETBITS 0xffff + +static ARMword GetWord(ARMul_State *state,ARMword address) ; +static void PutWord(ARMul_State *state,ARMword address, ARMword word) ; + +/***************************************************************************\ +* Initialise the memory interface * +\***************************************************************************/ + +unsigned ARMul_MemoryInit(ARMul_State *state, unsigned long initmemsize) +{ARMword **pagetable ; + unsigned page ; + + state->MemSize = initmemsize ; + pagetable = (ARMword **)malloc(sizeof(ARMword)*NUMPAGES) ; + if (pagetable == NULL) + return(FALSE) ; + for (page = 0 ; page < NUMPAGES ; page++) + *(pagetable + page) = NULL ; + state->MemDataPtr = (unsigned char *)pagetable ; +#ifdef BIGEND + state->bigendSig = HIGH ; +#endif +#ifdef LITTLEEND + state->bigendSig = LOW ; +#endif + ARMul_ConsolePrint(state, ", 4 Gb memory") ; + return(TRUE) ; +} + +/***************************************************************************\ +* Remove the memory interface * +\***************************************************************************/ + +void ARMul_MemoryExit(ARMul_State *state) +{ARMword page ; + ARMword **pagetable ; + ARMword *pageptr ; + + pagetable = (ARMword **)state->MemDataPtr ; + for (page = 0 ; page < NUMPAGES ; page++) { + pageptr = *(pagetable + page) ; + if (pageptr != NULL) + free((char *)pageptr) ; + } + free((char *)pagetable) ; + return ; + } + +/***************************************************************************\ +* Generic memory interface. Just alter this for a prototype memory system. * +\***************************************************************************/ + +ARMword ARMul_MemAccess(ARMul_State *state, + ARMword address, + ARMword dataOut, + ARMword mas1, + ARMword mas0, + ARMword rw, + ARMword seq, + ARMword mreq, + ARMword opc, + ARMword lock, + ARMword trans, + ARMword account) +{ARMword dataIn = 0 ; + +#ifdef TRACEBUS + ARMul_DebugPrint(state, "A=%08x, M=%01x, S=%01x, O=%01x\n", + address,mreq,seq,opc) ; +#endif + + ARMul_CLEARABORT ; + if (mreq == LOW) { /* memory request */ + if (account == TRUE) { /* a "real" memory access */ + if (seq == LOW) /* non-sequential (N) cycle */ + state->NumNcycles++ ; + else + state->NumScycles++ ; + } +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + if (opc == LOW) { /* opcode fetch */ + ARMul_PREFETCHABORT(address) ; + } + else { /* data access */ + ARMul_DATAABORT(address) ; + } +#ifdef TRACEBUS + ARMul_DebugPrint(state, "ABORT\n") ; +#endif + return(ARMul_ABORTWORD) ; + } /* abort */ +#endif + if (rw == LOW) { /* read */ + /* it's always a word, bytes and halfwords are extracted by ARM */ + dataIn = GetWord(state,address) ; + } /* read */ + else { /* write */ + if (mas0 == LOW) { /* byte or word */ + if (mas1 == LOW) { /* byte */ + ARMword word, offset ; + +#ifdef VALIDATE + if (address == TUBE) { + if (dataOut == 4) + state->Emulate = FALSE ; + else + (void)putc((char)dataOut,stderr) ; /* Write Char */ + return(0) ; + } +#endif + word = GetWord(state,address) ; + offset = (((ARMword)state->bigendSig * 3) ^ (address & 3)) << 3 ; /* bit offset into the word */ + PutWord(state,address,(word & ~(0xffL << offset)) | ((dataOut & 0xffL) << offset)) ; + } + else { /* write word */ + PutWord(state,address,dataOut) ; + } + } /* byte or word */ + else { /* halfword or reserved */ + if (mas1 == LOW) { /* halfword */ + ARMword word, offset ; + word = GetWord(state,address) ; + offset = (((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3 ; /* bit offset into the word */ + PutWord(state,address,(word & ~(0xffffL << offset)) | ((dataOut & 0xffffL) << offset)) ; + } else { /* reserved */ + ARMul_ConsolePrint(state, "Reserved memory access\n") ; + } + } /* halfword or reserved */ + } /* write */ + } /* memory request */ + else { /* not a memory request */ + if (seq == LOW) /* internal (I) cycle */ + state->NumIcycles++ ; + else /* co-processor (C) cycle */ + state->NumCcycles++ ; + } + return(dataIn) ; + } + +/***************************************************************************\ +* Get a Word from Virtual Memory, maybe allocating the page * +\***************************************************************************/ + +static ARMword GetWord(ARMul_State *state, ARMword address) +{ARMword page, offset ; + ARMword **pagetable ; + ARMword *pageptr ; + + page = address >> PAGEBITS ; + offset = (address & OFFSETBITS) >> 2 ; + pagetable = (ARMword **)state->MemDataPtr ; + pageptr = *(pagetable + page) ; + + if (pageptr == NULL) { + pageptr = (ARMword *)malloc(PAGESIZE) ; + if (pageptr == NULL) { + perror("ARMulator can't allocate VM page") ; + exit(12) ; + } + *(pagetable + page) = pageptr ; + } + + return(*(pageptr + offset)) ; + } + +/***************************************************************************\ +* Put a Word into Virtual Memory, maybe allocating the page * +\***************************************************************************/ + +static void PutWord(ARMul_State *state, ARMword address, ARMword data) +{ARMword page, offset ; + ARMword **pagetable ; + ARMword *pageptr ; + + page = address >> PAGEBITS ; + offset = (address & OFFSETBITS) >> 2 ; + pagetable = (ARMword **)state->MemDataPtr ; + pageptr = *(pagetable + page) ; + + if (pageptr == NULL) { + pageptr = (ARMword *)malloc(PAGESIZE) ; + if (pageptr == NULL) { + perror("ARMulator can't allocate VM page") ; + exit(13) ; + } + *(pagetable + page) = pageptr ; + } + + *(pageptr + offset) = data ; + } + +/*-------------------------------------------------------------------------*\ +* * +| NOTHING BELOW HERE SHOULD NEED CHANGING | +* * +\*-------------------------------------------------------------------------*/ + + +/***************************************************************************\ +* Load Instruction, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstrS(ARMul_State *state, ARMword address) +{ARMword temp ; + +#ifdef HOURGLASS_RATE + if( ( state->NumScycles & HOURGLASS_RATE ) == 0 ) { + armsd_hourglass(); + } +#endif + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + temp = ARMul_MemAccess(state,address,0L, 1L,0L,0L, 1L,0L, 0L, 0L,1L, 1L) ; + return(temp) ; +} + +/***************************************************************************\ +* Load Instruction, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstrN(ARMul_State *state, ARMword address) +{ARMword temp ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + temp = ARMul_MemAccess(state,address,0L, 1L,0L,0L, 0L,0L, 0L, 0L,1L, 1L) ; + return(temp) ; + } + +/***************************************************************************\ +* Load 16 bit Instruction, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstr16S(ARMul_State *state, ARMword address) +{ARMword temp, offset ; + +#ifdef HOURGLASS_RATE + if( ( state->NumScycles & HOURGLASS_RATE ) == 0 ) { + armsd_hourglass(); + } +#endif + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + temp = ARMul_MemAccess(state,address,0L, 0L,1L,0L, 1L,0L, 0L, 0L,1L, 1L) ; + offset = (((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3 ; /* bit offset into the word */ + return(temp >> offset & 0xffffL) ; +} + +/***************************************************************************\ +* Load 16 bit Instruction, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstr16N(ARMul_State *state, ARMword address) +{ARMword temp, offset ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + temp = ARMul_MemAccess(state,address,0L, 0L,1L,0L, 0L,0L, 0L, 0L,1L, 1L) ; + offset = (((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3 ; /* bit offset into the word */ + return(temp >> offset & 0xffffL) ; + } + +/***************************************************************************\ +* Load Word, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadWordS(ARMul_State *state, ARMword address) +{ARMword temp ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + temp = ARMul_MemAccess(state,address,0L, 1L,0L,0L, 1L,0L, 1L, 0L,1L, 1L) ; + return(temp) ; + } + +/***************************************************************************\ +* Load Word, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadWordN(ARMul_State *state, ARMword address) +{ARMword temp ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + temp = ARMul_MemAccess(state,address,0L, 1L,0L,0L, 0L,0L, 1L, 0L,1L, 1L) ; + return(temp) ; + } + +/***************************************************************************\ +* Load Halfword, (Non Sequential Cycle) * +\***************************************************************************/ + +ARMword ARMul_LoadHalfWord(ARMul_State *state, ARMword address) +{ARMword word, offset ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + word = ARMul_MemAccess(state,address,0L, 0L,1L,0L, 0L,0L, 1L, 0L,1L, 1L) ; + offset = (((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3 ; /* bit offset into the word */ + return(word >> offset & 0xffffL) ; + } + +/***************************************************************************\ +* Load Byte, (Non Sequential Cycle) * +\***************************************************************************/ + +ARMword ARMul_LoadByte(ARMul_State *state, ARMword address) +{ARMword word, offset ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + word = ARMul_MemAccess(state,address,0L, 0L,0L,0L, 0L,0L, 1L, 0L,1L, 1L) ; + offset = (((ARMword)state->bigendSig * 3) ^ (address & 3)) << 3 ; /* bit offset into the word */ + return(word >> offset & 0xffL) ; + } + +/***************************************************************************\ +* Store Word, Sequential Cycle * +\***************************************************************************/ + +void ARMul_StoreWordS(ARMul_State *state, ARMword address, ARMword data) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + (void)ARMul_MemAccess(state,address,data, 1L,0L,1L, 1L,0L, 1L, 0L,1L, 1L) ; +} +/***************************************************************************\ +* Store Word, Sequential Cycle * +\***************************************************************************/ + +void ARMul_StoreWordN(ARMul_State *state, ARMword address, ARMword data) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + (void)ARMul_MemAccess(state,address,data, 1L,0L,1L, 0L,0L, 1L, 0L,1L, 1L) ; +} + +/***************************************************************************\ +* Store Halfword, (Non Sequential Cycle) * +\***************************************************************************/ + +void ARMul_StoreHalfWord(ARMul_State *state, ARMword address, ARMword data) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + (void)ARMul_MemAccess(state,address,data, 0L,1L,1L, 0L,0L, 1L, 0L,1L, 1L) ; + } + +/***************************************************************************\ +* Store Byte, (Non Sequential Cycle) * +\***************************************************************************/ + +void ARMul_StoreByte(ARMul_State *state, ARMword address, ARMword data) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + (void)ARMul_MemAccess(state,address,data, 0L,0L,1L, 0L,0L, 1L, 0L,1L, 1L) ; + } + +/***************************************************************************\ +* Swap Word, (Two Non Sequential Cycles) * +\***************************************************************************/ + +ARMword ARMul_SwapWord(ARMul_State *state, ARMword address, ARMword data) +{ARMword temp ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + temp = ARMul_MemAccess(state,address,0L, 1L,0L,0L, 0L,0L, 1L, 1L,1L, 1L) ; + (void)ARMul_MemAccess(state,address,data, 1L,0L,1L, 0L,0L, 1L, 0L,1L, 1L) ; + return(temp) ; + } + +/***************************************************************************\ +* Swap Byte, (Two Non Sequential Cycles) * +\***************************************************************************/ + +ARMword ARMul_SwapByte(ARMul_State *state, ARMword address, ARMword data) +{ARMword word, offset ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + word = ARMul_MemAccess(state,address,0L, 0L,0L,0L, 0L,0L, 1L, 1L,1L, 1L) ; + (void)ARMul_MemAccess(state,address,data, 0L,0L,1L, 0L,0L, 1L, 0L,1L, 1L) ; + offset = (((ARMword)state->bigendSig * 3) ^ (address & 3)) << 3 ; /* bit offset into the word */ + return(word >> offset & 0xffL) ; + } + +/***************************************************************************\ +* Count I Cycles * +\***************************************************************************/ + +void ARMul_Icycles(ARMul_State *state, unsigned number, ARMword address) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + while (number--) + (void)ARMul_MemAccess(state,address,0L, 0L,0L,0L, 0L,1L, 1L, 0L,1L, 1L) ; + } +/***************************************************************************\ +* Count C Cycles * +\***************************************************************************/ + +void ARMul_Ccycles(ARMul_State *state, unsigned number, ARMword address) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + while (number--) + (void)ARMul_MemAccess(state,address,0L, 0L,0L,0L, 1L,1L, 1L, 0L,1L, 1L) ; + } + +/***************************************************************************\ +* Read Word (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadWord(ARMul_State *state, ARMword address) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + return(ARMul_MemAccess(state,address,0L, 1L,0L,0L, 0L,0L, 1L, 0L,1L, 0L)) ; + } + +/***************************************************************************\ +* Read Halfword (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadHalfWord(ARMul_State *state, ARMword address) +{ARMword word, offset ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + word = ARMul_MemAccess(state,address,0L, 0L,1L,0L, 0L,0L, 1L, 0L,1L, 0L) ; + offset = (((ARMword)state->bigendSig * 2) ^ (address & 2)) << 3 ; /* bit offset into the word */ + return(word >> offset & 0xffffL) ; + } + +/***************************************************************************\ +* Read Byte (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadByte(ARMul_State *state, ARMword address) +{ARMword word, offset ; + + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + word = ARMul_MemAccess(state,address,0L, 0L,0L,0L, 0L,0L, 1L, 0L,1L, 0L) ; + offset = (((ARMword)state->bigendSig * 3) ^ (address & 3)) << 3 ; /* bit offset into the word */ + return(word >> offset & 0xffL) ; + } + +/***************************************************************************\ +* Write Word (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteWord(ARMul_State *state, ARMword address, ARMword data) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + (void)ARMul_MemAccess(state,address,data, 1L,0L,1L, 0L,0L, 1L, 0L,1L, 0L) ; +} + +/***************************************************************************\ +* Write HalfWord (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteHalfWord(ARMul_State *state, ARMword address, ARMword data) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + (void)ARMul_MemAccess(state,address,data, 0L,1L,1L, 0L,0L, 1L, 0L,1L, 0L) ; + } + +/***************************************************************************\ +* Write Byte (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteByte(ARMul_State *state, ARMword address, ARMword data) +{ + /* address, data, mas1, mas0, rw, seq, mreq, opc, lock, trans, account */ + (void)ARMul_MemAccess(state,address,data, 0L,0L,1L, 0L,0L, 1L, 0L,1L, 0L) ; + } + + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULATE.DEF b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULATE.DEF new file mode 100644 index 0000000..5ad1432 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULATE.DEF @@ -0,0 +1,28 @@ +; RCS $Revision: 1.2.2.1 $ +; Checkin $Date: 1996/02/07 15:50:34 $ +; Revising $Author: jporter $ +; + +LIBRARY ARMULATE + +CODE LOADONCALL DISCARDABLE +DATA LOADONCALL SINGLE + +EXPORTS + ARMul_RDI_open @1 + ARMul_RDI_close @2 + ARMul_RDI_read @3 + ARMul_RDI_write @4 + ARMul_RDI_CPUread @5 + ARMul_RDI_CPUwrite @6 + ARMul_RDI_CPread @7 + ARMul_RDI_CPwrite @8 + ARMul_RDI_setbreak @9 + ARMul_RDI_clearbreak @10 + ARMul_RDI_setwatch @11 + ARMul_RDI_clearwatch @12 + ARMul_RDI_execute @13 + ARMul_RDI_step @14 + ARMul_RDI_info @15 + ARMul_RDI_cpunames @16 + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.C b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.C new file mode 100644 index 0000000..64305af --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.C @@ -0,0 +1,122 @@ +/***************************************************************************\ +* armuldll.c * +* Copyright (C) 1995 Advanced RISC Machines Limited. All rights reserved. * +\***************************************************************************/ + +/* + * RCS $Revision: 1.1.2.1 $ + * Checkin $Date: 1996/02/07 15:50:38 $ + * Revising $Author: jporter $ + */ + +#include +#include +#include "armuldll.h" + +UINT AbortRead; + +BOOL WINAPI DllMain (HANDLE hDLL, DWORD dwReason, LPVOID lpReserved) +{ + switch (dwReason) + { + case DLL_PROCESS_ATTACH: + { + AbortRead = RegisterWindowMessage("ABORT_READ"); +#ifdef _DEBUG + char buf[BUFSIZE+1]; + // + // DLL is attaching to the address space of the current process. + // + + ghMod = hDLL; + GetModuleFileName (NULL, (LPTSTR) buf, BUFSIZE); + MessageBox ( GetFocus(), + (LPCTSTR) buf, + (LPCTSTR) "ARMulator DLL: Process attaching", + MB_OK | MB_SYSTEMMODAL); +#endif + break; + } + + case DLL_THREAD_ATTACH: + { +#ifdef _DEBUG + + // + // A new thread is being created in the current process. + // + + MessageBox ( GetFocus(), + (LPCTSTR) "ARMulator DLL: Thread attaching", + (LPCTSTR) "", + MB_OK | MB_SYSTEMMODAL); +#endif + break; + } + case DLL_THREAD_DETACH: + { +#ifdef _DEBUG + + // + // A thread is exiting cleanly. + // + + MessageBox ( GetFocus(), + (LPCTSTR) "ARMulator DLL: Thread detaching", + (LPCTSTR) "", + MB_OK | MB_SYSTEMMODAL); +#endif + break; + } + case DLL_PROCESS_DETACH: + { +#ifdef _DEBUG + + // + // The calling process is detaching the DLL from its address space. + // + MessageBox ( GetFocus(), + (LPCTSTR) "ARMulator DLL: Process detaching", + (LPCTSTR) "", + MB_OK | MB_SYSTEMMODAL ); +#endif + break; + } + } + +return TRUE; +} + + +/******************************************************************************\ +* +* FUNCTION: Utils +* +* RETURNS: ARMulator DLL Utility functions (not exported) +* +\******************************************************************************/ + +void YieldControl(int nLoops) +{ + MSG Message; + int loop = 0; + + if (PeekMessage(&Message, NULL, AbortRead,AbortRead, PM_NOREMOVE)) return; + if (PeekMessage(&Message, NULL, WM_CLOSE,WM_CLOSE, PM_NOREMOVE)) return; + while (loop < nLoops) + { + while (PeekMessage(&Message, NULL, 0,0, PM_REMOVE)) + { + TranslateMessage(&Message); + DispatchMessage(&Message); + } + loop++; + } +} + +void armsd_hourglass(void) +{ + YieldControl(1); // This could be Selected By Options +} + + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.H new file mode 100644 index 0000000..3c6379a --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMULDLL.H @@ -0,0 +1,62 @@ +/***************************************************************************\ +* armuldll.h * +* Copyright (C) 1995 Advanced RISC Machines Limited. All rights reserved. * +\***************************************************************************/ + +/* + * RCS $Revision: 1.1.2.1 $ + * Checkin $Date: 1996/02/07 15:50:39 $ + * Revising $Author: jporter $ + */ + +#define BUFSIZE 80 +#include +#include "armdbg.h" +#include "dbg_rdi.h" + +#ifdef __WATCOMC__ + #define DLL_EXPORT __export +#elif _MSC_VER + #define DLL_EXPORT _declspec(dllexport) +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif +/******************************************************************************\ +* GLOBAL VARIABLES +\******************************************************************************/ +HANDLE ghMod; + +/******************************************************************************\ +* FUNCTION PROTOTYPES +\******************************************************************************/ + +//RDIProcVec *ARMul_DLL_GetRDI(); +RDI_NameList const *ARMul_RDI_cpunames(void); +INT ARMul_RDI_open(unsigned type, const Dbg_ConfigBlock *config, + const Dbg_HostosInterface *hostif, + struct Dbg_MCState *dbg_state); + +INT ARMul_RDI_close(void); +INT ARMul_RDI_read(ARMword source, void *dest, unsigned *nbytes); +INT ARMul_RDI_write(const void *source, ARMword dest, unsigned *nbytes); +INT ARMul_RDI_CPUread(unsigned mode, unsigned long mask, ARMword *buffer); +INT ARMul_RDI_CPUwrite(unsigned mode, unsigned long mask, ARMword const *buffer); +INT ARMul_RDI_CPread(unsigned CPnum, unsigned long mask, ARMword *buffer); +INT ARMul_RDI_CPwrite(unsigned CPnum, unsigned long mask, ARMword const *buffer); +INT ARMul_RDI_setbreak(ARMword address, unsigned type, ARMword bound, + PointHandle *handle); +INT ARMul_RDI_clearbreak(PointHandle handle); +INT ARMul_RDI_setwatch(ARMword address, unsigned type, unsigned datatype, + ARMword bound, PointHandle *handle); +INT ARMul_RDI_clearwatch(PointHandle handle); +INT ARMul_RDI_execute(PointHandle *handle); +INT ARMul_RDI_step(unsigned ninstr, PointHandle *handle); +INT ARMul_RDI_info(unsigned type, ARMword *arg1, ARMword *arg2); + +#ifdef __cplusplus +} +#endif + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMVIRT.C b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMVIRT.C new file mode 100644 index 0000000..70ec5d0 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/ARMVIRT.C @@ -0,0 +1,871 @@ +/*************************************************************************** + * armvirt.c + * ARMulator II virtual memory interface. + * Copyright (C) 1991 Advanced RISC Machines Limited. All rights reserved. + ***************************************************************************/ + +/* + * RCS $Revision: 1.19.2.4 $ + * Checkin $Date: 1995/08/31 09:36:54 $ + * Revising $Author: plg $ + */ + +/* This file contains a complete ARMulator memory model, modelling a +"virtual memory" system. A much simpler model can be found in +armfast.c, and that model goes faster too, but has a fixed amount of +memory. This model's memory has 64K pages, allocated on demand from a +64K entry page table, when the page is first written. Reads to an +unwritten (un-allocated) page are serviced by an access to a dummy page. +Pages are never freed as they might be needed again. A single area of +memory can be defined to generate aborts. */ + +#include "armdefs.h" + +/* The following hack, if defined, uses the F counter to count 32 bit + word accesses. This is useful when pretending to have 16 bit wide memory. + */ +/* #define RUN_IN_16_BIT_MEMORY_HACK */ + + +#ifdef VALIDATE /* for running the validate suite */ +#define TUBE 48 * 1024 * 1024 /* write a char on the screen */ +#define ABORTS 1 +#endif + +#ifdef ABORTS /* the memory system will abort */ +/* For the old test suite Abort between 32 Kbytes and 32 Mbytes + For the new test suite Abort between 8 Mbytes and 26 Mbytes */ +#define LOWABORT 32 * 1024 +#define HIGHABORT 32 * 1024 * 1024 +/* #define LOWABORT 8 * 1024 * 1024 +#define HIGHABORT 26 * 1024 * 1024 */ +#endif + +#define TOP_OF_MEM 0x80000000 /* 2Gb to avoid stack-checking probs */ +#define NUMPAGES 64 * 1024 +#define PAGESIZE 64 * 1024 +#define PAGEBITS 16 +#define WORDOFFSETBITS 0xfffc +#define HWRDOFFSETBITS 0xfffe +#define BYTEOFFSETBITS 0xffff +#define ENDSWAP(addr) (addr ^ 3) +#define ENDSWAPH(addr) (addr ^ 2) +static unsigned HostEndian ; + +#define PAGETABLE ((unsigned char **)state->MemDataPtr) +#define DUMMYPAGE ((unsigned char *)state->MemSparePtr) + +/***************************************************************************\ +* Get a Word/Byte from Virtual Memory * +\***************************************************************************/ + +#define GetWord(state, address) \ + *( (ARMword *) \ + ( *(PAGETABLE + (address >> PAGEBITS)) + (address & WORDOFFSETBITS) ) \ + ) + +#define GetHalfWord(state, address) \ + (HostEndian ? \ + ( \ + (*( *(PAGETABLE + (address >> PAGEBITS)) + (address & HWRDOFFSETBITS)) << 8) + \ + *( *(PAGETABLE + (address >> PAGEBITS)) + (address & HWRDOFFSETBITS) + 1) \ + ) : \ + ( \ + *( *(PAGETABLE + (address >> PAGEBITS)) + (address & HWRDOFFSETBITS)) + \ + (*( *(PAGETABLE + (address >> PAGEBITS)) + (address & HWRDOFFSETBITS) + 1) << 8) \ + )) + +#define GetByte(state, address) \ + *( \ + ( *(PAGETABLE + (address >> PAGEBITS)) + (address & BYTEOFFSETBITS) ) \ + ) + +/***************************************************************************\ +* Put a Word/Byte into Virtual Memory, maybe allocating the page * +\***************************************************************************/ + +#define PutWord(state, address, data) \ + {unsigned char *xxpageptr; \ + if ((xxpageptr = PAGETABLE[address >> PAGEBITS]) == DUMMYPAGE) \ + xxpageptr = AllocatePage(state,address); \ + *(ARMword *)(xxpageptr + (address & WORDOFFSETBITS)) = data; \ + } + +#define PutHalfWord(state, address, data) \ + {unsigned char *xxpageptr; \ + ARMword xxaddr; \ + if ((xxpageptr = PAGETABLE[(address) >> PAGEBITS]) == DUMMYPAGE) \ + xxpageptr = AllocatePage(state, address); \ + xxaddr = (address) & HWRDOFFSETBITS; \ + if (HostEndian) { \ + xxpageptr[xxaddr] = (unsigned char)(((data) & 0xff00) >> 8); \ + xxpageptr[xxaddr + 1] = (unsigned char)((data) & 0xff); \ + } else { \ + xxpageptr[xxaddr] = (unsigned char)((data) & 0xff); \ + xxpageptr[xxaddr + 1] = (unsigned char)(((data) & 0xff00) >> 8); \ + } \ + } + +#define PutByte(state, address, data) \ + {unsigned char *xxpageptr ; \ + if ((xxpageptr = PAGETABLE[address >> PAGEBITS]) == DUMMYPAGE) \ + xxpageptr = AllocatePage(state,address) ; \ + xxpageptr[address & BYTEOFFSETBITS] = (unsigned char)data ; \ + } + +/***************************************************************************\ +* Allocate and return a memory page * +\***************************************************************************/ + +static unsigned char * AllocatePage(ARMul_State *state, ARMword address) +{unsigned char *pageptr ; + + pageptr = (unsigned char *)malloc(PAGESIZE) ; + if (pageptr == NULL) { + perror("ARMulator can't allocate VM page") ; + exit(13) ; + } + *(PAGETABLE + (address >> PAGEBITS)) = pageptr ; + return(pageptr) ; + } + +/***************************************************************************\ +* Initialise the memory interface * +\***************************************************************************/ + +unsigned ARMul_MemoryInit(ARMul_State *state, unsigned long initmemsize) +{unsigned char **pagetable ; + unsigned page ; + unsigned char *dummypage ; + + if (initmemsize == 0) + state->MemSize = TOP_OF_MEM; /* initialise to 4Gb if no size specified */ + else + state->MemSize = initmemsize; + if ((pagetable = (unsigned char **)malloc(sizeof(ARMword *)*NUMPAGES))==NULL) + return(FALSE) ; + if ((dummypage = (unsigned char *)malloc(PAGESIZE))==NULL) + return(FALSE) ; + for (page = 0 ; page < NUMPAGES ; page++) + *(pagetable + page) = dummypage ; + state->MemDataPtr = (unsigned char *)pagetable ; + state->MemSparePtr = (unsigned char *)dummypage ; + *(ARMword *)dummypage = 1 ; + HostEndian = (*dummypage != 1) ; /* 1 for big endian, 0 for little */ + *(ARMword *)dummypage = 0 ; +#ifdef BIGEND + state->bigendSig = HIGH ; +#endif +#ifdef LITTLEEND + state->bigendSig = LOW ; +#endif + if (state->MemSize >= 10 * 1024 * 1024) + ARMul_ConsolePrint(state, ", %dMbyte",state->MemSize/1024/1024); + else + ARMul_ConsolePrint(state, ", %dKbyte",state->MemSize/1024); + return(TRUE) ; +} + +/***************************************************************************\ +* Remove the memory interface * +\***************************************************************************/ + +void ARMul_MemoryExit(ARMul_State *state) +{ARMword page ; + unsigned char *pageptr ; + + for (page = 0 ; page < NUMPAGES ; page++) { + pageptr = *(PAGETABLE + page) ; + if (pageptr != DUMMYPAGE) + free((unsigned char *)pageptr) ; + } + free((unsigned char *)DUMMYPAGE) ; + free((unsigned char *)PAGETABLE) ; + return ; + } + +/***************************************************************************\ +* Load Instruction, Sequential Cycle * +\***************************************************************************/ + +#define NS_PER_S 1000000000 +#define ADDNS(p,t) \ + do { \ + (p)->a.ns += (p)->t; \ + if ((p)->a.ns >= NS_PER_S) (p)->a.ns -= NS_PER_S, (p)->a.s++; } \ + while (0) + +ARMword ARMul_LoadInstrS(ARMul_State *state,ARMword address) +{ + MemDescr *m; + + state->NumScycles++ ; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Sreads += 4L >> m->md.width; + ADDNS(m, ns_LoadInstrS); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef HOURGLASS_RATE + if( ( state->NumScycles & HOURGLASS_RATE ) == 0 ) { + armsd_hourglass(); + } +#endif + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_PREFETCHABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + return(GetWord(state,address)) ; +} + +/***************************************************************************\ +* Load Instruction, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstrN(ARMul_State *state,ARMword address) +{ + MemDescr *m; + + state->NumNcycles++ ; +#ifdef RUN_IN_16_BIT_MEMORY_HACK +state->NumFcycles++ ; +#endif + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nreads++; + m->a.Sreads += (4L >> m->md.width) - 1; + ADDNS(m, ns_LoadInstrN); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_PREFETCHABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + return(GetWord(state,address)) ; +} + +/***************************************************************************\ +* Load 16 bit Instruction, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstr16S(ARMul_State *state,ARMword address) +{ + MemDescr *m; + ARMword temp ; + + state->NumScycles++ ; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + if ((m->md.access & 4) && (address & 2) && m->md.width == 2) { + m->a.ns += state->cpu_ns; + } else { + m->a.Sreads++; + if (m->md.width == 0) m->a.Sreads++; + m->a.ns += m->ns_LoadInstr16S; + } + if (m->a.ns >= NS_PER_S) m->a.ns -= NS_PER_S, m->a.s++; + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef HOURGLASS_RATE + if( ( state->NumScycles & HOURGLASS_RATE ) == 0 ) { + armsd_hourglass(); + } +#endif + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_PREFETCHABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAPH(address) ; + return((ARMword)GetHalfWord(state,temp)) ; +} + +/***************************************************************************\ +* Load 16 bit Instruction, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstr16N(ARMul_State *state,ARMword address) +{ + MemDescr *m; + ARMword temp ; + + state->NumNcycles++ ; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nreads++; + if (m->md.width == 0) m->a.Sreads++; + ADDNS(m, ns_LoadInstr16N); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_PREFETCHABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAPH(address) ; + return((ARMword)GetHalfWord(state,temp)) ; + } + +/***************************************************************************\ +* Load Word, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadWordS(ARMul_State *state,ARMword address) +{ + MemDescr *m; + + state->NumScycles++ ; +#ifdef RUN_IN_16_BIT_MEMORY_HACK +state->NumFcycles++ ; +#endif + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Sreads += 4L >> m->md.width; + ADDNS(m, ns_LoadWordS); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(0) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + return(GetWord(state,address)) ; + } + +/***************************************************************************\ +* Load Word, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadWordN(ARMul_State *state,ARMword address) +{ + MemDescr *m; + + state->NumNcycles++ ; +#ifdef RUN_IN_16_BIT_MEMORY_HACK +state->NumFcycles++ ; +#endif + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nreads++; + m->a.Sreads += (4L >> m->md.width) - 1; + ADDNS(m, ns_LoadWordN); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(0) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + return(GetWord(state,address)) ; + } + +/***************************************************************************\ +* Load Halfword, (Non Sequential Cycle) * +\***************************************************************************/ + +ARMword ARMul_LoadHalfWord(ARMul_State *state,ARMword address) +{ + MemDescr *m; + ARMword temp ; + + state->NumNcycles++ ; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nreads++; + if (m->md.width == 0) m->a.Sreads++; + ADDNS(m, ns_LoadHalfWord); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(0) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAPH(address) ; + return((ARMword)GetHalfWord(state,temp)) ; + } + +/***************************************************************************\ +* Load Byte, (Non Sequential Cycle) * +\***************************************************************************/ + +ARMword ARMul_LoadByte(ARMul_State *state,ARMword address) +{ + MemDescr *m; + ARMword temp ; + + state->NumNcycles++ ; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nreads++; + ADDNS(m, ns_LoadByte); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(0) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAP(address) ; + return((ARMword)GetByte(state,temp)) ; + } + +/***************************************************************************\ +* Store Word, Sequential Cycle * +\***************************************************************************/ + +void ARMul_StoreWordS(ARMul_State *state,ARMword address, ARMword data) +{ + MemDescr *m; + + state->NumScycles++ ; +#ifdef RUN_IN_16_BIT_MEMORY_HACK +state->NumFcycles++ ; +#endif + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Swrites += 4L >> m->md.width; + ADDNS(m, ns_StoreWordS); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + PutWord(state,address,data) ; + } + +/***************************************************************************\ +* Store Word, Non Sequential Cycle * +\***************************************************************************/ + +void ARMul_StoreWordN(ARMul_State *state, ARMword address, ARMword data) +{ + MemDescr *m; + + state->NumNcycles++ ; +#ifdef RUN_IN_16_BIT_MEMORY_HACK +state->NumFcycles++ ; +#endif + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nwrites++; + m->a.Swrites += (4L >> m->md.width) - 1; + ADDNS(m, ns_StoreWordN); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + PutWord(state,address,data) ; + } + +/***************************************************************************\ +* Store HalfWord, Non Sequential Cycle * +\***************************************************************************/ + +void ARMul_StoreHalfWord(ARMul_State *state, ARMword address, ARMword data) +{ + MemDescr *m; + ARMword temp ; + + state->NumNcycles++ ; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nwrites++; + if (m->md.width == 0) m->a.Swrites++; + ADDNS(m, ns_StoreHalfWord); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAPH(address) ; + PutHalfWord(state,temp,data) ; +} + +/***************************************************************************\ +* Store Byte, (Non Sequential Cycle) * +\***************************************************************************/ + +void ARMul_StoreByte(ARMul_State *state, ARMword address, ARMword data) +{ + MemDescr *m; + + ARMword temp ; + + state->NumNcycles++ ; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nwrites++; + ADDNS(m, ns_StoreByte); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef VALIDATE + if (address == TUBE) { + if (data == 4) + state->Emulate = FALSE ; + else + (void)putc((char)data,stderr) ; /* Write Char */ + return ; + } +#endif + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAP(address) ; + PutByte(state,temp,(unsigned char)data) ; + } + +/***************************************************************************\ +* Swap Word, (Two Non Sequential Cycles) * +\***************************************************************************/ + +ARMword ARMul_SwapWord(ARMul_State *state, ARMword address, ARMword data) +{ + MemDescr *m; + ARMword temp ; + + state->NumNcycles+=2; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nreads++; + m->a.Nwrites++; + m->a.Sreads += (4L >> m->md.width) - 1; + m->a.Swrites += (4L >> m->md.width) - 1; + ADDNS(m, ns_SwapWord); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = GetWord(state,address) ; + PutWord(state,address,data) ; + return(temp) ; +} + +/***************************************************************************\ +* Swap Byte, (Two Non Sequential Cycles) * +\***************************************************************************/ + +ARMword ARMul_SwapByte(ARMul_State *state, ARMword address, ARMword data) +{ + MemDescr *m; + ARMword temp ; + + state->NumNcycles+=2; + for (m = state->MemInfoPtr; m != NULL; m = m->next) + if (address >= m->md.start && address < m->md.limit) { + m->a.Nreads++; + m->a.Nwrites++; + ADDNS(m, ns_SwapByte); + break; + } + if (!m) { + state->ns += state->cpu_ns; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + } + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = ARMul_LoadByte(state,address) ; + ARMul_StoreByte(state,address,data) ; + return(temp) ; + } + +/***************************************************************************\ +* Count I Cycles * +\***************************************************************************/ + +void ARMul_Icycles(ARMul_State *state, unsigned number, ARMword address) +{ + state->NumIcycles += number ; + state->ns += state->cpu_ns * number; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + ARMul_CLEARABORT ; + } + +/***************************************************************************\ +* Count C Cycles * +\***************************************************************************/ + +void ARMul_Ccycles(ARMul_State *state, unsigned number, ARMword address) +{ + state->NumCcycles += number ; + state->ns += state->cpu_ns * number; + if (state->ns >= NS_PER_S) state->ns -= NS_PER_S, state->s++; + ARMul_CLEARABORT ; + } + +/***************************************************************************\ +* Read Word (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadWord(ARMul_State *state, ARMword address) +{ +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + return(GetWord(state,address)) ; + } + +/***************************************************************************\ +* Read HalfWord (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadHalfWord(ARMul_State *state, ARMword address) +{ARMword temp; +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAPH(address) ; + return((ARMword)GetHalfWord(state,temp)) ; + } + +/***************************************************************************\ +* Read Byte (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadByte(ARMul_State *state, ARMword address) +{ARMword temp ; + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return(ARMul_ABORTWORD) ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAP(address) ; + return((ARMword)GetByte(state,temp)) ; + } + +/***************************************************************************\ +* Write Word (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteWord(ARMul_State *state, ARMword address, ARMword data) +{ +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + PutWord(state,address,data) ; + } + +/***************************************************************************\ +* Write HalfWord (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteHalfWord(ARMul_State *state, ARMword address, ARMword data) +{ARMword temp; +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAPH(address) ; + PutHalfWord(state,temp,data) ; + } + +/***************************************************************************\ +* Write Byte (but don't tell anyone!) * +\***************************************************************************/ + +void ARMul_WriteByte(ARMul_State *state, ARMword address, ARMword data) +{ARMword temp ; + +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) { + ARMul_DATAABORT(address) ; + return ; + } + else { + ARMul_CLEARABORT ; + } +#endif + + temp = (HostEndian == state->bigendSig)?address:ENDSWAP(address) ; + PutByte(state,temp,(unsigned char)data) ; + } + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/DLL/ARMULATE.MAK b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/DLL/ARMULATE.MAK new file mode 100644 index 0000000..ea2eb90 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/DLL/ARMULATE.MAK @@ -0,0 +1,29 @@ +SRCDIR1=..\.. +EXTDIR1=..\..\..\clx +EXTDIR2=..\..\..\armdbg +CFLAGS= -O2 -c -D__STDC__ -D_WINDOWS -DCODE16 /MT -DWIN32 -I$(SRCDIR1) -I$(EXTDIR1) -I$(EXTDIR2) -DHOURGLASS_RATE=8191 -DRDI_VERBOSE +CC=cl +TOLOCAL=copy +OBJALL=ARMULDLL.OBJ ARMCOPRO.OBJ ARMOS.OBJ ARMVIRT.OBJ +ARMULLIB=..\iarm.lib +WINLIBS=user32.lib +RC=rc + +#rules +armulate.dll: $(OBJALL) +armulate.dll: $(ARMULLIB) + del $@ + link.exe /DEFAULTLIB:$(WINLIBS) /DLL /DEF:"..\..\armulate.def" /SUBSYSTEM:CONSOLE /INCREMENTAL:no /OUT:"armulate.dll" $(OBJALL) $(ARMULLIB) + +armuldll.obj: ..\..\armuldll.c +armuldll.obj: ..\..\armuldll.h + $(CC) $(CFLAGS) ..\..\armuldll.c + +armcopro.obj: $(SRCDIR1)\armcopro.c + $(CC) $(CFLAGS) $(SRCDIR1)\armcopro.c + +armos.obj: $(SRCDIR1)\armos.c + $(CC) $(CFLAGS) $(SRCDIR1)\armos.c + +armvirt.obj: $(SRCDIR1)\armvirt.c + $(CC) $(CFLAGS) $(SRCDIR1)\armvirt.c diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/IARM.LIB b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/IARM.LIB new file mode 100644 index 0000000..d5b167d Binary files /dev/null and b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/ARMUL/MSVC20/IARM.LIB differ diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/AIF.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/AIF.H new file mode 100644 index 0000000..71fbb5f --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/AIF.H @@ -0,0 +1,52 @@ +/* + Title: Acorn Image Format + Status: C Library Extension + Copyright: (C) 1991 Advanced RISC Machines Limited. All rights reserved. + $Revision: 1.5.2.1 $ 27-Apr-91 +*/ + + +#ifndef __aif_h +#define __aif_h + +#include "host.h" + +#define AIF_NOOP 0xe1a00000 /* MOV r0, r0 */ +#define AIF_BLAL 0xeb000000 +#define OS_EXIT 0xef000011 /* SWI OS_Exit */ +#define OS_GETENV 0xef000010 /* SWI OS_GetEnv */ +#define AIF_IMAGEBASE 0x00008000 /* Default load address = 32K */ +#define AIF_BLZINIT 0xeb00000C +#define DEBUG_TASK 0xef041d41 /* RISC OS SWI DDE_Debug */ +#define AIF_DBG_SRC 2 +#define AIF_DBG_LL 1 + +#define AIF_DATABASAT 0x100L /* if has a separate data base */ + +typedef struct aif_hdr { + unsigned32 compress_br; + unsigned32 reloc_br; + unsigned32 zinit_br; + unsigned32 entry_br; + unsigned32 exit_swi; + unsigned32 rosize, rwsize, dbgsize, zinitsize; + unsigned32 dbgtype; + unsigned32 imagebase; + unsigned32 workspace; + unsigned32 address_mode; /* and flags */ + unsigned32 data_base; + unsigned32 fragment_offset; + unsigned32 spare2; + unsigned32 debug_swi; + unsigned32 zinitcode[15]; +} aif_hdr; + +typedef struct { + unsigned32 next_fragment_offset; + unsigned32 load_address; + unsigned32 size; + char name[32]; +} fragment_header; + +#endif + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/ASDFMT.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/ASDFMT.H new file mode 100644 index 0000000..cbb0034 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/ASDFMT.H @@ -0,0 +1,473 @@ +/* + Title: Acorn Object Format + Status: C Library Extension + Copyright: (C) 1991, 1994, Advanced RISC Machines Limited. All rights reserved. + + RCS $Revision: 1.15.2.1 $ + Checkin $Date: 1995/05/13 17:04:13 $ + Revising $Author: kwelton $ +*/ + +/* + * This header defines the essential structure of ASD debugging tables. + */ + +#ifndef __asd_h +#define __asd_h + +#include "host.h" + +#define ASD_FORMAT_VERSION 3 +/* decaof is already 4, stayed for armsd for the moment */ + +/* Most table items start with a word containing a type code and the length + in bytes of the item (most items end as defined here in an array of size 1, + which in actual tables is made as large as needed). + */ + +typedef unsigned32 CodeAndLen; + +#define asd_code_(x) ((x) & 0xffff) +#define asd_len_(x) ((x) >> 16) + +#define asd_codeword(c, l) ((c) | ((l) << 16)) + +/* the code field of a CodeAndLen may have the following values */ + +#define ITEMSECTION 1 +#define ITEMPROC 2 +#define ITEMENDPROC 3 +#define ITEMVAR 4 +#define ITEMTYPE 5 +#define ITEMSTRUCT 6 +#define ITEMARRAY 7 +#define ITEMSUBR 8 +#define ITEMSET 9 +#define ITEMFILEINFO 10 +#define ITEMENUMC 11 +#define ITEMENUMD 12 +#define ITEMFUNCTION 13 +#define ITEMSCOPEBEGIN 14 +#define ITEMSCOPEEND 15 +#define ITEMBITFIELD 16 +#define ITEMDEFINE 17 +#define ITEMUNDEF 18 +#define ITEMCLASS 19 +#define ITEMUNION 20 +#define ITEMFPMAPFRAG 32 + +/* Type descriptions are contained in items ... */ + +typedef int32 asd_Type; /* with the structure ... */ + +#define TYPE_PTRCOUNT(t) ((t) & 0xff) +#define TYPE_TYPECODE(t) ((t) >> 8) + +#define TYPE_TYPEWORD(t, p) (((t) << 8) | (p)) + +/* where TYPE_TYPECODE(type) is + negative, and its negated value is the offset in the debug data of an + item defining a type + or positive, and its value is one of those listed below + */ + +#define TYPEVOID 0 + +#define TYPESBYTE 10 +#define TYPESHALF 11 +#define TYPESWORD 12 + +#define TYPEUBYTE 20 +#define TYPEUHALF 21 +#define TYPEUWORD 22 + +#define TYPEFLOAT 30 +#define TYPEDOUBLE 31 +#define TYPELDOUBLE 32 + +#define TYPECOMPLEX 40 +#define TYPEDCOMPLEX 41 + +#define TYPESTRING 50 /* a primitive (char *) type (needed for Number) */ + +#define TYPEFUNCTION 100 + +#define type_integral(t) ((unsigned32)(t) < 30) +#define type_signed(t) ((unsigned32)(t) < 20) +#define type_fpoint(t) ((t) >= 30 && (t) < 40) +#define type_complex(t) ((t) >= 40 && (t) < 50) + +typedef unsigned32 asd_Address; +typedef unsigned32 asd_FileOffset; + +/* sourcepos items contain line number and character position fields */ + +#define FILE_LINE(f) ((f) & 0x3fffffL) +#define FILE_CHPOS(f) (((f) >> 22) & 0x3ff) + +#define FILE_POSWORD(f, ch) ((f) | ((ch) << 22)) + +typedef struct ItemFileInfo ItemFileInfo; +typedef struct ItemFileEntry ItemFileEntry; +typedef struct ItemEndProc ItemEndProc; + +/* Values for the lang field of an ItemSection */ + +#define LANG_NONE 0 +#define LANG_C 1 +#define LANG_PASCAL 2 +#define LANG_FORTRAN 3 +#define LANG_ASM 4 + +/* Bits set in the flags field of an ItemSection */ + +#define FLAG_LINES(f) ((f) & 1) +#define FLAG_VARS(f) ((f) & 2) +#define FLAG_FPMAP(f) ((f) & 4) + +typedef union asd_NameP +{ char name[1]; + char *namep; +} asd_Name; + +typedef struct ItemSection +{ CodeAndLen id; + unsigned char lang; + unsigned char flags; + unsigned char unused; + unsigned char asdversion; + asd_Address codestart; + asd_Address datastart; + int32 codesize; + int32 datasize; + union { + asd_FileOffset i; + ItemFileInfo *p; + } fileinfo; + unsigned32 debugsize; + union { + char name[1]; /* high level section */ + unsigned32 nsyms; /* low level section: nsyms ItemSymbols follow */ + char *namep; + } n; +} ItemSection; + +/* the sym field of an ItemSymbol consists of + * 24 (ls) bits of string table index + * 8 (ms) bits of flags. + */ + +#define STR_INDEX(s) ((s) & 0xffffffL) + +#define ASD_LOCSYM 0 +#define ASD_GLOBSYM 0x01000000L +#define ASD_SYMGLOBAL(s) ((s) & 0x1000000L) + +#define ASD_ABSSYM 0 +#define ASD_TEXTSYM 0x02000000L +#define ASD_DATASYM 0x04000000L +#define ASD_ZINITSYM 0x06000000L +#define ASD_SYMTYPE(s) ((s) & 0x6000000L) + +#define ASD_32BITSYM 0 +#define ASD_16BITSYM 0x10000000L +#define ASD_SYM16(s) ((s) & 0x10000000L) + + +typedef struct ItemSymbol +{ unsigned32 sym; + unsigned32 value; +} ItemSymbol; + +typedef union +{ asd_FileOffset i; + ItemFileEntry *p; +} asd_FileEntryP; + +typedef struct ItemProc +{ CodeAndLen id; + asd_Type type; /* of the return value */ + unsigned32 args; + unsigned32 sourcepos; + asd_Address startaddr; + asd_Address entry; + union { + asd_FileOffset i; + ItemEndProc *p; + } endproc; + asd_FileEntryP fileentry; + asd_Name n; +} ItemProc; + +struct ItemEndProc +{ CodeAndLen id; + unsigned32 sourcepos; + asd_Address endpoint; + asd_FileEntryP fileentry; + unsigned32 nreturns; + asd_Address retaddrs[1]; +}; + +/* Values for ItemVar storageclass field */ +typedef enum StgClass { + C_NONE, + C_EXTERN, + C_STATIC, + C_AUTO, + C_REG, + C_VAR, + C_FARG, + C_FCARG, + C_LOCAL, + C_FILTERED, + C_GLOBALREG +} StgClass; + +typedef struct ItemVar +{ CodeAndLen id; + asd_Type type; + unsigned32 sourcepos; + unsigned32 storageclass; /* StgClass really */ + union { + int32 offset; + asd_Address address; + } location; + asd_Name n; +} ItemVar; + +typedef struct ItemType +{ CodeAndLen id; + asd_Type type; + asd_Name n; +} ItemType; + +typedef struct StructField +{ unsigned32 offset; + asd_Type type; + asd_Name n; +} StructField; + +typedef struct SUC +{ CodeAndLen id; + unsigned32 fields; + unsigned32 size; + StructField fieldtable[1]; +} SUC; + +typedef SUC ItemStruct; +typedef SUC ItemClass; +typedef SUC ItemUnion; + +/* Meaning of the flags field in an ItemArray */ + +#define ARRAY_UNDEF_LBOUND(f) ((f) & 1) +#define ARRAY_CONST_LBOUND(f) ((f) & 2) +#define ARRAY_UNDEF_UBOUND(f) ((f) & 4) +#define ARRAY_CONST_UBOUND(f) ((f) & 8) +#define ARRAY_VAR_LBOUND(f) ((f) & 16) +#define ARRAY_VAR_UBOUND(f) ((f) & 32) + +typedef union asd_ArrayBound +{ int32 i; /* (undef), const */ + int32 o; /* no flag bit set: bound is a variable on the stack + * with this fp offset */ + asd_FileOffset v;/* var: file form */ + ItemVar *vp; /* var: in memory form */ +} asd_ArrayBound; + +typedef struct ItemArray +{ CodeAndLen id; + unsigned32 size; + unsigned32 flags; + asd_Type basetype; + asd_ArrayBound lowerbound, + upperbound; +} ItemArray; + +/* The sizeandtype field of an ItemSubRange */ + +#define SUBRANGE_SIZE(s) ((s) & 0xffff) +#define SUBRANGE_TYPECODE(s) ((s) >> 16) + +typedef struct ItemSubrange +{ CodeAndLen id; + int32 sizeandtype; + int32 lb, hb; +} ItemSubrange; + +typedef struct ItemSet +{ CodeAndLen id; + unsigned32 size; +} ItemSet; + +typedef struct ItemEnumC +{ CodeAndLen id; + asd_Type type; /* of the container */ + unsigned32 count; + int32 base; + union { + char nametable[1]; + char *nametablep[1]; + } nt; +} ItemEnumC; + +typedef struct asd_EnumMember +{ int32 val; + asd_Name n; +} asd_EnumMember; + +typedef struct ItemEnumD +{ CodeAndLen id; + asd_Type type; /* of the container */ + unsigned32 count; + asd_EnumMember nametable[1]; +} ItemEnumD; + +typedef struct asd_Arg +{ asd_Type type; + asd_Name n; +} asd_Arg; + +typedef struct ItemFunction +{ CodeAndLen id; + asd_Type type; /* of the returned value */ + unsigned32 argcount; + asd_Arg args[1]; +} ItemFunction; + +typedef struct ItemBitfield +{ CodeAndLen id; + asd_Type type; /* of the extracted value */ + asd_Type container; + unsigned char size, offset, + pad1, pad2; +} ItemBitfield; + +typedef struct ItemScope /* begin or end */ +{ CodeAndLen id; + asd_Address codeaddress; +} ItemScope; + +typedef struct ItemDefine +{ CodeAndLen id; + asd_FileEntryP fileentry; + unsigned32 sourcepos; + union { + asd_FileOffset i; + char *p; + } body; + int32 argcount; + union { + asd_FileOffset i; + asd_Name *p; + } argtable; + asd_Name n; +} ItemDefine; + +typedef struct ItemUndef +{ CodeAndLen id; + asd_FileEntryP fileentry; + unsigned32 sourcepos; + asd_Name n; +} ItemUndef; + +typedef struct Fragment +{ unsigned32 size; + unsigned32 firstline, lastline; + asd_Address codestart; + unsigned32 codesize; + unsigned char lineinfo[1]; +} Fragment; + +#define Asd_LineInfo_Short_MaxLine 63 + +/* short form lineinfo items have code and file position increments < 256. + * If the current file position is (line, col), a file position increment + * fpinc describes a new file position + * (line+fpinc, 1) if inc <= Asd_LineInfo_Short_MaxLine + * (line, col+fpinc-Asd_LineInfo_Short_MaxLine-1) otherwise + * + * fpinc = 0, codeinc = 0 indicates that the item is in long format 1: + * new file position is (line+lineinc, 1) + * + * fpinc = Asd_LineInfo_Short_MaxLine+1, codeinc = 0 indicates that the + * item is in long format 2. new file position is + * (line+lineinc, newcol) + */ + +typedef struct +{ unsigned char codeinc; + unsigned char lineinc; +} asd_LineInfo_Short; + +typedef struct +{ unsigned short marker; + unsigned short lineinc; /* (in target byte order) */ + unsigned short codeinc; /* (in target byte order) */ +} asd_LineInfo_Long_1; + +typedef struct +{ unsigned short marker; + unsigned short lineinc; /* (in target byte order) */ + unsigned short codeinc; /* (in target byte order) */ + unsigned short newcol; /* (in target byte order) */ +} asd_LineInfo_Long_2; + +struct ItemFileEntry +{ unsigned32 len; + unsigned32 date; + char filename[1]; +}; + +struct ItemFileInfo +{ CodeAndLen id; + ItemFileEntry entries[1]; +}; + +typedef struct ItemFPMapFragment { + unsigned32 marker; + int32 bytes; + asd_Address codestart; + asd_Address saveaddr; + unsigned32 codesize; + int32 initoffset; + char b[1]; +} ItemFPMapFragment; + +typedef struct { + unsigned char codeinc; + signed char offsetinc; +} asd_FPInfo_Short; + +typedef struct { + char marker[2]; + unsigned short codeinc; + signed short offsetinc; +} asd_FPInfo_Long; + +typedef union { + unsigned char b; + CodeAndLen c; + ItemSection sect; + ItemProc p; + ItemEndProc e; + ItemVar v; + ItemArray a; + ItemType t; + ItemStruct s; + ItemSubrange sr; + ItemSet set; + ItemFileInfo f; + ItemFileEntry fe; + ItemEnumC ec; + ItemEnumD ed; + ItemFunction fn; + ItemScope sc; + ItemBitfield bf; + ItemDefine def; + ItemUndef undef; + ItemFPMapFragment fp; +} Item; + +#endif + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/HOST.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/HOST.H new file mode 100644 index 0000000..1625b00 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/HOST.H @@ -0,0 +1,279 @@ +/* + * C compiler file mip/host.h + * Copyright (C) Codemist Ltd., 1988 + * Copyright (C) Acorn Computers Ltd., 1988. + */ + +/* + * RCS $Revision: 1.15.2.7 $ Codemist 11 + * Checkin $Date: 1995/06/29 10:47:31 $ + * Revising $Author: kwelton $ + */ + +/* AM memo, July 1990: in principle there should be no tests of */ +/* COMPILING_ON_, but only COMPILING_ON_ or */ +/* COMPILING_ON_ (for special features). */ +/* Accordingly COMPILING_ON_ is deprecated. */ + +/* + * This file deals with peculiarities of the host system under which the + * compiler is compiled AND peculiarities of the host system under which + * the compiler will run (hence it might need further explication in the + * unlikely event that we wish to cross-compile the compiler (repeatedly + * as opposed to once-off bootstrap)). It is now loaded first and can + * therefore not depend on TARGET_xxx parameterisations, these are now + * done in target.h or, if systematic, in mip/defaults.h. + * The correct mechanism for host->target dependencies (e.g. if compiling + * on unix then make a unix compiler, else a homebrew object file version) + * is via the options.h file, along the lines of: + * #ifdef COMPILING_ON_UNIX + * # define TARGET_IS_UNIX + * #endif + * The intent is that most of the pecularities should be linked to + * COMPILING_ON_machine and/or COMPILING_ON_system. Further NO OTHER FILE + * should refer to magic names like 'unix', '__arm' etc., but go via + * the COMPILING_xxx flags defined here in terms of these. + * The aim is that this file should suffice for all host dependencies + * and thus all COMPILING_ON_xxx tests outwith are suspect. However, + * the #include file munger clearly needs to so depend. + */ + +#ifndef _host_LOADED +#define _host_LOADED 1 + +#include +#include /* for xsyn.c (and more?) and offsetof test below */ +#include /* for EXIT_FAILURE test below */ + +#ifndef SEEK_SET +# define SEEK_SET 0 +#endif +#ifndef SEEK_CUR +# define SEEK_CUR 1 +#endif +#ifndef SEEK_END +# define SEEK_END 2 +#endif + +#ifdef __STDC__ + +#define BELL '\a' +typedef void /* newline to fool the topcc tool */ + *VoidStar; +typedef const void + *ConstVoidStar; +#define safe_tolower(ch) tolower(ch) /* see comment below */ +#define safe_toupper(ch) toupper(ch) /* see comment below */ + +#else /* ! __STDC__ */ + +#define BELL '\007' +typedef char *VoidStar; +#define ConstVoidStar VoidStar +/* + * not all C libraries define tolower() and toupper() over all character + * values. BSD Unix, for example, defines tolower() only over UC chars. + */ +#define safe_tolower(ch) (isupper(ch) ? tolower(ch) : ch) +#define safe_toupper(ch) (islower(ch) ? toupper(ch) : ch) + +#endif /* ! __STDC__ */ + +/* The following for the benefit of compiling on SunOS */ +#ifndef offsetof +# define offsetof(T, member) ((char *)&(((T *)0)->member) - (char *)0) +#endif + +#ifdef unix /* A temporary sop to older compilers */ +# ifndef __unix /* (good for long-term portability?) */ +# define __unix 1 +# endif +#endif + +#ifdef __unix +/* Generic unix -- hopefully a split into other variants will not be */ +/* needed. However, beware the 'bsd' test above and safe_toupper etc. */ +/* which cope with backwards (pre-posix/X/open) unix compatility. */ +# define COMPILING_ON_UNIX 1 +#endif +#ifdef __helios +/* start improving parameterisation. Maybe we should also set */ +/* COMPILING_ON_UNIX and use HELIOS as a special subcase? */ +# define COMPILING_ON_HELIOS 1 +#endif +#ifdef __acorn +# define COMPILING_ON_ACORN_KIT 1 +#endif +#ifdef __riscos +# define COMPILING_ON_RISC_OS 1 +#endif +#ifdef __arm +# define COMPILING_ON_ARM 1 /* dying: unix/riscos/acorn suffice */ +#endif +#ifdef __ibm370 +# ifndef COMPILING_ON_UNIX +# define __mvs 1 /* a hack to be removed soon */ +# endif +#endif +#ifdef __mvs +# define COMPILING_ON_MVS 1 +#endif +#ifdef _MSDOS +# define COMPILING_ON_MSDOS 1 +#endif +#ifdef __ZTC__ +# define COMPILING_ON_MSDOS 1 +#endif +#ifdef __WATCOMC__ +# define COMPILING_ON_MSDOS 1 +#endif +#ifdef _MSC_VER +# define COMPILING_ON_MSDOS 1 +#endif +#ifdef macintosh +# define COMPILING_ON_MACINTOSH 1 /* for things that depend on how Macintosh handles filenames, etc. */ +# define COMPILING_ON_MPW 1 /* for things that depend on how MPW handles arguments, i/o, etc. */ +#endif + +/* + * The following typedefs may need alteration for obscure host machines. + */ +#ifdef __alpha +typedef int int32; +typedef unsigned int unsigned32; +#else +typedef long int int32; +typedef unsigned long int unsigned32; +#endif +typedef short int int16; +typedef unsigned short int unsigned16; +typedef signed char int8; +typedef unsigned char unsigned8; +typedef int bool; + +/* + * The following sets ArgvType for 64-bit pointers so that + * DEC Unix (OSF) cc can be used with the -xtaso_short compiler option + * to force pointers to be 32-bit. + */ +#if defined(__alpha) && defined(__osf__) +#pragma pointer_size (save) +#pragma pointer_size (long) +#endif +typedef char *ArgvType; +#if defined(__alpha) && defined(__osf__) +#pragma pointer_size (restore) +#endif + +#define YES 1 +#define TRUE 1 +#define NO 0 +#define FALSE 0 + +/* + * Rotate macros + */ +#define ROL_32(val, n) \ +((((unsigned32)(val) << (n)) | ((unsigned32)(val) >> (32-(n)))) & 0xFFFFFFFFL) +#define ROR_32(val, n) \ +((((unsigned32)(val) >> (n)) | ((unsigned32)(val) << (32-(n)))) & 0xFFFFFFFFL) + +/* The following two lines are a safety play against using ncc with a */ +/* vendor supplied library, many of which refuse to accept "wb". POSIX */ +/* and other unix standards require "wb" and "w" to have the same */ +/* effect and so the following is safe. */ +#ifdef COMPILING_ON_UNIX +# define FOPEN_WB "w" +# define FOPEN_RB "r" +# define FOPEN_RWB "r+" +# ifndef __STDC__ /* caveat RISCiX... */ +# define remove(file) unlink(file) /* a horrid hack, but probably best? */ +# endif +#else +# define FOPEN_WB "wb" +# define FOPEN_RB "rb" +# define FOPEN_RWB "rb+" +#endif + +/* (defined __sparc && defined P_tmpdir) is to detect gcc on SunOS */ +#if !defined __STDC__ || (defined __sparc && defined P_tmpdir) +/* Use bcopy rather than memmove, as memmove is not available. */ +# define memmove(d,s,l) bcopy(s,d,l) +/* BSD/SUN don't have strtoul(), but then strtol() doesn't barf on */ +/* overflow as required by ANSI... This bodge is horrid. */ +# define strtoul(s, ptr, base) strtol(s, ptr, base) +/* strtod is present in the C-library but is not in stdlib.h */ +extern double strtod(const char *str, char **ptr); +#endif + +#ifdef __CC_NORCROFT +# ifndef COMPILING_ON_UNIX /* suppress if maybe non-norcroft lib */ +# define LIBRARY_IS_NORCROFT 1 +# endif +# ifdef LIBRARY_IS_ALIEN /* unify with the 3 previous lines? */ +# undef LIBRARY_IS_NORCROFT +# endif +#endif + +#ifdef LIBRARY_IS_NORCROFT +/* + * Calls to all non-ansi functions are removable by macros here. + */ +#ifdef __cplusplus +extern "C" { +#endif +/* These routines have no floating point abilities. */ +extern int _vfprintf(FILE *stream, const char *format, __va_list arg); +extern int _vsprintf(char *s, const char *format, __va_list arg); +extern int _fprintf(FILE *stream, const char *format, ...); +extern int _sprintf(char *s, const char *format, ...); +#ifdef __cplusplus +} +#endif +#else /* LIBRARY_IS_NORCROFT */ +# define _vfprintf vfprintf +# define _vsprintf vsprintf +# define _fprintf fprintf +# define _sprintf sprintf +#endif /* LIBRARY_IS_NORCROFT */ + +#ifdef COMPILING_ON_MVS + +#define HOST_USES_CCOM_INTERFACE 1 +#define EXIT_warn 4 +#define EXIT_error 8 +#define EXIT_fatal 12 +#define EXIT_syserr 16 + +/* + * The following #included #define's ensure that external symbols are + * limited to 6 chars without gratuitous changes to every file. + */ +#include "sixchar.h" + +#else /* ! COMPILING_ON_MVS */ + +#define EXIT_warn 0 +#define EXIT_error 1 +#define EXIT_fatal 1 + +#ifdef COMPILING_ON_UNIX +# define EXIT_syserr 100 +#else +# define EXIT_syserr 1 +#endif + +#endif /* ! COMPILING_ON_MVS */ + +/* For systems that do not define EXIT_SUCCESS and EXIT_FAILURE */ +#ifndef EXIT_SUCCESS +# define EXIT_SUCCESS 0 +#endif +#ifndef EXIT_FAILURE +# define EXIT_FAILURE EXIT_error +#endif + +#endif + +/* end of host.h */ + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/IEEEFLT.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/IEEEFLT.H new file mode 100644 index 0000000..eb215c7 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/IEEEFLT.H @@ -0,0 +1,75 @@ +/* + * ieeeflt.h: interface to host-arithmetic-independent IEEE fp package. + * Copyright (C) Codemist Ltd., 1994. + * Copyright (C) Advanced RISC Machines Limited, 1994. + */ + +/* + * RCS $Revision: 1.2.2.1 $ + * Checkin $Date: 1995/05/13 17:04:14 $ + * Revising $Author: kwelton $ + */ + +#ifndef _ieeeflt_LOADED +#define _ieeeflt_LOADED + +/* + * The following types describe the representation of floating-point + * values by the compiler in both binary and source-related forms. + * The order of fields in DbleBin in is exploited only in object-code + * formatters and assembly code generators. + */ + +#include "host.h" + +typedef struct DbleBin { +#ifdef TARGET_HAS_OTHER_IEEE_ORDER + int32 lsd,msd; /* e.g. clipper */ +#else + int32 msd,lsd; /* e.g. arm, 370 (not really ieee) */ +#endif +} DbleBin; + +typedef struct FloatBin { + int32 val; +} FloatBin; + +#define flt_ok 0 +#define flt_very_small 1 +#define flt_very_big 2 +#define flt_big_single 3 +#define flt_small_single 4 +#define flt_negative 5 +#define flt_divide_by_zero 6 +#define flt_invalidop 7 /* inf - int, inf / inf, anything involving NaNs */ +#define flt_bad 8 /* invalid string for stod */ + +extern int fltrep_stod(const char *s, DbleBin *p, char **endp); +extern int fltrep_narrow(DbleBin const *d, FloatBin *e); +extern int fltrep_narrow_round(DbleBin const *d, FloatBin *e); +extern void fltrep_widen(FloatBin const *e, DbleBin *d); + +extern int flt_add(DbleBin *a, DbleBin const *b, DbleBin const *c); +extern int flt_subtract(DbleBin *a, DbleBin const *b, DbleBin const *c); +extern int flt_multiply(DbleBin *a, DbleBin const *b, DbleBin const *c); +extern int flt_divide(DbleBin *a, DbleBin const *b, DbleBin const *c); +extern int flt_compare(DbleBin const *b, DbleBin const *c); +extern int flt_move(DbleBin *a, DbleBin const *b); +extern int flt_negate(DbleBin *a, DbleBin const *b); +extern int flt_abs(DbleBin *a, DbleBin const *b); + +extern int flt_dtoi(int32 *n, DbleBin const *a); +extern int flt_dtou(unsigned32 *u, DbleBin const *a); + +extern int flt_itod(DbleBin *a, int32 n); +extern int flt_utod(DbleBin *a, unsigned32 n); + +void flt_frexp(DbleBin *res, DbleBin const *dp, int *lvn); +void flt_ldexp(DbleBin *res, DbleBin const *dp, int n); + +int fltrep_dtos(char *p, int flags, int ch, int precision, int width, + char *prefix, DbleBin const *d); +extern void fltrep_sprintf(char *b, char const *fmt, DbleBin const *dp); + +#endif + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/MSG.H b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/MSG.H new file mode 100644 index 0000000..1722480 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/MSG.H @@ -0,0 +1,104 @@ +/* msg.h -- interface to the message file and nls system. */ +/* Copyright (C) Advanced RISC Machines Limited, 1995. All rights reserved. */ + +/* + * RCS $Revision: 1.8 $ + * Checkin $Date: 1995/03/14 17:09:16 $ + * Revising $Author: mwilliam $ + */ + +#ifndef msg_h +#define msg_h + +#include + +#ifdef NLS +#include + +/* + * Initialise a tool. Passed in the name of the tool, and it attempts to + * locate the message file (in a host dependent way). Can be called + * multiple times for various components of a tool - e.g.: + * msg_init("armdbg",NULL); msg_init("armsd",NULL); msg_init("armul",NULL); + * + * toolname may be a full pathname to the tool - e.g. argv[0] under DOS, + * in which case that directory will be searched for the messagefile too. + */ +extern void msg_init(const char * /*toolname*/, + const char * /*default_name*/); + +/* Open and "closes" a message file. Once closed, all attempts to lookup a + * message will fail. close also frees any internally allocated store. + */ + +/* It is possible, at the moment, to call msg_open() multiple times, and the + * message files will be merged (new entries overwriting old). However any + * call to msg_close() will destroy the entire hash table, unfortunately. + */ +extern char *msg_open(const char * /*filename*/); /* Returns NULL on error */ +extern void msg_close(char * /*value_returned_by_msg_open*/); + +/* At the moment if you call msg_lookup(), or any function which in turn + * calls msg_lookup() will call msg_open("messages") if no msg_open call + * has yet been called. + */ + +typedef const unsigned char *msg_t; /* type of message tag */ + +/* printf variants */ +extern int msg_printf(msg_t /*tag*/, ...); +extern int msg_sprintf(char *, msg_t /*tag*/, ...); +extern int msg_fprintf(FILE *, msg_t /*tag*/, ...); +extern int msg_vsprintf(char *, msg_t /*tag*/, va_list); +extern int msg_vfprintf(FILE *, msg_t /*tag*/, va_list); + +/* Low-level find-a-message-from-a-tag routine */ +/* If the lookup fails, it tries the equivalent of returning the result + * from msg_sprintf("msg_lookup_failed",tag); + */ +extern char *msg_lookup(msg_t /*tag*/); + + +/* ==== nls printf functions (take format strings, not tags) ==== */ + +extern int nls_printf(const char * /*fmt*/, ...); +extern int nls_sprintf(char *,const char * /*fmt*/, ...); +extern int nls_fprintf(FILE *,const char * /*fmt*/, ...); +extern int nls_vfprintf(FILE *,const char * /*fmt*/, va_list); + +/* ==== Even lower-level things ==== */ +typedef union { + double floating; + long cardinal; + void *pointer; +} nls_type; + +/* These functions take a *format* string, not a tag. */ +extern nls_type *nls_va2type(const char * /*fmt*/, va_list); +extern int nls_tsprintf(char *,const char * /*fmt*/, nls_type *); +extern int nls_tfprintf(FILE *,const char * /*fmt*/, nls_type *); + +#else + +typedef char *msg_t; /* type of message tag */ + +# define msg_printf printf +# define msg_sprintf sprintf +# define msg_fprintf fprintf +# define msg_vsprintf vsprintf +# define msg_vfprintf vfprintf + +# define nls_printf printf +# define nls_sprintf sprintf +# define nls_fprintf fprintf +# define nls_vfprintf vfprintf + +# define msg_init(X,Y) /* null def'n */ +# define msg_open(X) +# define msg_close(X) + +# define msg_lookup(X) X +#endif + +#endif + \ No newline at end of file diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/MSVC20/CLX.LIB b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/MSVC20/CLX.LIB new file mode 100644 index 0000000..85ba5d7 Binary files /dev/null and b/Bachelor/Mikroprozessorsysteme2/ARM202U/SOURCE/WIN32/CLX/MSVC20/CLX.LIB differ -- cgit v1.2.3