From 33613a85afc4b1481367fbe92a17ee59c240250b Mon Sep 17 00:00:00 2001 From: Sven Eisenhauer Date: Fri, 10 Nov 2023 15:11:48 +0100 Subject: add new repo --- .../CANVerificationTool/CANVerificationTool.avrsln | 20 + .../CANVerificationTool.avrgccproj | 553 ++++++ .../CANVerificationTool/Framework.config | 71 + .../CANVerificationTool/__TemplateIcon.png | Bin 0 -> 935 bytes .../CANVerificationTool/src/AVR_COMPILER.H | 2 + .../CANVerificationTool/src/CAN1c1.c | 657 +++++++ .../CANVerificationTool/src/CAN1c1.h | 322 ++++ .../CANVerificationTool/src/CAND1c1.c | 314 ++++ .../CANVerificationTool/src/CAND1c1.h | 38 + .../CANVerificationTool/src/CANDCI.h | 89 + .../CANVerificationTool/src/CANIF1c1.c | 126 ++ .../CANVerificationTool/src/CANIF1c1.h | 24 + .../CANVerificationTool/src/EVHD1c1.c | 415 +++++ .../CANVerificationTool/src/EVHD1c1.h | 79 + .../CANVerificationTool/src/EVHD1ce.h | 58 + .../CANVerificationTool/src/EXEA1c1.c | 57 + .../CANVerificationTool/src/EXEA1c1.h | 28 + .../CANVerificationTool/src/EXEA1ce.h | 30 + .../CANVerificationTool/src/IL1c1.c | 1419 +++++++++++++++ .../CANVerificationTool/src/IL1c1.h | 27 + .../CANVerificationTool/src/IVECT1c1.c | 34 + .../CANVerificationTool/src/IVECT1c1.h | 23 + .../CANVerificationTool/src/IVECT1ce.h | 16 + .../CANVerificationTool/src/OS1c1.c | 230 +++ .../CANVerificationTool/src/OS1c1.h | 104 ++ .../CANVerificationTool/src/OS1ce.h | 32 + .../CANVerificationTool/src/PINT1c1.c | 51 + .../CANVerificationTool/src/PINT1c1.h | 15 + .../CANVerificationTool/src/PINT1ce.h | 36 + .../CANVerificationTool/src/START1C1.c | 148 ++ .../CANVerificationTool/src/START1C1.h | 17 + .../CANVerificationTool/src/TIMER1c1.c | 122 ++ .../CANVerificationTool/src/TIMER1c1.h | 143 ++ .../CANVerificationTool/src/TIMER1ce.h | 31 + .../CANVerificationTool/src/asf.h | 64 + .../src/asf/avr32/boards/uc3c_ek/led.h | 185 ++ .../src/asf/avr32/boards/uc3c_ek/uc3c_ek.h | 323 ++++ .../src/asf/avr32/drivers/canif/canif.c | 115 ++ .../src/asf/avr32/drivers/canif/canif.h | 331 ++++ .../src/asf/avr32/drivers/flashc/flashc.c | 1136 ++++++++++++ .../src/asf/avr32/drivers/flashc/flashc.h | 1018 +++++++++++ .../src/asf/avr32/drivers/gpio/gpio.c | 649 +++++++ .../src/asf/avr32/drivers/gpio/gpio.h | 680 ++++++++ .../src/asf/avr32/drivers/intc/exception.S | 237 +++ .../src/asf/avr32/drivers/intc/intc.c | 214 +++ .../src/asf/avr32/drivers/intc/intc.h | 90 + .../src/asf/avr32/drivers/pm/pm_uc3c.c | 277 +++ .../src/asf/avr32/drivers/pm/pm_uc3c.h | 392 +++++ .../src/asf/avr32/drivers/pm/power_clocks_lib.c | 575 +++++++ .../src/asf/avr32/drivers/pm/power_clocks_lib.h | 381 ++++ .../src/asf/avr32/drivers/pm/sleep.h | 149 ++ .../src/asf/avr32/drivers/scif/scif_uc3c.c | 784 +++++++++ .../src/asf/avr32/drivers/scif/scif_uc3c.h | 761 ++++++++ .../src/asf/avr32/drivers/tc/tc.c | 312 ++++ .../src/asf/avr32/drivers/tc/tc.h | 589 +++++++ .../src/asf/avr32/drivers/wdt/wdt.h | 140 ++ .../src/asf/avr32/drivers/wdt/wdt4.c | 165 ++ .../src/asf/avr32/services/network/can/can.c | 464 +++++ .../src/asf/avr32/services/network/can/can.h | 183 ++ .../src/asf/avr32/utils/compiler.h | 1233 +++++++++++++ .../at32uc3c/0512c/gcc/link_uc3c0512c.lds | 288 ++++ .../src/asf/avr32/utils/parts.h | 253 +++ .../src/asf/avr32/utils/preprocessor/mrepeat.h | 326 ++++ .../asf/avr32/utils/preprocessor/preprocessor.h | 53 + .../src/asf/avr32/utils/preprocessor/stringz.h | 73 + .../src/asf/avr32/utils/preprocessor/tpaste.h | 93 + .../src/asf/avr32/utils/startup/startup_uc3.S | 118 ++ .../src/asf/avr32/utils/startup/trampoline_uc3.S | 75 + .../src/asf/avr32/utils/startup/trampoline_uc3.h | 52 + .../src/asf/avr32/utils/status_codes.h | 81 + .../src/asf/common/boards/board.h | 196 +++ .../src/asf/common/services/clock/genclk.h | 136 ++ .../src/asf/common/services/clock/osc.h | 145 ++ .../src/asf/common/services/clock/pll.h | 279 +++ .../src/asf/common/services/clock/sysclk.h | 150 ++ .../src/asf/common/services/clock/uc3c/genclk.h | 132 ++ .../src/asf/common/services/clock/uc3c/osc.c | 169 ++ .../src/asf/common/services/clock/uc3c/osc.h | 600 +++++++ .../src/asf/common/services/clock/uc3c/pll.c | 76 + .../src/asf/common/services/clock/uc3c/pll.h | 228 +++ .../src/asf/common/services/clock/uc3c/sysclk.c | 407 +++++ .../src/asf/common/services/clock/uc3c/sysclk.h | 1169 +++++++++++++ .../src/asf/common/utils/interrupt.h | 132 ++ .../asf/common/utils/interrupt/interrupt_avr32.h | 342 ++++ .../CANVerificationTool/src/can1ce.h | 141 ++ .../CANVerificationTool/src/cdef.h | 70 + .../CANVerificationTool/src/config/CANDCI.h | 89 + .../CANVerificationTool/src/config/conf_board.h | 11 + .../CANVerificationTool/src/config/conf_can.h | 97 ++ .../CANVerificationTool/src/config/conf_clock.h | 55 + .../CANVerificationTool/src/main.c | 29 + .../src/CANVerificationTool/doc/Doxyfile | 1813 ++++++++++++++++++++ 92 files changed, 24656 insertions(+) create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool.avrsln create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/CANVerificationTool.avrgccproj create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/Framework.config create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/__TemplateIcon.png create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/AVR_COMPILER.H create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAN1c1.c create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAN1c1.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAND1c1.c create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAND1c1.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CANDCI.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CANIF1c1.c create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CANIF1c1.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EVHD1c1.c create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EVHD1c1.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EVHD1ce.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EXEA1c1.c create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EXEA1c1.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EXEA1ce.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/IL1c1.c create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/IL1c1.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/IVECT1c1.c create mode 100644 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Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/power_clocks_lib.c create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/power_clocks_lib.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/sleep.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/scif/scif_uc3c.c create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/scif/scif_uc3c.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/tc/tc.c create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/tc/tc.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/wdt/wdt.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/wdt/wdt4.c create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/services/network/can/can.c create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/services/network/can/can.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/compiler.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/linker_scripts/at32uc3c/0512c/gcc/link_uc3c0512c.lds create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/parts.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/mrepeat.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/preprocessor.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/stringz.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/tpaste.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/startup/startup_uc3.S create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/startup/trampoline_uc3.S create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/startup/trampoline_uc3.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/status_codes.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/boards/board.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/genclk.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/osc.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/pll.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/sysclk.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/genclk.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/osc.c create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/osc.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/pll.c create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/pll.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/sysclk.c create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/sysclk.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/utils/interrupt.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/utils/interrupt/interrupt_avr32.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/can1ce.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/cdef.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/CANDCI.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/conf_board.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/conf_can.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/conf_clock.h create mode 100644 Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/main.c create mode 100644 Master/Masterarbeit/src/CANVerificationTool/doc/Doxyfile (limited to 'Master/Masterarbeit/src/CANVerificationTool') diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool.avrsln b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool.avrsln new file mode 100644 index 0000000..c382db3 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool.avrsln @@ -0,0 +1,20 @@ + +Microsoft Visual Studio Solution File, Format Version 11.00 +# AvrStudio Solution File, Format Version 11.00 +Project("{D1100916-62DA-4D80-A9B4-55A1E7CCEEB3}") = "CANVerificationTool", "CANVerificationTool\CANVerificationTool.avrgccproj", "{C800AB44-876A-11E0-BB03-000C2967FA5F}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|AVR = Debug|AVR + Release|AVR = Release|AVR + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {C800AB44-876A-11E0-BB03-000C2967FA5F}.Debug|AVR.ActiveCfg = Debug|AVR + {C800AB44-876A-11E0-BB03-000C2967FA5F}.Debug|AVR.Build.0 = Debug|AVR + {C800AB44-876A-11E0-BB03-000C2967FA5F}.Release|AVR.ActiveCfg = Release|AVR + {C800AB44-876A-11E0-BB03-000C2967FA5F}.Release|AVR.Build.0 = Release|AVR + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/CANVerificationTool.avrgccproj b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/CANVerificationTool.avrgccproj new file mode 100644 index 0000000..89c0c85 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/CANVerificationTool.avrgccproj @@ -0,0 +1,553 @@ + + + + 2.0 + 5.0 + c800ab44-876a-11e0-bb03-000c2967fa5f + AT32UC3C0512C + uc3c + $(MSBuildProjectName).elf + $(MSBuildProjectDirectory)\$(Configuration) + + $(MSBuildProjectName) + $(MSBuildProjectName) + $(MSBuildProjectName) + Executable + C + True + C:\Programme\Atmel\AVR Studio 5.0\AVR ToolChain\bin + + + com.atmel.avrdbg.tool.avrdragon + JTAG + + com.atmel.avrdbg.tool.avrdragon + AVR Dragon + 00A200019255 + + 127.0.0.1 + 1317 + False + + + JTAG + + 1000000 + 1000000 + 150000 + false + false + 0 + 0 + 0 + 0 + + + + + com.atmel.avrdbg.tool.jtagicemkii + JTAGICE mkII + 070000002558 + + 127.0.0.1 + 1586 + False + + + JTAG + + 0 + 1000000 + 150000 + false + true + 0 + 0 + 0 + 0 + + + + + + + + + + BOARD=UC3C_EK + + + + + ../src + ../src/asf/avr32/boards + ../src/asf/avr32/boards/uc3c_ek + ../src/asf/avr32/drivers/canif + ../src/asf/avr32/drivers/flashc + ../src/asf/avr32/drivers/gpio + ../src/asf/avr32/drivers/intc + ../src/asf/avr32/drivers/pm + ../src/asf/avr32/drivers/scif + ../src/asf/avr32/services/network/can + ../src/asf/avr32/services/network/can/example2/conf + ../src/asf/avr32/utils + ../src/asf/avr32/utils/preprocessor + ../src/asf/common/boards + ../src/asf/common/utils + ../src/config + ../src/asf/avr32/drivers/wdt + ../src/asf/common/services/clock + ../src/asf/avr32/drivers/tc + + + Optimize for size (-Os) + -fdata-sections + True + True + -std=gnu99 -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -mrelax + True + + True + -T../src/asf/avr32/utils/linker_scripts/at32uc3c/0512c/gcc/link_uc3c0512c.lds -Wl,-section-start=.hsb_ram_loc=0xA0000000 -Wl,--relax -Wl,-e,_trampoline + -mrelax + + + ../src + ../src/asf/avr32/boards + ../src/asf/avr32/boards/uc3c_ek + ../src/asf/avr32/drivers/canif + ../src/asf/avr32/drivers/flashc + ../src/asf/avr32/drivers/gpio + ../src/asf/avr32/drivers/intc + ../src/asf/avr32/drivers/pm + ../src/asf/avr32/drivers/scif + ../src/asf/avr32/services/network/can + ../src/asf/avr32/services/network/can/example2/conf + ../src/asf/avr32/utils + ../src/asf/avr32/utils/preprocessor + ../src/asf/common/boards + ../src/asf/common/utils + ../src/config + ../src/asf/avr32/drivers/wdt + ../src/asf/common/services/clock + ../src/asf/avr32/drivers/tc + + + -mrelax + + + ../src + ../src/asf/avr32/boards + ../src/asf/avr32/boards/uc3c_ek + ../src/asf/avr32/drivers/canif + ../src/asf/avr32/drivers/flashc + ../src/asf/avr32/drivers/gpio + ../src/asf/avr32/drivers/intc + ../src/asf/avr32/drivers/pm + ../src/asf/avr32/drivers/scif + ../src/asf/avr32/services/network/can + ../src/asf/avr32/services/network/can/example2/conf + ../src/asf/avr32/utils + ../src/asf/avr32/utils/preprocessor + ../src/asf/common/boards + ../src/asf/common/utils + ../src/config + ../src/asf/avr32/drivers/wdt + ../src/asf/common/services/clock + ../src/asf/avr32/drivers/tc + + + + + + + + + + + BOARD=UC3C_EK + + + + + ../src + ../src/asf/avr32/boards + ../src/asf/avr32/boards/uc3c_ek + ../src/asf/avr32/drivers/canif + ../src/asf/avr32/drivers/flashc + ../src/asf/avr32/drivers/gpio + ../src/asf/avr32/drivers/intc + ../src/asf/avr32/drivers/pm + ../src/asf/avr32/drivers/scif + ../src/asf/avr32/services/network/can + ../src/asf/avr32/services/network/can/example2/conf + ../src/asf/avr32/utils + ../src/asf/avr32/utils/preprocessor + ../src/asf/common/boards + ../src/asf/common/utils + ../src/config + ../src/asf/avr32/drivers/wdt + ../src/asf/common/services/clock + ../src/asf/avr32/drivers/tc + + + -fdata-sections + True + Maximum (-g3) + True + -std=gnu99 -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -mrelax + True + True + -T../src/asf/avr32/utils/linker_scripts/at32uc3c/0512c/gcc/link_uc3c0512c.lds -Wl,-section-start=.hsb_ram_loc=0xA0000000 -Wl,--relax -Wl,-e,_trampoline + -mrelax + + + ../src + ../src/asf/avr32/boards + ../src/asf/avr32/boards/uc3c_ek + ../src/asf/avr32/drivers/canif + ../src/asf/avr32/drivers/flashc + ../src/asf/avr32/drivers/gpio + ../src/asf/avr32/drivers/intc + ../src/asf/avr32/drivers/pm + ../src/asf/avr32/drivers/scif + ../src/asf/avr32/services/network/can + ../src/asf/avr32/services/network/can/example2/conf + ../src/asf/avr32/utils + ../src/asf/avr32/utils/preprocessor + ../src/asf/common/boards + ../src/asf/common/utils + ../src/config + ../src/asf/avr32/drivers/wdt + ../src/asf/common/services/clock + ../src/asf/avr32/drivers/tc + + + -mrelax + + + ../src + ../src/asf/avr32/boards + ../src/asf/avr32/boards/uc3c_ek + ../src/asf/avr32/drivers/canif + ../src/asf/avr32/drivers/flashc + ../src/asf/avr32/drivers/gpio + ../src/asf/avr32/drivers/intc + ../src/asf/avr32/drivers/pm + ../src/asf/avr32/drivers/scif + ../src/asf/avr32/services/network/can + ../src/asf/avr32/services/network/can/example2/conf + ../src/asf/avr32/utils + ../src/asf/avr32/utils/preprocessor + ../src/asf/common/boards + ../src/asf/common/utils + ../src/config + ../src/asf/avr32/drivers/wdt + ../src/asf/common/services/clock + ../src/asf/avr32/drivers/tc + + + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/Framework.config b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/Framework.config new file mode 100644 index 0000000..b8dcc18 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/Framework.config @@ -0,0 +1,71 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/__TemplateIcon.png b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/__TemplateIcon.png new file mode 100644 index 0000000..c9b04d5 Binary files /dev/null and b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/__TemplateIcon.png differ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/AVR_COMPILER.H b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/AVR_COMPILER.H new file mode 100644 index 0000000..0531c1f --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/AVR_COMPILER.H @@ -0,0 +1,2 @@ +#include "compiler.h" + diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAN1c1.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAN1c1.c new file mode 100644 index 0000000..78b6913 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAN1c1.c @@ -0,0 +1,657 @@ + +#include "CAN1c1.h" +#include "CAND1c1.h" +#include "CANIF1c1.h" + + +void CAN_vNoRxIndication_Cb( CAN_tenMessage enMsg, CAN_tId CanId ) +{ +} + +void CAN_vNoPreTx_Cb( CAN_tenMessage enMsg ) +{ +} + +/**********************/ +/*Signal Konfiguration*/ +/**********************/ +#define MakeTxMessages() \ + +#define MakeTxMessagesEnd() \ + +#define MakeRxMessages() \ + +#define MakeRxMessagesEnd() \ + +#define MakeTxMsg( MSG_ID, CAN_CH, CAN_ID, DLC, TX_MODE, CYCLE, PRE_TX_CALLBACK ) \ + +#define MakeRxMsg( MSG_ID, CAN_CH, CAN_ID_START, CAN_ID_END, DLC, TIMEOUT, RX_CALLBACK ) \ + +#define MakeSignal( MSG_ID, SIG_ID, START_BIT, SIZE, DEFAULT ) \ + { MSG_ID, START_BIT, SIZE, DEFAULT }, \ + +#define MakeTxMsgEnd() \ + +#define MakeRxMsgEnd() \ + +const CAN__tstSignalConfig CAN__astSignalConfig[CAN_nenSig_NoOfSignals] = +{ + CAN_MakeDbConfig +}; + +#undef MakeTxMsg +#undef MakeTxMsgEnd +#undef MakeRxMsg +#undef MakeRxMsgEnd +#undef MakeSignal +#undef MakeTxMessages +#undef MakeTxMessagesEnd +#undef MakeRxMessages +#undef MakeRxMessagesEnd + + +/*****************************************************/ +/*extern-Deklaration der Rx/Tx-Callback-Funktionen */ +/*****************************************************/ +#define MakeTxMessages() \ + +#define MakeTxMessagesEnd() \ + +#define MakeRxMessages() \ + +#define MakeRxMessagesEnd() \ + +#define MakeTxMsg( MSG_ID, CAN_CH, CAN_ID, DLC, TX_MODE, CYCLE, PRE_TX_CALLBACK ) \ + extern void PRE_TX_CALLBACK( CAN_tenMessage enMsgId ); \ + +#define MakeRxMsg( MSG_ID, CAN_CH, CAN_ID_START, CAN_ID_END, DLC, TIMEOUT, RX_CALLBACK ) \ + extern void RX_CALLBACK( CAN_tenMessage enMsgId, CAN_tId CanId ); \ + +#define MakeSignal( MSG_ID, SIG_ID, START_BIT, SIZE, DEFAULT ) \ + +#define MakeTxMsgEnd() \ + +#define MakeRxMsgEnd() \ + + CAN_MakeDbConfig + +#undef MakeTxMsg +#undef MakeTxMsgEnd +#undef MakeRxMsg +#undef MakeRxMsgEnd +#undef MakeSignal +#undef MakeTxMessages +#undef MakeTxMessagesEnd +#undef MakeRxMessages +#undef MakeRxMessagesEnd + +/******************************************/ +/*Message Daten Speicher (RAM) */ +/******************************************/ +#define MakeTxMessages() \ + +#define MakeTxMessagesEnd() \ + +#define MakeRxMessages() \ + +#define MakeRxMessagesEnd() \ + +#define MakeTxMsg( MSG_ID, CAN_CH, CAN_ID, DLC, TX_MODE, CYCLE, PRE_TX_CALLBACK ) \ + uint8_t CAN__au8MsgData_##MSG_ID[DLC]; \ + +#define MakeRxMsg( MSG_ID, CAN_CH, CAN_ID_START, CAN_ID_END, DLC, TIMEOUT, RX_CALLBACK ) \ + uint8_t CAN__au8MsgData_##MSG_ID[DLC]; \ + +#define MakeSignal( MSG_ID, SIG_ID, START_BIT, SIZE, DEFAULT ) \ + +#define MakeTxMsgEnd() \ + +#define MakeRxMsgEnd() \ + + CAN_MakeDbConfig + +#undef MakeTxMsg +#undef MakeTxMsgEnd +#undef MakeRxMsg +#undef MakeRxMsgEnd +#undef MakeSignal +#undef MakeTxMessages +#undef MakeTxMessagesEnd +#undef MakeRxMessages +#undef MakeRxMessagesEnd + + +/***************************/ +/*Rx-Messages Konfiguration*/ +/***************************/ +#define MakeTxMessages() \ + +#define MakeTxMessagesEnd() \ + +#define MakeRxMessages() \ + +#define MakeRxMessagesEnd() \ + +#define MakeTxMsg( MSG_ID, CAN_CH, CAN_ID, DLC, TX_MODE, CYCLE, PRE_TX_CALLBACK ) \ + +#define MakeRxMsg( MSG_ID, CAN_CH, CAN_ID_START, CAN_ID_END, DLC, TIMEOUT, RX_CALLBACK ) \ + { DLC, TIMEOUT/CAN__nPollCycle, CAN__au8MsgData_##MSG_ID, RX_CALLBACK }, \ + +#define MakeSignal( MSG_ID, SIG_ID, START_BIT, SIZE, DEFAULT ) \ + +#define MakeTxMsgEnd() \ + +#define MakeRxMsgEnd() \ + +const CAN__tstRxMessageConfig CAN__astRxMessageConfig[CAN_nenMsg_NoOfRxMessages] = +{ + CAN_MakeDbConfig +}; + +#undef MakeTxMsg +#undef MakeTxMsgEnd +#undef MakeRxMsg +#undef MakeRxMsgEnd +#undef MakeSignal +#undef MakeTxMessages +#undef MakeTxMessagesEnd +#undef MakeRxMessages +#undef MakeRxMessagesEnd + + +/***************************/ +/*Tx-Messages Konfiguration*/ +/***************************/ +#define MakeTxMessages() \ + +#define MakeTxMessagesEnd() \ + +#define MakeRxMessages() \ + +#define MakeRxMessagesEnd() \ + +#define MakeTxMsg( MSG_ID, CAN_CH, CAN_ID, DLC, TX_MODE, CYCLE, PRE_TX_CALLBACK ) \ + { CAN_CH, DLC, CYCLE/CAN__nPollCycle, CAN__au8MsgData_##MSG_ID, PRE_TX_CALLBACK }, \ + +#define MakeRxMsg( MSG_ID, CAN_CH, CAN_ID_START, CAN_ID_END, DLC, TIMEOUT, RX_CALLBACK ) \ + +#define MakeSignal( MSG_ID, SIG_ID, START_BIT, SIZE, DEFAULT ) \ + +#define MakeTxMsgEnd() \ + +#define MakeRxMsgEnd() \ + +const CAN__tstTxMessageConfig CAN__astTxMessageConfig[CAN_nenMsg_NoOfTxMessages] = +{ + CAN_MakeDbConfig +}; + +#undef MakeTxMsg +#undef MakeTxMsgEnd +#undef MakeRxMsg +#undef MakeRxMsgEnd +#undef MakeSignal +#undef MakeTxMessages +#undef MakeTxMessagesEnd +#undef MakeRxMessages +#undef MakeRxMessagesEnd + +/***************************/ +/*Tx CAN-ID Konfiguration */ +/***************************/ +#define MakeTxMessages() \ + +#define MakeTxMessagesEnd() \ + +#define MakeRxMessages() \ + +#define MakeRxMessagesEnd() \ + +#define MakeTxMsg( MSG_ID, CAN_CH, CAN_ID, DLC, TX_MODE, CYCLE, PRE_TX_CALLBACK ) \ + CAN_ID, \ + +#define MakeRxMsg( MSG_ID, CAN_CH, CAN_ID_START, CAN_ID_END, DLC, TIMEOUT, RX_CALLBACK ) \ + +#define MakeSignal( MSG_ID, SIG_ID, START_BIT, SIZE, DEFAULT ) \ + +#define MakeTxMsgEnd() \ + +#define MakeRxMsgEnd() \ + +CAN_tTxId CAN__aTxIds[CAN_nenMsg_NoOfTxMessages] = +{ + CAN_MakeDbConfig +}; + +#undef MakeTxMsg +#undef MakeTxMsgEnd +#undef MakeRxMsg +#undef MakeRxMsgEnd +#undef MakeSignal +#undef MakeTxMessages +#undef MakeTxMessagesEnd +#undef MakeRxMessages +#undef MakeRxMessagesEnd + + + +/***************************/ +/*Rx CAN-ID Konfiguration */ +/***************************/ +#define MakeTxMessages() \ + +#define MakeTxMessagesEnd() \ + +#define MakeRxMessages() \ + +#define MakeRxMessagesEnd() \ + +#define MakeTxMsg( MSG_ID, CAN_CH, CAN_ID, DLC, TX_MODE, CYCLE, PRE_TX_CALLBACK ) \ + +#define MakeRxMsg( MSG_ID, CAN_CH, CAN_ID_START, CAN_ID_END, DLC, TIMEOUT, RX_CALLBACK ) \ + { CAN_ID_START, CAN_ID_END }, \ + +#define MakeSignal( MSG_ID, SIG_ID, START_BIT, SIZE, DEFAULT ) \ + +#define MakeTxMsgEnd() \ + +#define MakeRxMsgEnd() \ + +CAN__tstRxCanIds CAN__astRxIds[CAN_nenMsg_NoOfRxMessages] = +{ + CAN_MakeDbConfig +}; + +#undef MakeTxMsg +#undef MakeTxMsgEnd +#undef MakeRxMsg +#undef MakeRxMsgEnd +#undef MakeSignal +#undef MakeTxMessages +#undef MakeTxMessagesEnd +#undef MakeRxMessages +#undef MakeRxMessagesEnd + +/******************************/ +/* Timeout Counter */ +/******************************/ +uint16_t CAN__au16TimeoutCounter[CAN_nenMsg_NoOfRxMessages]; + +void CAN__vResetTimeoutCounter( CAN_tenMessage u8RxMsgId ) +{ + uint8_t u8MsgIndex; + + if( u8RxMsgId >= CAN_nenMsg_RxMessagesStart + && u8RxMsgId <= CAN_nenMsg_RxMessagesEnd + ) + { + u8MsgIndex = CAN__u8RxMsgIdToMsgIndex( u8RxMsgId ); + CAN__au16TimeoutCounter[u8MsgIndex] = CAN__astRxMessageConfig[u8MsgIndex].u16Timout; + } +} + +bool CAN_boIsTimeout( CAN_tenMessage u8RxMsgId ) +{ + uint8_t u8MsgIndex; + + if( u8RxMsgId >= CAN_nenMsg_RxMessagesStart + && u8RxMsgId <= CAN_nenMsg_RxMessagesEnd + ) + { + u8MsgIndex = CAN__u8RxMsgIdToMsgIndex( u8RxMsgId ); + return CAN__au16TimeoutCounter[ u8MsgIndex ] == 0; + } + return false; +} + +void CAN__vCountAllTimeoutCounters( void ) +{ + uint8_t u8MsgIndex; + + for( u8MsgIndex=0; u8MsgIndex= CAN_nenMsg_RxMessagesStart + && u8TxMsgId <= CAN_nenMsg_RxMessagesEnd + ) + { + u8MsgIndex = CAN__u8TxMsgIdToMsgIndex( u8TxMsgId ); + CAN__abiFirstValueFlags[ u8MsgIndex >> 3 ] |= 1 << (u8MsgIndex & 0x07); + } +} + +void CAN__vClearFirstValueFlag( CAN_tenMessage u8TxMsgId ) +{ + uint8_t u8MsgIndex; + + if( u8TxMsgId >= CAN_nenMsg_RxMessagesStart + && u8TxMsgId <= CAN_nenMsg_RxMessagesEnd + ) + { + u8MsgIndex = CAN__u8TxMsgIdToMsgIndex( u8TxMsgId ); + CAN__abiFirstValueFlags[ u8MsgIndex >> 3 ] &= ~(1 << (u8MsgIndex & 0x07)); + } +} + +bool CAN_boIsFirstValue( CAN_tenMessage u8TxMsgId ) +{ + uint8_t u8MsgIndex; + + if( u8TxMsgId >= CAN_nenMsg_RxMessagesStart + && u8TxMsgId <= CAN_nenMsg_RxMessagesEnd + ) + { + u8MsgIndex = CAN__u8TxMsgIdToMsgIndex( u8TxMsgId ); + return (CAN__abiFirstValueFlags[ u8MsgIndex >> 3 ] & (1 << (u8MsgIndex & 0x07))) != 0; + } + return false; +} + + +/***********************************/ +/*Send-Request Flags */ +/***********************************/ +uint8_t CAN__abiSendRequestFlags[ (CAN_nenMsg_NoOfTxMessages + 7) / 8 ]; + +void CAN__vInitAllSendRequestFlags( void ) +{ + uint8_t u8Index; + + for( u8Index=0; u8Index= CAN_nenMsg_TxMessagesStart + && enTxMsgId <= CAN_nenMsg_TxMessagesEnd + ) + { + u8MsgIndex = CAN__u8TxMsgIdToMsgIndex( enTxMsgId ); + CAN__abiSendRequestFlags[ u8MsgIndex >> 3 ] |= 1 << (u8MsgIndex & 0x07); + } +} + +void CAN__vClearSendRequestFlag( CAN_tenMessage enTxMsgId ) +{ + uint8_t u8MsgIndex; + + if( enTxMsgId >= CAN_nenMsg_TxMessagesStart + && enTxMsgId <= CAN_nenMsg_TxMessagesEnd + ) + { + u8MsgIndex = CAN__u8TxMsgIdToMsgIndex( enTxMsgId ); + CAN__abiSendRequestFlags[ u8MsgIndex >> 3 ] &= ~(1 << (u8MsgIndex & 0x07)); + } +} + +bool CAN__boIsSendRequestActive( CAN_tenMessage enTxMsgId ) +{ + uint8_t u8MsgIndex; + bool boIsSendRequestActive = false; + + if( enTxMsgId >= CAN_nenMsg_TxMessagesStart + && enTxMsgId <= CAN_nenMsg_TxMessagesEnd + ) + { + u8MsgIndex = CAN__u8TxMsgIdToMsgIndex( enTxMsgId ); + boIsSendRequestActive = ( CAN__abiSendRequestFlags[ u8MsgIndex >> 3 ] & 1 << (u8MsgIndex & 0x07) ) != 0; + } + return boIsSendRequestActive; +} + + +/***********************************/ +/*Cyclic Send-Request Flags */ +/***********************************/ + +uint8_t CAN__abiCyclicSendFlags[ (CAN_nenMsg_NoOfTxMessages + 7) / 8 ]; + +void CAN__vInitAllCyclicSendFlags( void ) +{ + uint8_t u8Index; + + for( u8Index=0; u8Index= CAN_nenMsg_TxMessagesStart + && enTxMsgId <= CAN_nenMsg_TxMessagesEnd + ) + { + u8MsgIndex = CAN__u8TxMsgIdToMsgIndex( enTxMsgId ); + CAN__abiCyclicSendFlags[ u8MsgIndex >> 3 ] |= 1 << (u8MsgIndex & 0x07); + } +} + +void CAN__vClearCyclicSendFlag( CAN_tenMessage enTxMsgId ) +{ + uint8_t u8MsgIndex; + + if( enTxMsgId >= CAN_nenMsg_TxMessagesStart + && enTxMsgId <= CAN_nenMsg_TxMessagesEnd + ) + { + u8MsgIndex = CAN__u8TxMsgIdToMsgIndex( enTxMsgId ); + CAN__abiCyclicSendFlags[ u8MsgIndex >> 3 ] &= ~(1 << (u8MsgIndex & 0x07)); + } +} + +bool CAN__boIsCyclicSendActive( CAN_tenMessage enTxMsgId ) +{ + uint8_t u8MsgIndex; + + if( enTxMsgId >= CAN_nenMsg_TxMessagesStart + && enTxMsgId <= CAN_nenMsg_TxMessagesEnd + ) + { + u8MsgIndex = CAN__u8TxMsgIdToMsgIndex( enTxMsgId ); + return ( CAN__abiCyclicSendFlags[ u8MsgIndex >> 3 ] & 1 << (u8MsgIndex & 0x07) ) != 0; + } + return false; +} + +/**********************************************/ +/*Zuordnung CAN-Konfiguration zu CAN-Channels */ +/**********************************************/ + +#define MakeCanChannel( CAN_CH, BAUD, RX_CALLBACK, TX_CALLBACK ) \ + { BAUD, RX_CALLBACK, TX_CALLBACK }, \ + +#define MakeMsgBox( MSG_BOX_ID, ID_VALUE, ID_MASK, MB_MODE ) \ + +#define MakeRxMsg( MSG_ID ) \ + +#define MakeMsgBoxEnd() \ + +#define MakeCanChannelEnd() \ + +const CAN__tstCanChannelConfig CAN__astCanChannelConfig[CAN__nenCh_NoOfChannels] = +{ + CAN_MessageBoxConfig +}; + +#undef MakeCanChannel +#undef MakeMsgBox +#undef MakeRxMsg +#undef MakeMsgBoxEnd +#undef MakeCanChannelEnd + + +/*****************************************/ +/*Zuordnung Rx-Message.IDs zu Msg.-Box */ +/*****************************************/ +#define MakeCanChannel( CAN_CH, BAUD, RX_CALLBACK, TX_CALLBACK ) \ + +#define MakeMsgBox( MSG_BOX_ID, ID_VALUE, ID_MASK, MB_MODE ) \ + CAN_tenMessage CAN__ap##MSG_BOX_ID##_RxMsgList[] = { \ + +#define MakeRxMsg( MSG_ID ) \ + MSG_ID, + +#define MakeMsgBoxEnd() \ + CAN_nenMsg_Invalid }; \ + +#define MakeCanChannelEnd() \ + +CAN_MessageBoxConfig + +#undef MakeCanChannel +#undef MakeMsgBox +#undef MakeRxMsg +#undef MakeMsgBoxEnd +#undef MakeCanChannelEnd + + +/*****************************************/ +/*Message-Box Konfiguration */ +/*****************************************/ +#define MakeCanChannel( CAN_CH, BAUD, RX_CALLBACK, TX_CALLBACK ) \ + +#define MakeMsgBox( MSG_BOX_ID, ID_VALUE, ID_MASK, MB_MODE ) \ + { ID_VALUE, ID_MASK, MB_MODE, CAN__ap##MSG_BOX_ID##_RxMsgList }, \ + +#define MakeRxMsg( MSG_ID ) \ + +#define MakeMsgBoxEnd() \ + +#define MakeCanChannelEnd() \ + +const CAN__tstMessageBoxConfig CAN__astMessageBoxConfig[CAN__nenMb_NoOfMessageBoxes] = +{ + CAN_MessageBoxConfig +}; + + +#undef MakeCanChannel +#undef MakeMsgBox +#undef MakeRxMsg +#undef MakeMsgBoxEnd +#undef MakeCanChannelEnd + + + +void CAN_vInit( void ) +{ +// CAN__vInitAllMsgDataBuffer(); +// CAN__vInitAllSigValues(); + CAN__vInitAllTimeoutCounters(); + CAN__vInitAllCycleCounter(); + CAN__vInitAllFirstValueFlags(); + CAN__vInitAllSendRequestFlags(); + CAN__vInitAllCyclicSendFlags(); + + CAND_vInit(); + CANIF_vInit(); +} + +void CAN_vMain( void ) +{ + CANIF_vMain(); +} + diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAN1c1.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAN1c1.h new file mode 100644 index 0000000..b1eac98 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAN1c1.h @@ -0,0 +1,322 @@ +#ifndef CAN_C1_H +#define CAN_C1_H + + +#include "cdef.h" +#include "CAN1ce.h" + +/************************/ +/*global type definition*/ +/************************/ +typedef uint16_t CAN_tId; +typedef uint16_t CAN_tTxId; + +typedef struct +{ + CAN_tTxId StartId; + CAN_tTxId EndId; +}CAN__tstRxCanIds; + + +/**********************/ +/*Signal IDs (enum) */ +/**********************/ +#define MakeTxMessages() \ + +#define MakeTxMessagesEnd() \ + +#define MakeRxMessages() \ + +#define MakeRxMessagesEnd() \ + +#define MakeTxMsg( MSG_ID, CAN_CH, CAN_ID, DLC, TX_MODE, CYCLE, PRE_TX_CALLBACK ) \ + +#define MakeRxMsg( MSG_ID, CAN_CH, CAN_ID_START, CAN_ID_END, DLC, TIMEOUT, RX_CALLBACK ) \ + +#define MakeSignal( MSG_ID, SIG_ID, START_BIT, SIZE, DEFAULT ) \ + SIG_ID, \ + +#define MakeTxMsgEnd() \ + +#define MakeRxMsgEnd() \ + + + +typedef enum +{ + CAN_MakeDbConfig + + CAN_nenSig_NoOfSignals, + CAN_nenSig_Invalid +}CAN_tenSignal; + +#undef MakeTxMsg +#undef MakeRxMsg +#undef MakeSignal +#undef MakeTxMsgEnd +#undef MakeRxMsgEnd +#undef MakeTxMessages +#undef MakeTxMessagesEnd +#undef MakeRxMessages +#undef MakeRxMessagesEnd + +/**********************/ +/*Message IDs (enum) */ +/**********************/ +#define MakeTxMessages() \ + CAN_nenMsg_TxMessagesStart, \ + CAN__nenMsg_DummyTxMessagesStart = CAN_nenMsg_TxMessagesStart -1, \ + +#define MakeTxMessagesEnd() \ + CAN__nenMsg_DummyTxMessagesEnd, \ + CAN_nenMsg_TxMessagesEnd = CAN__nenMsg_DummyTxMessagesEnd-1, \ + +#define MakeRxMessages() \ + CAN_nenMsg_RxMessagesStart, \ + CAN__nenMsg_DummyRxMessagesStart = CAN_nenMsg_RxMessagesStart -1, \ + +#define MakeRxMessagesEnd() \ + CAN__nenMsg_DummyRxMessagesEnd, \ + CAN_nenMsg_RxMessagesEnd = CAN__nenMsg_DummyRxMessagesEnd-1, \ + +#define MakeTxMsg( MSG_ID, CAN_CH, CAN_ID, DLC, TX_MODE, CYCLE, PRE_TX_CALLBACK ) \ + MSG_ID, + +#define MakeRxMsg( MSG_ID, CAN_CH, CAN_ID_START, CAN_ID_END, DLC, TIMEOUT, RX_CALLBACK ) \ + MSG_ID, + +#define MakeSignal( MSG_ID, SIG_ID, START_BIT, SIZE, DEFAULT ) \ + +#define MakeTxMsgEnd() \ + +#define MakeRxMsgEnd() \ + + +typedef enum +{ + CAN_MakeDbConfig + + CAN_nenMsg_NoOfMessages, + CAN_nenMsg_Invalid +}CAN_tenMessage; + +#undef MakeTxMsg +#undef MakeTxMsgEnd +#undef MakeRxMsg +#undef MakeRxMsgEnd +#undef MakeSignal +#undef MakeTxMessages +#undef MakeTxMessagesEnd +#undef MakeRxMessages +#undef MakeRxMessagesEnd + +#define CAN_nenMsg_NoOfTxMessages (CAN_nenMsg_TxMessagesEnd - CAN_nenMsg_TxMessagesStart + 1) +#define CAN_nenMsg_NoOfRxMessages (CAN_nenMsg_RxMessagesEnd - CAN_nenMsg_RxMessagesStart + 1) + +#define CAN__enMsgIndexToRxMsgId( u8MSG_INDEX ) ( (u8MSG_INDEX) + CAN_nenMsg_RxMessagesStart ) +#define CAN__enMsgIndexToTxMsgId( u8MSG_INDEX ) ( (u8MSG_INDEX) + CAN_nenMsg_TxMessagesStart ) +#define CAN__u8RxMsgIdToMsgIndex( enMSG_ID ) ( (enMSG_ID) - CAN_nenMsg_RxMessagesStart ) +#define CAN__u8TxMsgIdToMsgIndex( enMSG_ID ) ( (enMSG_ID) - CAN_nenMsg_TxMessagesStart ) + +#define CAN__boIsTxMsg( enMSG_ID ) ( (enMSG_ID) >= CAN_nenMsg_TxMessagesStart && (enMSG_ID) <= CAN_nenMsg_TxMessagesEnd ) +#define CAN__boIsRxMsg( enMSG_ID ) ( (enMSG_ID) >= CAN_nenMsg_RxMessagesStart && (enMSG_ID) <= CAN_nenMsg_RxMessagesEnd ) +#define CAN__boIsMsg( enMSG_ID ) ( CAN__boIsRxMsg( enMSG_ID ) || CAN__boIsTxMsg( enMSG_ID ) ) + +#define CAN_boIsSignal( enSIG_ID ) ( (enSIG_ID) >= 0 && (enSIG_ID) < CAN_nenSig_NoOfSignals ) + +/**********************/ +/*Signal Konfiguration*/ +/**********************/ +typedef struct +{ + uint16_t enMsgId; + uint8_t u8StartBit; + uint8_t u8BitSize; + uint32_t u32DefaultValue; +}CAN__tstSignalConfig; + +extern const CAN__tstSignalConfig CAN__astSignalConfig[CAN_nenSig_NoOfSignals]; + +/******************************************/ +/* Prototypes of empty callback fucntions */ +/******************************************/ +void CAN_vNoRxIndication_Cb( CAN_tenMessage enMsg, CAN_tId CanId ); +void CAN_vNoPreTx_Cb( CAN_tenMessage enMsg ); + +/**************************/ +/*Rx Message Konfiguration*/ +/**************************/ +typedef struct +{ + uint8_t u8Dlc; + uint16_t u16Timout; + volatile uint8_t *pu8Data; + void (*pfctRxIndicationCb)( CAN_tenMessage enMsgId, CAN_tId enCanId ); +}CAN__tstRxMessageConfig; + +extern const CAN__tstRxMessageConfig CAN__astRxMessageConfig[CAN_nenMsg_NoOfRxMessages]; + + +/**************************/ +/*Tx Message Konfiguration*/ +/**************************/ +typedef struct +{ + uint8_t enCanChannel; + uint8_t u8Dlc; + uint16_t u16Cycle; + volatile uint8_t *pu8Data; + void (*pfctPreTransmitCb)( CAN_tenMessage enMsgId ); +}CAN__tstTxMessageConfig; + +extern const CAN__tstTxMessageConfig CAN__astTxMessageConfig[CAN_nenMsg_NoOfTxMessages]; + +extern CAN_tTxId CAN__aTxIds[CAN_nenMsg_NoOfTxMessages]; +extern CAN__tstRxCanIds CAN__astRxIds[CAN_nenMsg_NoOfRxMessages]; + +/******************************/ +/* Timeout Counter */ +/******************************/ +void CAN__vResetTimeoutCounter( CAN_tenMessage u8RxMsgId ); +bool CAN_boIsTimeout( CAN_tenMessage u8RxMsgId ); +void CAN__vCountAllTimeoutCounters( void ); +void CAN__vInitAllTimeoutCounters( void ); + +/******************************/ +/* Cycle Counter */ +/******************************/ +void CAN__vCheckAllCycleCounter( void ); + +/***********************************/ +/*First-Value-Flags */ +/***********************************/ +void CAN__vSetFirstValueFlag( CAN_tenMessage u8TxMsgId ); +void CAN__vClearFirstValueFlag( CAN_tenMessage u8TxMsgId ); +bool CAN_boIsFirstValue( CAN_tenMessage u8TxMsgId ); + +/***********************************/ +/*Send-Request Flags */ +/***********************************/ +void CAN__vSetSendRequestFlag( CAN_tenMessage enMessage ); +void CAN__vClearSendRequestFlag( CAN_tenMessage enMessage ); +bool CAN__boIsSendRequestActive( CAN_tenMessage enMessage ); + +/***********************************/ +/*Cyclic Send-Request Flags */ +/***********************************/ +void CAN__vSetCyclicSendFlag( CAN_tenMessage enMessage ); +void CAN__vClearCyclicSendFlag( CAN_tenMessage enMessage ); +bool CAN__boIsCyclicSendActive( CAN_tenMessage enMessage ); + + + +/*****************************/ +/*CAN-HW-Channel IDs (enum) */ +/*****************************/ +#define MakeCanChannel( CAN_CH, BAUD, RX_CALLBACK, TX_CALLBACK ) \ + CAN_CH, \ + +#define MakeMsgBox( MSG_BOX_ID, ID_VALUE, ID_MASK, MB_MODE ) \ + +#define MakeRxMsg( MSG_ID ) \ + +#define MakeMsgBoxEnd() \ + +#define MakeCanChannelEnd() \ + +typedef enum +{ + CAN_MessageBoxConfig + + CAN__nenCh_NoOfChannels, + CAN__nenCh_Invalid +}CAN_tenChannel; + + +#undef MakeCanChannel +#undef MakeMsgBox +#undef MakeRxMsg +#undef MakeMsgBoxEnd +#undef MakeCanChannelEnd + + +/***********************/ +/*Msg.-Box IDs (enum) */ +/***********************/ +#define MakeCanChannel( CAN_CH, BAUD, RX_CALLBACK, TX_CALLBACK ) \ + +#define MakeMsgBox( MSG_BOX_ID, ID_VALUE, ID_MASK, MB_MODE ) \ + MSG_BOX_ID, \ + +#define MakeRxMsg( MSG_ID ) \ + +#define MakeMsgBoxEnd() \ + +#define MakeCanChannelEnd() \ + +typedef enum +{ + CAN_MessageBoxConfig + + CAN__nenMb_NoOfMessageBoxes, + CAN__nenMb_Invalid +}CAN__tenMessageBox; + + +#undef MakeCanChannel +#undef MakeMsgBox +#undef MakeRxMsg +#undef MakeMsgBoxEnd +#undef MakeCanChannelEnd + +typedef enum +{ + CAN__nenMbMode_Rx = 0, + CAN__nenMbMode_Tx = 1, + CAN__nenMbMode_NotUsed = 2 +}CAN__tenMbMode; + +typedef struct +{ + CAN_tTxId IdValue; + CAN_tTxId IdMask; + const CAN__tenMbMode enMode; + const CAN_tenMessage *(paenRxMsgIdList); +}CAN__tstMessageBoxConfig; + +extern const CAN__tstMessageBoxConfig CAN__astMessageBoxConfig[CAN__nenMb_NoOfMessageBoxes]; + + +typedef struct +{ + uint8_t au8Data[8]; + uint8_t u8Dlc; + CAN_tId CanId; +}CAN_tstMessage; + + + + + +/**********************************************/ +/*Konfiguration zu CAN-Channels */ +/**********************************************/ +typedef void (*CAN__tpfctTxConfirmation)(CAN_tenChannel enChannel, CAN_tId CanId); +typedef void (*CAN__tpfctRxIndication)( CAN_tenChannel enChannel, CAN__tenMessageBox enMsgBox, CAN_tstMessage *pstMessage ); + +typedef struct +{ + uint32_t u32Baudrate; + CAN__tpfctRxIndication pfctRxIndication; + CAN__tpfctTxConfirmation pfctTxConfirmation; +} CAN__tstCanChannelConfig; + +extern const CAN__tstCanChannelConfig CAN__astCanChannelConfig[CAN__nenCh_NoOfChannels]; + + +void CAN_vInit( void ); +void CAN_vMain( void ); + + + +#endif /*CAN_C1_H*/ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAND1c1.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAND1c1.c new file mode 100644 index 0000000..e7214f2 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAND1c1.c @@ -0,0 +1,314 @@ + +#include "cdef.h" +#include "CAND1c1.h" +#include "CANIF1c1.h" +#ifndef _WINECU_ +#include "CANDCI.h" + +//! Local Mob Declaration +volatile can_msg_t mob_ram_ch[CAN__nenCh_NoOfChannels][NB_MOB_CHANNEL]; + +void can_out_callback_channel0(U8 handle, U8 event,U8 dir); +void can_out_callback_channel1(U8 handle, U8 event,U8 dir); + +#endif /* !_WINECU */ + + +/*Konfigurationstest*/ +compile_time_assert( CAN__nenMb_NoOfMessageBoxes == 32 ); +compile_time_assert( CAN__nenCh_NoOfChannels == 2 ); + + + +void CAND_vInit( void ) /*CAN_Zelle Initialisieren noch nicht starten*/ +{ +#ifndef _WINECU_ + U8 u8Mode=0; + U8 u8ChIndex=0; + U8 u8MobIndex =0; + + // Setup the generic clock for CAN + scif_gc_setup(AVR32_SCIF_GCLK_CANIF, + SCIF_GCCTRL_OSC0, + AVR32_SCIF_GC_NO_DIV_CLOCK, + 0); + // Now enable the generic clock + scif_gc_enable(AVR32_SCIF_GCLK_CANIF); + static const gpio_map_t CAN_GPIO_MAP = { + {AVR32_CANIF_RXLINE_0_0_PIN, AVR32_CANIF_RXLINE_0_0_FUNCTION}, + {AVR32_CANIF_TXLINE_0_0_PIN, AVR32_CANIF_TXLINE_0_0_FUNCTION} + , + {AVR32_CANIF_RXLINE_1_2_PIN, AVR32_CANIF_RXLINE_1_2_FUNCTION}, + {AVR32_CANIF_TXLINE_1_2_PIN, AVR32_CANIF_TXLINE_1_2_FUNCTION} + }; + // Assign GPIO to CAN. + gpio_enable_module(CAN_GPIO_MAP, + sizeof(CAN_GPIO_MAP) / sizeof(CAN_GPIO_MAP[0])); + + for (u8ChIndex=0; u8ChIndexid = CAN__astMessageBoxConfig[handle+0*NB_MOB_CHANNEL].IdValue; + appli_tx_msg[0][handle].can_msg->id_mask = CAN__astMessageBoxConfig[handle+0*NB_MOB_CHANNEL].IdMask; + can_rx(0,handle,appli_tx_msg[0][handle].req_type,appli_tx_msg[0][handle].can_msg); + break; + // Transmission + case CAN__nenMbMode_Tx: + u16CanId = can_get_mob_id(0,handle); + CANIF_vTxConfirmation(0,u16CanId); + CANIF_mob_clr_dlc(0,handle); + CANIF_clr_mob(0,handle); + break; + default: + break; + } +} + + + +/*! \brief CAN Call Back when message is transmitted + * + */ +void can_out_callback_channel1(U8 handle, U8 event,U8 dir) +{ + uint16_t u16CanId; + uint8_t u8dlc; + CAN_tstMessage stMessage; + + //gpio_tgl_gpio_pin(LED2_GPIO); + switch(dir) + { // Reception + case CAN__nenMbMode_Rx: + u8dlc = can_get_mob_dlc(1,handle); + stMessage.u8Dlc = u8dlc; + stMessage.CanId = can_get_mob_id(1,handle); + for (U8 i=0; iid = CAN__astMessageBoxConfig[handle+1*NB_MOB_CHANNEL].IdValue; + appli_tx_msg[1][handle].can_msg->id_mask = CAN__astMessageBoxConfig[handle+1*NB_MOB_CHANNEL].IdMask; + can_rx(1,handle,appli_tx_msg[1][handle].req_type,appli_tx_msg[1][handle].can_msg); + break; + // Transmission + case CAN__nenMbMode_Tx: + u16CanId = can_get_mob_id(1,handle); + CANIF_vTxConfirmation(1,u16CanId); + CANIF_mob_clr_dlc(1,handle); + CANIF_clr_mob(1,handle); + break; + default: + break; + } +} + +#endif /* !WINECU */ + +bool CAND_boSend( CAN_tenChannel enChannel, CAN_tstMessage *pstMessage ) +{ +#ifdef _WINECU_ + HW_CAN_tstCanMessage stCanMsg; + + stCanMsg.u32Id = pstMessage->CanId; + stCanMsg.u8Length = pstMessage->u8Dlc; + + *((uint32_t *)&(stCanMsg.au8Data[0]) ) = *( (uint32_t *)&pstMessage->au8Data[0] ); + *((uint32_t *)&(stCanMsg.au8Data[4]) ) = *( (uint32_t *)&pstMessage->au8Data[4] ); + + stCanMsg.boRemoteFrame = false; + + HW_CAN_vTransmit( enChannel, &stCanMsg ); + + /*Callback an CANIF schicken*/ + CANIF_vTxConfirmation( enChannel, pstMessage->CanId ); + + return false; +#else /* !_WINECU */ + U8 dir; + U8 u8Dlc=0; + bool success = false; + + for(U8 u8MobIndex=0; (u8MobIndex < NB_MOB_CHANNEL) && (!success) ; u8MobIndex++) + { + dir = CANIF_mob_get_dir(enChannel,u8MobIndex); + if(dir == CAN__nenMbMode_Tx) + { + appli_tx_msg[enChannel][u8MobIndex].can_msg->id = pstMessage->CanId; + u8Dlc = pstMessage->u8Dlc; + appli_tx_msg[enChannel][u8MobIndex].dlc = u8Dlc; + for(U8 i=0; idata.u8[i] = pstMessage->au8Data[i]; + } + can_tx(enChannel, + appli_tx_msg[enChannel][u8MobIndex].handle, + appli_tx_msg[enChannel][u8MobIndex].dlc, + appli_tx_msg[enChannel][u8MobIndex].req_type, + appli_tx_msg[enChannel][u8MobIndex].can_msg); + success = true; + } + } + return success; +#endif /* !_WINECU */ +} + +void CAND_boGetOverflow( CAN_tenChannel enChannel ) +{ +} + +#ifdef _WINECU_ +void CAND__vRxInterruptCh0( HW_CAN_tstCanMessage* pMsg ) +{ + CAN__tenMessageBox enMbId; + CAN_tstMessage stCanMsg; + + for( enMbId = CAN_enCh0MBox0; enMbId <= CAN_enCh0MBox15 ;enMbId ++ ) + { + if( /*ist RX Box?*/ + CAN__astMessageBoxConfig[enMbId].enMode == CAN__nenMbMode_Rx + ) + { + if( /*Maske prüfen*/ + (pMsg->u32Id & CAN__astMessageBoxConfig[enMbId].IdMask) + == (CAN__astMessageBoxConfig[enMbId].IdValue & CAN__astMessageBoxConfig[enMbId].IdMask) + ) + { + stCanMsg.CanId = (CAN_tId)pMsg->u32Id; + stCanMsg.u8Dlc = pMsg->u8Length; + *((uint32_t *)&(stCanMsg.au8Data[0])) = *((uint32_t *)(&pMsg->au8Data[0])); + *((uint32_t *)&(stCanMsg.au8Data[4])) = *((uint32_t *)(&pMsg->au8Data[4])); + /*Callback an CANIF schicken*/ + CANIF_vRxIndication( 0, enMbId, &stCanMsg ); + } + } + } +} + +void CAND__vRxInterruptCh1( HW_CAN_tstCanMessage* pMsg ) +{ + CAN__tenMessageBox enMbId; + CAN_tstMessage stCanMsg; + for( enMbId = CAN_enCh1MBox0; enMbId <= CAN_enCh1MBox15 ;enMbId ++ ) + { + if( /*ist RX Box?*/ + CAN__astMessageBoxConfig[enMbId].enMode == CAN__nenMbMode_Rx + ) + { + if( /*Maske prüfen*/ + (pMsg->u32Id & CAN__astMessageBoxConfig[enMbId].IdMask) + == (CAN__astMessageBoxConfig[enMbId].IdValue & CAN__astMessageBoxConfig[enMbId].IdMask) + ) + { + stCanMsg.CanId = (CAN_tId)pMsg->u32Id; + stCanMsg.u8Dlc = pMsg->u8Length; + *((uint32_t *)&(stCanMsg.au8Data[0])) = *((uint32_t *)(&pMsg->au8Data[0])); + *((uint32_t *)&(stCanMsg.au8Data[4])) = *((uint32_t *)(&pMsg->au8Data[4])); + /*Callback an CANIF schicken*/ + CANIF_vRxIndication( 1, enMbId, &stCanMsg ); + } + } + } +} + +#else /*!_WINECU_*/ +void CAND_vEnableInterrupt( CAN_tenChannel enChannel ) +{ + CANIF_enable_interrupt(enChannel); +} +void CAND_vDisableInterrupt( CAN_tenChannel enChannel ) +{ + CANIF_disable_interrupt(enChannel); +} +#endif /*!_WINECU_*/ \ No newline at end of file diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAND1c1.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAND1c1.h new file mode 100644 index 0000000..e793bcc --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CAND1c1.h @@ -0,0 +1,38 @@ +#ifndef CAND_C1_H +#define CAND_C1_H +#ifndef _WINECU_ +#include +#include +#include +#include "compiler.h" +#include "board.h" +#include "power_clocks_lib.h" +#include "gpio.h" +#include "pm_uc3c.h" +#include "scif_uc3c.h" +#include "can.h" +#include "canif.h" +#include "CANIF1c1.h" +#endif /* !_WINECU_ */ +#include "CAN1c1.h" + +void can_task(void); +void CAND_vInit( void ); /*CAN_Zelle Initialisieren noch nicht starten*/ +void CAND_vStart( CAN_tenChannel enChannel ); /*CAN-Channel starten Rx und Tx*/ +void CAND_vStop( CAN_tenChannel enChannel ); /*CAN-Channel stoppen Rx und Tx*/ +void CAND_vDeinit( void ); + +bool CAND_boSend( CAN_tenChannel enChannel, CAN_tstMessage *pstMessage ); +void CAND_boGetOverflow( CAN_tenChannel enChannel ); + +#ifdef _WINECU_ +#include "HW_CAN_API.h" +void CAND__vRxInterruptCh0( HW_CAN_tstCanMessage *pMsg ); +void CAND__vRxInterruptCh1( HW_CAN_tstCanMessage *pMsg ); +#else /*_WINECU_*/ +void CAND_vEnableInterrupt( CAN_tenChannel enChannel ); +void CAND_vDisableInterrupt( CAN_tenChannel enChannel ); +#endif /*_WINECU_*/ + + +#endif /*CAND_C1_H*/ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CANDCI.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CANDCI.h new file mode 100644 index 0000000..fcfc926 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CANDCI.h @@ -0,0 +1,89 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief CAN driver for AVR32 UC3. + * + * This file contains basic functions for the AVR32 CAN, with support for all + * modes, settings and clock speeds. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a CAN module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + + +#ifndef _CANDCI_H +#define _CANDCI_H + +//_____ I N C L U D E S ________________________________________________________ +#include "avr32/io.h" +#include "compiler.h" +#include "can.h" +#include "board.h" + +/* + * + *//* + * Mail Box Definition + */ +// ----------------------------------------------------------------- +// CAN Message Definition: Tx Message +#if defined (__ICCAVR32__) +can_msg_t msg_tx_sot = +{ + 0x000, // Identifier + 0x000, // Mask + 0x0000000000000000LL, // Data +}; +#else +can_msg_t msg_tx_sot = +{ + { + { + .id = 0x000, // Identifier + .id_mask = 0x000, // Mask + }, + }, + .data.u64 = 0x0000000000000000LL, // Data +}; +#endif +can_msg_t pcan_msg[2][16]; +// MOB Message Definition: Tx Message +can_mob_t appli_tx_msg[2][16]; + +#endif // _CANDCI_H diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CANIF1c1.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CANIF1c1.c new file mode 100644 index 0000000..1a36784 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CANIF1c1.c @@ -0,0 +1,126 @@ + +#include "cdef.h" +#include "IL1c1.h" +#include "CAND1c1.h" +#include "CANIF1c1.h" + + +volatile bool CANIF__aboSendingActive[CAN__nenCh_NoOfChannels]; + +void CANIF__vCheckSendRequests( void ) +{ + CAN_tenMessage enTxMsgId; + CAN_tstMessage stMessage; + + for( enTxMsgId=CAN_nenMsg_TxMessagesStart; enTxMsgId<=CAN_nenMsg_TxMessagesEnd; enTxMsgId++ ) + { + if( /*Sende Request gesetzt*/ + CAN__boIsSendRequestActive( enTxMsgId ) + /*und keine laufende Sendung auf dem Kanal */ + && !CANIF__aboSendingActive[ CAN__astTxMessageConfig[ CAN__u8TxMsgIdToMsgIndex(enTxMsgId) ].enCanChannel ] + ) + { + + CAN__vClearSendRequestFlag( enTxMsgId ); + /*Kanal auf Sendung aktive setzen*/ + CANIF__aboSendingActive[ CAN__astTxMessageConfig[ CAN__u8TxMsgIdToMsgIndex(enTxMsgId) ].enCanChannel ] = true; + + stMessage.CanId = CAN__aTxIds[CAN__u8TxMsgIdToMsgIndex(enTxMsgId)]; + stMessage.u8Dlc = CAN__astTxMessageConfig[ CAN__u8TxMsgIdToMsgIndex(enTxMsgId) ].u8Dlc; + IL_vGetMessageData( enTxMsgId, stMessage.au8Data ); + + /* check if pretransmit callback is set */ + if (CAN__astTxMessageConfig[ CAN__u8TxMsgIdToMsgIndex(enTxMsgId) ].pfctPreTransmitCb != CAN_vNoPreTx_Cb) + { + /* call pretransmit callback */ + CAN__astTxMessageConfig[ CAN__u8TxMsgIdToMsgIndex(enTxMsgId) ].pfctPreTransmitCb(enTxMsgId); + } + CAND_boSend( CAN__astTxMessageConfig[ CAN__u8TxMsgIdToMsgIndex(enTxMsgId) ].enCanChannel, &stMessage ); + } + } +} + + +void CANIF_vInit( void ) +{ + CAN_tenChannel enChannle; + + /*alle CAN-HW_Kanaele auf "keine Sendeuing aktive" setzen*/ + for( enChannle=0; enChannleCanId >= CAN__astRxIds[ u8MsgIndex ].StartId + && pstMessage->CanId <= CAN__astRxIds[ u8MsgIndex ].EndId + ) + { + boFound = true; + + /*Daten in Msg.-Dante speichern*/ + IL_vSetMessageData( enMsgId, pstMessage->au8Data ); + + CAN__vSetFirstValueFlag( enMsgId ); + CAN__vResetTimeoutCounter( enMsgId ); + + /*Callback aufrufen wenn konfiguriert*/ + if( CAN__astRxMessageConfig[u8MsgIndex].pfctRxIndicationCb ) + { + if( CAN__astRxMessageConfig[u8MsgIndex].pfctRxIndicationCb != CAN_vNoRxIndication_Cb ) + { + CAN__astRxMessageConfig[u8MsgIndex].pfctRxIndicationCb( enMsgId, pstMessage->CanId ); + } + } + } + + /*Naechset MSG ID aus Liste holen */ + u8ListIndex++; + enMsgId = aenRxMsgIdList[u8ListIndex]; + } +} + diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CANIF1c1.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CANIF1c1.h new file mode 100644 index 0000000..2c06dd1 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/CANIF1c1.h @@ -0,0 +1,24 @@ +#ifndef CANIF_C1_H +#define CANIF_C1_H + +#include "CAN1c1.h" + + +void CANIF_vInit( void ); +void CANIF_vMain( void ); //Zyklisch Verarbeitung (Sendezyklen, Timeouts) + +void CANIF_vSendRequest( void ); // Sendeverarbeitung triggern + +/*Callbacks für CAN-Treiber*/ +void CANIF_vTxConfirmation( CAN_tenChannel enChannel, CAN_tId CanId ); +void CANIF_vRxIndication( CAN_tenChannel enChannel, CAN__tenMessageBox enMsgBox, CAN_tstMessage *pstMessage ); + +/* +Beispiele für aufgerufene Callbacks: +void MODUL_vRxIndication_Cb( CAN_tenMessageId enMsgId ); +void MODUL_vPreTransmit_Cb( CAN_tenMessageId enMsgId ); +*/ + + + +#endif /*CANIF_C1_H*/ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EVHD1c1.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EVHD1c1.c new file mode 100644 index 0000000..8b175bf --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EVHD1c1.c @@ -0,0 +1,415 @@ +#include "OS1c1.h" +#include "EXEA1c1.h" +#include "EVHD1c1.h" + + +/***********************************/ +/* Rx-Event Listen fuer Tx-Events */ +/***********************************/ +#define MakeSendEvent( TX_EVENT ) \ + EVHD_tenReceiveEvent EVHD__aenRxEventList_##TX_EVENT[] = \ + { \ + +#define MakeReceiveEvent( TX_EVENT, CALLBACK ) \ + TX_EVENT##_##CALLBACK, \ + +#define MakeSendEventEnd( P ) \ + EVHD_nenReceiveEventNone \ + }; \ + +EVHD_EventConfig + +#undef MakeSendEvent +#undef MakeReceiveEvent +#undef MakeSendEventEnd + +/************************************/ +/* Rx-Events Listen fuer Tasks */ +/************************************/ +#define MakeEventTask( OS_TASK_ID, TASK_FCT, EVHD_TASK_ID ) \ + EVHD_tenReceiveEvent EVHD__aenRxEventList_##EVHD_TASK_ID[] = \ + { \ + +#define MakeSynchronCalls() \ + EVHD_tenReceiveEvent EVHD__aenRxEventList_SynchronCalls[] = \ + { \ + +#define MakeCallbackCall( TX_EVENT, CALLBACK, REGISTERED, EVHD_TASK ) \ + TX_EVENT##_##CALLBACK, \ + +#define MakeEventTaskEnd( P ) \ + EVHD_nenReceiveEventNone \ + }; \ + +#define MakeSynchronCallsEnd( ) \ + EVHD_nenReceiveEventNone \ + }; \ + + + EVHD_CallbackConfig + +#undef MakeEventTask +#undef MakeSynchronCalls +#undef MakeCallbackCall +#undef MakeEventTaskEnd +#undef MakeSynchronCallsEnd + + +/**********************************/ +/* Tx-Events Config */ +/**********************************/ +#define MakeSendEvent( TX_EVENT ) \ + EVHD__aenRxEventList_##TX_EVENT, \ + +#define MakeReceiveEvent( TX_EVENT, CALLBACK ) \ + +#define MakeSendEventEnd( P ) \ + +EVHD_tenReceiveEvent *EVHD__paenReceiveEventLists[EVHD_nenNoOfSendEvents] = +{ + EVHD_EventConfig +}; + +#undef MakeSendEvent +#undef MakeReceiveEventAsync +#undef MakeReceiveEventSync +#undef MakeSendEventEnd + +/**********************************/ +/* EVHD-Task IDs (Enum) */ +/**********************************/ +#define MakeEventTask( OS_TASK_ID, TASK_FCT, EVHD_TASK_ID ) \ + EVHD_TASK_ID, \ + +#define MakeSynchronCalls() \ + +#define MakeCallbackCall( TX_EVENT, CALLBACK, REGISTERED, EVHD_TASK ) \ + +#define MakeEventTaskEnd( P ) \ + +#define MakeSynchronCallsEnd( ) \ + +typedef enum +{ + EVHD_CallbackConfig + + EVHD__nenNoOfTasks, + EVHD__nenSynchron +}EVHD__tenTask; + +#undef MakeEventTask +#undef MakeSynchronCalls +#undef MakeCallbackCall +#undef MakeEventTaskEnd +#undef MakeSynchronCallsEnd + +/************************************/ +/* Task Config EVDH-Task -> OS-Task */ +/************************************/ +typedef struct +{ + OS_tenTaskId enOsTaskId; + EVHD_tenReceiveEvent *aenRxEventList; + uint8_t biActivated : 1; + uint8_t biReserve1 : 7; +}EVHD__tstTaskConfig; + +#define MakeEventTask( OS_TASK_ID, TASK_FCT, EVHD_TASK_ID ) \ + { OS_TASK_ID, EVHD__aenRxEventList_##EVHD_TASK_ID, 0, 0 }, \ + +#define MakeSynchronCalls() \ + +#define MakeCallbackCall( TX_EVENT, CALLBACK, REGISTERED, EVHD_TASK ) \ + +#define MakeEventTaskEnd( P ) \ + +#define MakeSynchronCallsEnd( ) \ + +EVHD__tstTaskConfig EVHD__astTaskConfig[EVHD__nenNoOfTasks] = +{ + EVHD_CallbackConfig +}; + +#undef MakeEventTask +#undef MakeSynchronCalls +#undef MakeCallbackCall +#undef MakeEventTaskEnd +#undef MakeSynchronCallsEnd + + +/************************************/ +/* extern Declaration der Callbacks */ +/************************************/ +#define MakeEventTask( OS_TASK_ID, TASK_FCT, EVHD_TASK_ID ) \ + +#define MakeSynchronCalls() \ + +#define MakeCallbackCall( TX_EVENT, CALLBACK, REGISTERED, EVHD_TASK ) \ + extern void CALLBACK( EVHD_tenReceiveEvent ); \ + +#define MakeEventTaskEnd( P ) \ + +#define MakeSynchronCallsEnd( ) \ + + EVHD_CallbackConfig + +#undef MakeEventTask +#undef MakeSynchronCalls +#undef MakeCallbackCall +#undef MakeEventTaskEnd +#undef MakeSynchronCallsEnd + + + +/**********************************/ +/* Rx-Event Configuration */ +/**********************************/ +typedef struct +{ + const void (*pfctCallback)( EVHD_tenReceiveEvent ); + const EVHD__tenTask enEvhdTask; + uint8_t biRegistered :1; + uint8_t biActive :1; + const uint8_t biSynchron :1; + uint8_t biReserve1 :5; +}EVHD__tstReceiveEventConfig; + + +#define MakeEventTask( OS_TASK_ID, TASK_FCT, EVHD_TASK_ID ) \ + +#define MakeSynchronCalls() \ + +#define MakeCallbackCall( TX_EVENT, CALLBACK, REGISTERED, EVHD_TASK_ID ) \ + { CALLBACK, EVHD_TASK_ID, REGISTERED, 0, (EVHD_TASK_ID == EVHD__nenSynchron ? 1 : 0), 0, }, \ + +#define MakeEventTaskEnd( P ) \ + +#define MakeSynchronCallsEnd( ) \ + +EVHD__tstReceiveEventConfig EVHD__astReceiveEventConfig[EVHD_nenNoOfReceiveEvents] = +{ + EVHD_CallbackConfig +}; + +#undef MakeEventTask +#undef MakeSynchronCalls +#undef MakeCallbackCall +#undef MakeEventTaskEnd +#undef MakeSynchronCallsEnd + +void EVHD__vActivateTask( EVHD__tenTask enEvhdTask ) +{ + EVHD__tstTaskConfig *pstTaskConfig = &(EVHD__astTaskConfig[enEvhdTask]); + + EVHD__mcDisableInterrupt(); + if( !(pstTaskConfig->biActivated) ) + { + pstTaskConfig->biActivated = 1; + EVHD__mcEnableInterrupt(); + OS_vActivateTask( pstTaskConfig->enOsTaskId ); + } + else + { + EVHD__mcEnableInterrupt(); + } +} + +void EVHD__vHandleReceivEvent( EVHD_tenReceiveEvent enReceiveEvent ) +{ + EVHD__tstReceiveEventConfig *pstReceiveEventConfig = &EVHD__astReceiveEventConfig[enReceiveEvent]; + + if( pstReceiveEventConfig->biRegistered ) + { + if( pstReceiveEventConfig->biSynchron ) + { + EVHD__mcDisableInterrupt(); + pstReceiveEventConfig->biActive = 0; + EVHD__mcEnableInterrupt(); + + pstReceiveEventConfig->pfctCallback( enReceiveEvent ); + } + else + { + EVHD__vActivateTask( pstReceiveEventConfig->enEvhdTask ); + } + } +} + +void EVHD__vHandleTask( EVHD__tenTask enEvhdTask ) +{ + EVHD_tenReceiveEvent *aenReceiveEvent; + EVHD_tenReceiveEvent enReceiveEvent; + EVHD__tstReceiveEventConfig *pstReceiveEventConfig; + uint8_t u8Index; + + aenReceiveEvent = EVHD__astTaskConfig[enEvhdTask].aenRxEventList; + + u8Index = 0; + while( (enReceiveEvent = aenReceiveEvent[u8Index]) != EVHD_nenReceiveEventNone ) + { + u8Index++; + pstReceiveEventConfig = &EVHD__astReceiveEventConfig[enReceiveEvent]; + + if( pstReceiveEventConfig->biRegistered ) + { + EVHD__mcDisableInterrupt(); + if( pstReceiveEventConfig->biActive ) + { + pstReceiveEventConfig->biActive = 0; + EVHD__mcEnableInterrupt(); + + pstReceiveEventConfig->pfctCallback( enReceiveEvent ); + } + } + } +} + + +void EVHD_vSendEvent( EVHD_tenSendEvent enSendEvent ) +{ + uint8_t u8Index = 0; + + EVHD_tenReceiveEvent *aenReceiveEventList; + EVHD_tenReceiveEvent enReceiveEvent; + + if( enSendEvent < EVHD_nenNoOfSendEvents ) + { + aenReceiveEventList = EVHD__paenReceiveEventLists[enSendEvent]; + if( aenReceiveEventList ) + { + while( (enReceiveEvent = aenReceiveEventList[u8Index]) != EVHD_nenReceiveEventNone ) + { + EVHD__mcDisableInterrupt(); + EVHD__astReceiveEventConfig[enReceiveEvent].biActive = 1; + EVHD__mcEnableInterrupt(); + + EVHD__vHandleReceivEvent( enReceiveEvent ); + + u8Index++; + } + } + } + else + { + if( enSendEvent != EVHD_nenSendEventNone ) + { + EXEA_vThrowException( EXEA_nenEVHD_InvalidSendEvent ); + } + } +} + +void EVHD_vRegisterEvent( EVHD_tenReceiveEvent enReceiveEvent, bool boGetPending ) +{ + EVHD__tstReceiveEventConfig *pstReceiveEvent; + + if( enReceiveEvent < EVHD_nenNoOfReceiveEvents ) + { + pstReceiveEvent = &EVHD__astReceiveEventConfig[enReceiveEvent]; + + EVHD__mcDisableInterrupt(); + + pstReceiveEvent->biRegistered = 1; + + if( !boGetPending ) + { + pstReceiveEvent->biActive = 0; + EVHD__mcEnableInterrupt(); + } + else if( pstReceiveEvent->biActive ) + { + EVHD__mcEnableInterrupt(); + EVHD__vHandleReceivEvent( enReceiveEvent ); + } + else + { + EVHD__mcEnableInterrupt(); + } + } + else + { + if( enReceiveEvent != EVHD_nenReceiveEventNone ) + { + EXEA_vThrowException( EXEA_nenEVHD_InvalidReceiveEvent ); + } + } +} + +void EVHD_vDeregisterEvent( EVHD_tenReceiveEvent enReceiveEvent ) +{ + if( enReceiveEvent < EVHD_nenNoOfReceiveEvents ) + { + EVHD__mcDisableInterrupt(); + EVHD__astReceiveEventConfig[enReceiveEvent].biRegistered = 0; + EVHD__mcEnableInterrupt(); + } + else + { + if( enReceiveEvent != EVHD_nenReceiveEventNone ) + { + EXEA_vThrowException( EXEA_nenEVHD_InvalidReceiveEvent ); + } + } +} + + +bool EVHD_boIsReceiveEventSet( EVHD_tenReceiveEvent enReceiveEvent ) +{ + if( enReceiveEvent < EVHD_nenNoOfReceiveEvents ) + { + return EVHD__astReceiveEventConfig[enReceiveEvent].biActive; + } + else + { + if( enReceiveEvent != EVHD_nenReceiveEventNone ) + { + EXEA_vThrowException( EXEA_nenEVHD_InvalidReceiveEvent ); + } + return 0; + } +} + +void EVHD_vClearReceiveEvent( EVHD_tenReceiveEvent enReceiveEvent ) +{ + if( enReceiveEvent < EVHD_nenNoOfReceiveEvents ) + { + EVHD__mcDisableInterrupt(); + EVHD__astReceiveEventConfig[enReceiveEvent].biActive = 0; + EVHD__mcEnableInterrupt(); + } + else + { + if( enReceiveEvent != EVHD_nenReceiveEventNone ) + { + EXEA_vThrowException( EXEA_nenEVHD_InvalidReceiveEvent ); + } + } +} + + +/************************************/ +/* Task Funktionen */ +/************************************/ +#define MakeEventTask( OS_TASK_ID, TASK_FCT, EVHD_TASK_ID ) \ + OS_TASK( TASK_FCT ) \ + { \ + EVHD__mcDisableInterrupt(); \ + EVHD__astTaskConfig[EVHD_TASK_ID].biActivated = 0; \ + EVHD__mcEnableInterrupt(); \ + EVHD__vHandleTask( EVHD_TASK_ID ); \ + } \ + +#define MakeSynchronCalls() \ + +#define MakeCallbackCall( TX_EVENT, CALLBACK, REGISTERED, EVHD_TASK ) \ + +#define MakeEventTaskEnd( P ) \ + +#define MakeSynchronCallsEnd( ) \ + + EVHD_CallbackConfig + +#undef MakeEventTask +#undef MakeSynchronCalls +#undef MakeCallbackCall +#undef MakeEventTaskEnd +#undef MakeSynchronCallsEnd diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EVHD1c1.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EVHD1c1.h new file mode 100644 index 0000000..b22173c --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EVHD1c1.h @@ -0,0 +1,79 @@ +#ifndef EVHD_C1_H +#define EVHD_C1_H + + +#include "cdef.h" +#include "EVHD1ce.h" + + +/**************************/ +/* Send Event IDs (enum) */ +/**************************/ +#define MakeSendEvent( TX_EVENT ) \ + TX_EVENT, + +#define MakeReceiveEvent( TX_EVENT, CALLBACK ) \ + +#define MakeSendEventEnd( TX_EVENT ) \ + +typedef enum +{ + EVHD_EventConfig + + EVHD_nenNoOfSendEvents, + EVHD_nenSendEventNone +}EVHD_tenSendEvent; + +#undef MakeSendEvent +#undef MakeReceiveEvent +#undef MakeSendEventEnd + + +/*****************************/ +/* Receive Event IDs (enum) */ +/*****************************/ +#define MakeEventTask( OS_TASK, TASK_FCT, EVHD_TASK ) \ + +#define MakeSynchronCalls() \ + +#define MakeCallbackCall( TX_EVENT, CALLBACK, REGISTERED, EVHD_TASK ) \ + TX_EVENT##_##CALLBACK, \ + +#define MakeEventTaskEnd( P ) \ + +#define MakeSynchronCallsEnd( ) \ + +typedef enum +{ + EVHD_CallbackConfig + + EVHD_nenNoOfReceiveEvents, + EVHD_nenReceiveEventNone +}EVHD_tenReceiveEvent; + +#undef MakeEventTask +#undef MakeSynchronCalls +#undef MakeCallbackCall +#undef MakeEventTaskEnd +#undef MakeSynchronCallsEnd + + + + +/*API*/ +void EVHD_vSendEvent( EVHD_tenSendEvent enEvent ); +void EVHD_vRegisterEvent( EVHD_tenReceiveEvent enEvent, bool boGetPending ); +void EVHD_vDeregisterEvent( EVHD_tenReceiveEvent enEvent ); + +bool EVHD_boIsReceiveEventSet( EVHD_tenReceiveEvent enEvent ); +void EVHD_vClearReceiveEvent( EVHD_tenReceiveEvent enEvent ); + +#if 0 +/*Beispiele für aufgerufene Callbacks*/ +void MODUL_vOnEvent_Cb( EVHD_tenReceiveEvent enEvent ); +#endif + + + + +#endif /*EVHD_C1_H*/ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EVHD1ce.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EVHD1ce.h new file mode 100644 index 0000000..bf0cbe7 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EVHD1ce.h @@ -0,0 +1,58 @@ +#ifndef EVHD_CE_H +#define EVHD_CE_H + +#define EVDH_nRegister 1 +#define EVDH_nUnregister 0 + +#if 0 +/*****************************/ +/*Noetige EXEA-Konfiguration */ +/*****************************/ +MakeException( EXEA_nenEVHD_InvalidReceiveEvent, EXEA__vBlink ) \ +MakeException( EXEA_nenEVHD_InvalidSendEvent, EXEA__vBlink ) \ + +#endif + + +#define EVHD__mcDisableInterrupt() +#define EVHD__mcEnableInterrupt() + + +/*Konfiguration für Event-Handler*/ + +#define EVHD_EventConfig \ +MakeSendEvent( EVHD_nenAVR32_TC0_IRQ0 ) \ + MakeReceiveEvent( EVHD_nenAVR32_TC0_IRQ0, TIMER_v1msCallback ) \ +MakeSendEventEnd( EVHD_nenAVR32_TC0_IRQ0 ) \ +MakeSendEvent( EVHD_nenAVR32_GPIO_IRQ_1 ) \ + MakeReceiveEvent( EVHD_nenAVR32_GPIO_IRQ_1, PINT_vIrqHandler_AVR32_GPIO_IRQ_1 ) \ +MakeSendEventEnd( EVHD_nenAVR32_GPIO_IRQ_1 ) \ +MakeSendEvent( EVHD_nenAVR32_GPIO_IRQ_3 ) \ + MakeReceiveEvent( EVHD_nenAVR32_GPIO_IRQ_3, PINT_vIrqHandler_AVR32_GPIO_IRQ_3 ) \ +MakeSendEventEnd( EVHD_nenAVR32_GPIO_IRQ_3 ) \ +MakeSendEvent( EVHD_nenBtn0 ) \ + MakeReceiveEvent( EVHD_nenBtn0, START_vBtn0Callback ) \ +MakeSendEventEnd( EVHD_nenBtn0 ) \ +MakeSendEvent( EVHD_nenBtn1 ) \ + MakeReceiveEvent( EVHD_nenBtn1, START_vBtn1Callback ) \ +MakeSendEventEnd( EVHD_nenBtn1 ) \ + + +#define EVHD_CallbackConfig \ +MakeEventTask( OS_nenEvhdHigh, EVHD_vHigh, EVHD__nenTaskHigh ) \ + MakeCallbackCall( EVHD_nenBtn0, START_vBtn0Callback, EVDH_nRegister, EVHD__nenTaskHigh ) \ + MakeCallbackCall( EVHD_nenBtn1, START_vBtn1Callback, EVDH_nRegister, EVHD__nenTaskHigh ) \ +MakeEventTaskEnd( EVHD_nenTaskHigh ) \ + \ +MakeEventTask( OS_nenEvhdLow, EVHD_vLow, EVHD__nenTaskLow ) \ +MakeEventTaskEnd( EVHD__nenTaskLow ) \ + \ +MakeSynchronCalls( ) \ + MakeCallbackCall( EVHD_nenAVR32_TC0_IRQ0, TIMER_v1msCallback, EVDH_nRegister, EVHD__nenSynchron ) \ + MakeCallbackCall( EVHD_nenAVR32_GPIO_IRQ_1, PINT_vIrqHandler_AVR32_GPIO_IRQ_1, EVDH_nRegister, EVHD__nenSynchron ) \ + MakeCallbackCall( EVHD_nenAVR32_GPIO_IRQ_3, PINT_vIrqHandler_AVR32_GPIO_IRQ_3, EVDH_nRegister, EVHD__nenSynchron ) \ +MakeSynchronCallsEnd( ) \ + + + +#endif /*EVHD_CE_H*/ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EXEA1c1.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EXEA1c1.c new file mode 100644 index 0000000..d2228bc --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EXEA1c1.c @@ -0,0 +1,57 @@ + +#include "TIMER1c1.h" +#include "EXEA1c1.h" + +void EXEA__vBlink( void ) +{ + TIMER_vSet( TIMER_nenExea_Blitz, 100 ); + TIMER_vStart( TIMER_nenExea_Blitz ); + while( 1 ) + { + if( TIMER_boIsTimeExpired( TIMER_nenExea_Blitz ) ) + { + TIMER_vSubValue( TIMER_nenExea_Blitz, 100 ); + EXEA__nenDioOutput(); + } + } +} + +void EXEA__vReset( void ) +{ + /*Reset durch Watchdog*/ + while( 1 ); +} + +void EXEA__vDontCare( void ) +{ + /*Do nothing*/ +} + +typedef struct +{ + void (*pFctAciton)( void ); +}EXEA__tstConfig; + + + +/*Konfigurations Tabelle*/ + +#define MakeException( ExceId, Action ) \ + Action, + +EXEA__tstConfig EXEA__astCondfig[EXEA_nenNoOfChannles] = +{ + EXEA_MakeConfig +}; + + +#undef MakeException + + +void EXEA__vThrowException( EXEA_tenChannels enChannel ) +{ + if( EXEA__astCondfig[enChannel].pFctAciton ) + { + EXEA__astCondfig[enChannel].pFctAciton(); + } +} \ No newline at end of file diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EXEA1c1.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EXEA1c1.h new file mode 100644 index 0000000..ae488f7 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EXEA1c1.h @@ -0,0 +1,28 @@ +#ifndef EXEA_C1_H +#define EXEA_C1_H + + +#include "cdef.h" +#include "EXEA1ce.h" + + +#define MakeException( ExceId, Action ) \ + ExceId, + +typedef enum +{ + EXEA_MakeConfig + + EXEA_nenNoOfChannles +}EXEA_tenChannels; + +#undef MakeException + + +#define EXEA_vThrowException( EXEA_Channel ) EXEA__vThrowException( EXEA_Channel ) + +/*Kein Aufruf von extern!*/ +void EXEA__vThrowException( EXEA_tenChannels enChannel ); + + +#endif /*EXEA_C1_H*/ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EXEA1ce.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EXEA1ce.h new file mode 100644 index 0000000..04feb6b --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/EXEA1ce.h @@ -0,0 +1,30 @@ +#ifndef EXEA_CE_H +#define EXEA_CE_H + +#if 0 +/*********************************************************/ +/*Benoetigt folgende Konfigurationen von anderen Modulen!*/ +/*********************************************************/ +TIMER_Make( TIMER_nenExea_Blintz, TIMER_nenUnit1ms, NULL ) \ + +#endif + +//#include "DIO1c1.h" + +/*Output des Blitzens*/ +//#define EXEA__nenDioOutput() DIO_vSetValue( DIO_nenModeLed, !DIO_xGetValueSet( DIO_nenModeLed ) ); +#define EXEA__nenDioOutput() + + +/*Konfiguration für EXEA*/ +#define EXEA_MakeConfig \ +/* EXEA-Kanal, Aktion */\ +MakeException( EXEA_nenCAN_MsgId_Invalid, EXEA__vBlink ) \ +MakeException( EXEA_nenCAN_SigId_Invalid, EXEA__vReset ) \ +MakeException( EXEA_nenCAND_SendWhilBusy, EXEA__vDontCare ) \ +MakeException( EXEA_nenEVHD_InvalidReceiveEvent, EXEA__vBlink ) \ +MakeException( EXEA_nenEVHD_InvalidSendEvent, EXEA__vBlink ) \ + + + +#endif /*EXEA_CE_H*/ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/IL1c1.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/IL1c1.c new file mode 100644 index 0000000..5b15750 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/IL1c1.c @@ -0,0 +1,1419 @@ +#include "IL1c1.h" + + + + +/* Wie sind die Bytes zu interpretieren */ +typedef enum +{ + IL__nenLittleEndian, /*Intel*/ + IL__nenBigEndian /*Motorola*/ +}CAN__tenByteOrderBitAccess; + + +#ifdef _WINECU_ /*means littleendian CPU*/ + +void vBitWrite( uint8_t *pMsgData, + uint8_t *pSigData, + uint8_t u8MsgLength, + uint8_t u8SigDataLength, + uint32_t dwBitCount, + uint32_t dwStartBit, + CAN__tenByteOrderBitAccess enOrder + ) +{ + //**************************************** + //********Lokale Variablen anlegen******** + //**************************************** + //Bitoffset in erstem Byte (Anzahl der Bits bis erstes Bit des Wertes beginnt) + uint8_t u8BitOffset; + //Startadresse erstes relevantes Byte in Speicher + uint8_t* pau8SpeicherStart; + //Relevante Laenge des Speichers in Byte + uint8_t u8SpeicherLaengeRelevant; + //Berechnete Lange des Wert-Speichers in Byte + uint8_t u8WertByteLaenge; + //Anzahl der Bits in letztem relevanten Byte des Speichers bis zum letzten Bit des Wertes + uint8_t u8WertRestBits; + //Maskierungen fuer erstes und letztes Byte + uint8_t u8MaskeStartByte; + uint8_t u8MaskeEndByte; + //Zaehlvariable fuer For-Schleifen (@StRi: Guter Name!) + uint8_t u8ForCount; + + uint8_t u8SpeicherLaengeBenötigt; + uint8_t msgOverflow; + uint8_t sigOverflow; + + + + // Wenn keine Daten vorhanden sind, kann auch nichts geschrieben werden. + if(u8MsgLength == 0) + return; + + + //**************************************************************************************** + //********Berechnen lokaler Variablen Gueltigkeit fuer LittleEndian und BigEndian********* + //**************************************************************************************** + //berechnen der ByteLaenge des Wert-Speichers + u8WertByteLaenge = ((unsigned char)((dwBitCount - 1) >> 3)) + 1; + //pruefen, ob die Laenge des uebergebenen Speichers groß genug ist um den maxWert des Signals zu beinhalten +// ASSERT(u8WertByteLaenge <= u8SigDataLength); + + //Offset berechnen (Bits in erstem Byte bis 1.Bit des Wertes beginnt) + u8BitOffset = (unsigned char)((dwStartBit)%8); + //Anzahl der Bits in letztem relevanten Byte des Speichers bis zum letzten Bit des Wertes + u8WertRestBits = (uint8_t)(((dwBitCount) + (u8BitOffset))%8); + + //Laenge in Byte des relevanten Speicherbereichs ermitteln + u8SpeicherLaengeRelevant = ((unsigned char)(((dwBitCount) + (unsigned short)(u8BitOffset))>>3)); + if (//stehen die letzten Bits des Wertes in einem Teil des letzten Bytes + u8WertRestBits > 0) + { + //Im letzten Byte des relevanten Speichers stehen letzte Bit des Wertes (kleiner 8) + u8SpeicherLaengeRelevant++; + } + + // BTP 5360: Es sollen nur so viele Daten übertragen werden wie vorhanden sind oder ins Ziel passen. + u8SpeicherLaengeBenötigt = u8SpeicherLaengeRelevant + (unsigned char)((dwStartBit)>>3); +// ASSERT(u8SpeicherLaengeBenötigt <= u8MsgLength); + if(u8SpeicherLaengeBenötigt > u8MsgLength || u8WertByteLaenge > u8SigDataLength) + { + // Wenn Restbits, zuerst diese weg lassen. + if(u8WertRestBits != 0) + { + u8WertRestBits = 0; + --u8SpeicherLaengeRelevant; + --u8SpeicherLaengeBenötigt; + } + // Zu übertragende Bytes auf Botschaftslänge oder Ziellänge kürzen. + msgOverflow = u8SpeicherLaengeBenötigt > u8MsgLength ? u8SpeicherLaengeBenötigt - u8MsgLength : 0; + sigOverflow = u8WertByteLaenge > u8SigDataLength ? u8WertByteLaenge - u8SigDataLength : 0; + if(msgOverflow < sigOverflow) + msgOverflow = sigOverflow; + if(msgOverflow >= u8WertByteLaenge)// Nichts zu übertragen. + return; + u8SpeicherLaengeRelevant -= msgOverflow; + u8WertByteLaenge -= msgOverflow; + } + + if(u8WertByteLaenge == 0)// Nichts zu übertragen. + return; + + if(dwBitCount > (unsigned)(u8SigDataLength * 8)) + dwBitCount = u8SigDataLength * 8; + + //************************************************************** + //********null setzen ungenutzter Bits im Wert-Speicher********* + //************************************************************** + if (//enthält das letzte Byte des Wert-Speichers ungenutzte Bits + (dwBitCount % 8) == 0) + { + // letztes Byte in Wert-Speicher enthält keine ungenutzten Bits + } + else + { + //letztes Byte in Wert-Speicer enthaelt ungenutzten Bits + //null setzen der ungenutzten Bits + *((pSigData) + u8WertByteLaenge - 1) &= (0xff >> (8 - (dwBitCount % 8)) ); + } + + + switch(enOrder) + { + case IL__nenLittleEndian: + { + //************************************************************** + //********Byteorder ist INTEL*********************************** + //************************************************************** + + //Startadresse des relevanten Speicherbereichs ermitteln + pau8SpeicherStart = pMsgData + (unsigned char)((dwStartBit)>>3); + + + if (//Steht der gesamte Wert nur in einem Byte im Speicher + u8SpeicherLaengeRelevant == 1) + { + //******************************************************* + //gesamter Wert steht in nur einem Byte im Speicher + //******************************************************* + //Maske anlegen um Wert-Bereich in Speicher null zu setzen + if (//Sind RestBits enthalten + u8WertRestBits == 0) + { + //keine RestBits enthalten + u8MaskeStartByte = 0; + } + else + { + //RestBits enthalten + u8MaskeStartByte = 0xff << u8WertRestBits; + } + //BitOffset in Maske beruecksichtigen + u8MaskeStartByte |= ( ~(0xff << u8BitOffset)); + + //Wert-Bereich in Speicher null setzen + *pau8SpeicherStart &= u8MaskeStartByte; + + //Wert in Wert-Bereich im Speicher schreiben + *pau8SpeicherStart |= ((*pSigData)< 2) + { + // @StRi: Die inneren Bytes auf 0 setzen. So einfacher + //::ZeroMemory(*(pau8SpeicherStart + 1), u8SpeicherLaengeRelevant - 3); + + //Ja es gibt Bytes die mit Sicherheit null gesetzt werden muessen + for (u8ForCount = 1; u8ForCount <= (u8SpeicherLaengeRelevant - 2) ; u8ForCount++) + { + *(pau8SpeicherStart + u8ForCount) = 0; + } + } + else + { + //Nein es sind keine Bytes null zu setzen + } + + //relevante Bits in erstem relevanten SpeicherByte null setzen + //Maske erstellen + u8MaskeStartByte = ~(0xff << u8BitOffset); + //verunden + *pau8SpeicherStart &= u8MaskeStartByte; + + + if (//muss ein Offset beruecksichtigt werden + u8BitOffset == 0) + { + //es muss kein Offset beruecksichtigt werden + //*********************************************************** + //schreiben aller WertBytes in Speicher beide ab Startadresse + //*********************************************************** + u8ForCount = 0; + while (//schreiben aller WertBytes bis auf das letzte (muss verodert werden, da + //dort Bits enthalten sein koennen die nicht angetastet werden duerfen + u8ForCount < (u8WertByteLaenge - 1)) + { + *(pau8SpeicherStart + u8ForCount) = *(pSigData + u8ForCount); + u8ForCount++; + } + //verodern des letzten WertBytes in letztes relevantes Byte in Speicher + *((pau8SpeicherStart) + u8ForCount) |= *(pSigData + u8ForCount); + } + else + { + //es muss ein Offset beruecksichtigt werden + + + u8ForCount = 0; + while (u8ForCount < u8WertByteLaenge) + { + //schreiben lowBits + *(pau8SpeicherStart + u8ForCount) |= (*(pSigData + u8ForCount)) << u8BitOffset; + //schreiben highBits + *(pau8SpeicherStart + u8ForCount + 1) |= (*(pSigData + u8ForCount)) >> (8-u8BitOffset); + + u8ForCount++; + } + } + } + } + break; + case IL__nenBigEndian: + { + //************************************************************** + //********Byteorder ist MOTOROLA******************************** + //************************************************************** + + //Startadresse des relevanten Speicherbereichs ermitteln + pau8SpeicherStart = pMsgData + (u8MsgLength - 1) - (unsigned char)(dwStartBit >> 3); + + if (//Steht der gesamte Wert nur in einem Byte im Speicher + u8SpeicherLaengeRelevant == 1) + { + //********************************************************* + //gesamter Wert steht in nur einem Byte im Speicher******** + //********************************************************* + // Maske anlegen um Wert-Bereich in Speicher null zu setzen + if (//Sind RestBits enthalten + u8WertRestBits == 0) + { + //keine RestBits enthalten + u8MaskeStartByte = 0; + } + else + { + //RestBits enthalten + u8MaskeStartByte = 0xff << u8WertRestBits; + } + //BitOffset beruecksichtigen + u8MaskeStartByte |= ~(0xff << u8BitOffset); + + //Wert-Bereich in Speicher null setzen + *pau8SpeicherStart &= u8MaskeStartByte; + + //Wert in Wert-Bereich im Speicher schreiben + *pau8SpeicherStart |= *pSigData << u8BitOffset; + } + else + { + //********************************************************* + //Wert ist ueber mehr als ein Byte im Speicher verteilt + //********************************************************* + //letzte Bits des Wert-Bereich in Speicher null setzen + if (//Sind RestBits enthalten + u8WertRestBits == 0) + { + //keine RestBits enthalten + *(pau8SpeicherStart - u8SpeicherLaengeRelevant + 1) = 0; + } + else + { + //RestBits sind enthalten + //Maske erstellen + u8MaskeEndByte = (0xff << u8WertRestBits); + //letztes relevantes Byte in Speicher mit Maske verunden + *(pau8SpeicherStart - u8SpeicherLaengeRelevant + 1) &= u8MaskeEndByte; + } + + //Loeschen von (StartByte+1) bis (Startbyte+LaengeRelevant-2) + if (//gibt es zwischen erstem und letztem Relevanten Byte noch Bytes die komplett null gesetzt werden k”nnen + u8SpeicherLaengeRelevant > 2) + { + // @StRi. Hier ZeroMemory einbauen! + //Ja es gibt Bytes die mit sicherheit null gesetzt werden muessen + for (u8ForCount = 1; u8ForCount <= (u8SpeicherLaengeRelevant - 2) ; u8ForCount++) + { + *(pau8SpeicherStart - u8ForCount) = 0; + } + } + else + { + //Nein, es sind keine Bytes null zu setzen + } + + //relevante Bits in erstem relevanten Byte null setzen + //Maske erstellen + u8MaskeStartByte = ~(0xff << u8BitOffset); + //verunden + *pau8SpeicherStart &= u8MaskeStartByte; + + if (//muss ein Offset beruecksichtigt werden + u8BitOffset == 0) + { + //es muss kein Offset beruecksichtigt werden + //schreiben aller WertBytes bis auf das letzte (muss verodert werden, da + //dort Bits enthalten sein koennen die nicht angetastet werden duerfen + u8ForCount = 0; + while (u8ForCount < u8WertByteLaenge - 1) + { + *((pau8SpeicherStart) - u8ForCount) = *((pSigData) + u8ForCount); + + u8ForCount++; + } + //verodern des letzten WertBytes in letztes relevantes Byte in Speicher + *((pau8SpeicherStart) - u8ForCount) |= *((pSigData) + u8ForCount); + } + else + { + //es muss ein Offset beruecksichtigt werden + u8ForCount = 0; + while (u8ForCount < u8WertByteLaenge) + { + //schreiben lowBits + *((pau8SpeicherStart) - u8ForCount) |= ((*((pSigData) + u8ForCount))<>(8-u8BitOffset)); + u8ForCount++; + } + } + } + } + break; + } +} + + +void vBitRead(const uint8_t* pMsgData, + uint8_t* pSigData, + uint8_t u8MsgLength, + uint8_t u8SigDataLength, + uint32_t dwBitCount, + uint32_t dwStartBit, + CAN__tenByteOrderBitAccess enOrder) +{ + //************************************************************** + //************anlegen Lokaler Variablen************************* + //************************************************************** + + //Bitoffset in erstem Byte (Anzahl der Bits bis erstes Bit des Wertes beginnt) + uint8_t u8BitOffset; + //Startadresse erstes relevantes Byte in Speicher + const uint8_t* pau8SpeicherStart; + //Relevante Laenge des Speichers in Byte + uint8_t u8SpeicherLaengeRelevant; + //Berechnete Lange des Wert-Speichers in Byte + uint8_t u8WertByteLaenge; + //Anzahl der Bits in letztem relevanten Byte des Speichers bis zum letzten Bit des Wertes + uint8_t u8WertRestBits; + //Maskierungen fuer erstes und letztes Byte + uint8_t u8MaskeEndByte; + uint8_t u8MaskeStartByte; + //Zaehlvariable fuer For-Schleifen + uint8_t u8ForCount; + + uint8_t u8SpeicherLaengeBenoetigt; + uint8_t msgOverflow; + uint8_t sigOverflow; + uint8_t u8Pos; + + + //************************************************************* + //******* berechnen lokaler Variablen fuer READ ************** + //************************************************************* + //Berechnen der Laenge des benoetigten Wert-Speichers in Byte + u8WertByteLaenge = ((unsigned char)((dwBitCount - 1) >> 3)) + 1; + + //Offset berechnen (Bits in erstem Byte bis 1.Bit des Wertes beginnt) + u8BitOffset = (unsigned char)((dwStartBit)%8); + //Anzahl der Bits in letztem relevanten Byte des Speichers bis zum letzten Bit des Wertes + u8WertRestBits = (uint8_t)(((dwBitCount) + (u8BitOffset))%8); + + //Laenge in Byte des relevanten Speicherbereichs ermitteln + u8SpeicherLaengeRelevant = ((unsigned char)(((dwBitCount) + (unsigned short)(u8BitOffset))>>3)); + if (//stehen die letzten Bits des Wertes in einem Teil des letzten Bytes + u8WertRestBits > 0) + { + //Im letzten Byte des relevanten Speichers stehen letzte Bit des Wertes (kleiner 8) + u8SpeicherLaengeRelevant++; + } + + // BTP 5360: Es sollen nur so viele Daten übertragen werden wie vorhanden sind oder ins Ziel passen. + u8SpeicherLaengeBenoetigt = u8SpeicherLaengeRelevant + (unsigned char)((dwStartBit)>>3); + if(u8SpeicherLaengeBenoetigt > u8MsgLength || u8WertByteLaenge > u8SigDataLength) + { + // Wenn Restbits, zuerst diese weg lassen. + if(u8WertRestBits != 0) + { + u8WertRestBits = 0; + --u8SpeicherLaengeRelevant; + --u8SpeicherLaengeBenoetigt; + } + // Zu übertragende Bytes auf Botschaftslänge oder Ziellänge kürzen. + msgOverflow = u8SpeicherLaengeBenoetigt > u8MsgLength ? u8SpeicherLaengeBenoetigt - u8MsgLength : 0; + sigOverflow = u8WertByteLaenge > u8SigDataLength ? u8WertByteLaenge - u8SigDataLength : 0; + if(msgOverflow < sigOverflow) + msgOverflow = sigOverflow; + if(msgOverflow >= u8WertByteLaenge)// Nichts zu übertragen. + return; + u8SpeicherLaengeRelevant -= msgOverflow; + u8WertByteLaenge -= msgOverflow; + } + + //Null setzen des Wert speichers ueber die errechnete Bytelaenge + for( u8Pos=0; u8Pos>3); + + if (//Steht der gesamte Wert nur in einem Byte im Speicher + u8SpeicherLaengeRelevant == 1) + { + //******************************************************** + //gesamter Wert steht in nur einem Byte im Speicher* + //******************************************************** + + //Maske anlegen um Wert-Bereich aus Speicher zu lesen + if (//Sind RestBits enthalten + u8WertRestBits == 0) + { + //keine RestBits enthalten + u8MaskeStartByte = 0xff; + } + else + { + //RestBits enthalten + u8MaskeStartByte = ~(0xff << u8WertRestBits); + } + //BitOffset beruecksichtigen + u8MaskeStartByte &= (0xff << u8BitOffset); + + //Wert-Bereich aus Speicher lesen um den Offset nach rechts verschieben und in Wert speichern + *pSigData = ((*pau8SpeicherStart) & u8MaskeStartByte) >> u8BitOffset; + } + else + { + //********************************************************* + //Wert ist ueber mehr als ein Byte im Speicher verteilt + //********************************************************* + + //Bitmaske fuer Bits aus letztem relevanten SpeicherByte erstellen + if (//Sind RestBits enthalten + u8WertRestBits == 0) + { + //keine RestBits enthalten (alle Bits des letzten Byte muessen ausgelesen werden) + u8MaskeEndByte = 0xff; + } + else + { + //RestBits enthalten + + //Maske erstellen(Maskiert alle relevanten Bits des letzten Bytes) + u8MaskeEndByte = ~(0xff << u8WertRestBits); + } + + if (//muss ein Offset beruecksichtigt werden + u8BitOffset == 0) + { + //es muss kein Offset beruecksichtigt werden + //lesen aller WertBytes in Speicher beide ab Startadresse + u8ForCount = 0; + while (u8ForCount < u8WertByteLaenge-1) + { + *((pSigData) + u8ForCount) = *((pau8SpeicherStart) + u8ForCount); + u8ForCount++; + } + //lesen des letzten relevanten Bytes Maskiert, um nur relevante bits zu lesen + *((pSigData) + u8ForCount) = ((*((pau8SpeicherStart) + u8ForCount)) & u8MaskeEndByte); + } + else + { + //es muss ein Offset beruecksichtigt werden + u8ForCount = 0; + while (u8ForCount < u8SpeicherLaengeRelevant -2) + { + //lesen lowBits + (*((pSigData) + u8ForCount)) |= ((*((pau8SpeicherStart) + u8ForCount))>>u8BitOffset); + //lesen highBits + (*((pSigData) + u8ForCount)) |= ((*((pau8SpeicherStart) + u8ForCount + 1))<<(8-u8BitOffset)) ; + u8ForCount++; + } + //lesen lowBits + (*((pSigData) + u8ForCount)) |= ((*((pau8SpeicherStart) + u8ForCount))>>u8BitOffset); + //lesen highBits mit Maske für letztes Byte + (*((pSigData) + u8ForCount)) |= (((*((pau8SpeicherStart) + u8ForCount + 1)) & u8MaskeEndByte)<<(8-u8BitOffset)) ; + //lesen lowBits mit Maske für letztes Byte + (*((pSigData) + u8ForCount+1)) |= (((*((pau8SpeicherStart) + u8ForCount +1)) & u8MaskeEndByte)>>u8BitOffset); + } + } + + } + break; + case IL__nenBigEndian: + { + + //Startadresse des relevanten Speicherbereichs ermitteln + pau8SpeicherStart = pMsgData + (u8MsgLength - 1) - (unsigned char)((dwStartBit)>>3); + + if (//Steht der gesamte Wert nur in einem Byte im Speicher + u8SpeicherLaengeRelevant == 1) + { + //********************************************************* + //gesamter Wert steht in nur einem Byte im Speicher + //********************************************************* + + //Maske anlegen um Wert-Bereich aus Speicher zu lesen + if (//Sind RestBits enthalten + u8WertRestBits == 0) + { + //keine RestBits enthalten + u8MaskeStartByte = 0xff; + } + else + { + //RestBits enthalten + u8MaskeStartByte = ~(0xff << u8WertRestBits); + } + //BitOffset beruecksichtigen + u8MaskeStartByte &= (0xff << u8BitOffset); + + //Wert-Bereich aus Speicher lesen um den Offset nach rechts verschieben und in Wert speichern + *pSigData = ((*pau8SpeicherStart) & u8MaskeStartByte) >> u8BitOffset; + } + else + { + //********************************************************* + //Wert ist ueber mehr als ein Byte im Speicher verteilt + //********************************************************* + + //Bitmaske fuer Bits aus letztem relevanten SpeicherByte erstellen + if (//Sind RestBits enthalten + u8WertRestBits == 0) + { + //keine RestBits enthalten (alle Bits des letzten Byte muessen ausgelesen werden) + u8MaskeEndByte = 0xff; + } + else + { + //RestBits enthalten + + //Maske erstellen(Maskiert alle relevanten Bits des letzten Bytes) + u8MaskeEndByte = ~(0xff << u8WertRestBits); + } + + if (//muss ein Offset beruecksichtigt werden + u8BitOffset == 0) + { + //es muss kein Offset beruecksichtigt werden + //lesen aller WertBytes in Speicher beide ab Startadresse + u8ForCount = 0; + while (u8ForCount < u8WertByteLaenge-1) + { + *((pSigData) + u8ForCount) = *((pau8SpeicherStart) - u8ForCount); + u8ForCount++; + } + //lesen des letzten relevanten Bytes Maskiert, um nur relevante bits zu lesen + *((pSigData) + u8ForCount) = (*((pau8SpeicherStart) - u8ForCount)) & u8MaskeEndByte; + } + else + { + //es muss ein Offset beruecksichtigt werden + u8ForCount = 0; + while (u8ForCount < u8SpeicherLaengeRelevant -2) + { + //lesen lowBits + (*((pSigData) + u8ForCount)) |= ((*((pau8SpeicherStart) - u8ForCount))>>u8BitOffset); + //lesen highBits + (*((pSigData) + u8ForCount)) |= ((*((pau8SpeicherStart) - u8ForCount - 1))<<(8-u8BitOffset)) ; + u8ForCount++; + } + //lesen lowBits + (*((pSigData) + u8ForCount)) |= (((*((pau8SpeicherStart) - u8ForCount))>>u8BitOffset) ); + //lesen highBits mit Maske für letztes Byte + (*((pSigData) + u8ForCount)) |= (((*((pau8SpeicherStart) - u8ForCount - 1)) & u8MaskeEndByte)<<(8-u8BitOffset)) ; + //lesen lowBits mit Maske für letztes Byte + (*((pSigData) + u8ForCount + 1)) |= (((*((pau8SpeicherStart) - u8ForCount - 1)) & u8MaskeEndByte)>>u8BitOffset); + } + } + + } + break; + } +} + +#else /*!_WINECU_ means bigendian CPU*/ + +void vBitWrite( uint8_t *pMsgData, + uint8_t *pSigData, + uint8_t u8MsgLength, + uint8_t u8SigDataLength, + uint32_t dwBitCount, + uint32_t dwStartBit, + CAN__tenByteOrderBitAccess enOrder + ) +{ + //**************************************** + //********Lokale Variablen anlegen******** + //**************************************** + //Bitoffset in erstem Byte (Anzahl der Bits bis erstes Bit des Wertes beginnt) + uint8_t u8BitOffset; + //Startadresse erstes relevantes Byte in Speicher + uint8_t* pau8SpeicherStart; + //Relevante Laenge des Speichers in Byte + uint8_t u8SpeicherLaengeRelevant; + //Berechnete Lange des Wert-Speichers in Byte + uint8_t u8WertByteLaenge; + //Anzahl der Bits in letztem relevanten Byte des Speichers bis zum letzten Bit des Wertes + uint8_t u8WertRestBits; + //Maskierungen fuer erstes und letztes Byte + uint8_t u8MaskeStartByte; + uint8_t u8MaskeEndByte; + //Zaehlvariable fuer For-Schleifen (@StRi: Guter Name!) + uint8_t u8ForCount; + + uint8_t u8SpeicherLaengeBenoetigt; + uint8_t msgOverflow; + uint8_t sigOverflow; + + + + // Wenn keine Daten vorhanden sind, kann auch nichts geschrieben werden. + if(u8MsgLength == 0) + return; + + + //**************************************************************************************** + //********Berechnen lokaler Variablen Gueltigkeit fuer LittleEndian und BigEndian********* + //**************************************************************************************** + //berechnen der ByteLaenge des Wert-Speichers + u8WertByteLaenge = ((unsigned char)((dwBitCount - 1) >> 3)) + 1; + //pruefen, ob die Laenge des uebergebenen Speichers groß genug ist um den maxWert des Signals zu beinhalten +// ASSERT(u8WertByteLaenge <= u8SigDataLength); + + //Offset berechnen (Bits in erstem Byte bis 1.Bit des Wertes beginnt) + u8BitOffset = (unsigned char)((dwStartBit)%8); + //Anzahl der Bits in letztem relevanten Byte des Speichers bis zum letzten Bit des Wertes + u8WertRestBits = (uint8_t)(((dwBitCount) + (u8BitOffset))%8); + + //Laenge in Byte des relevanten Speicherbereichs ermitteln + u8SpeicherLaengeRelevant = ((unsigned char)(((dwBitCount) + (unsigned short)(u8BitOffset))>>3)); + if (//stehen die letzten Bits des Wertes in einem Teil des letzten Bytes + u8WertRestBits > 0) + { + //Im letzten Byte des relevanten Speichers stehen letzte Bit des Wertes (kleiner 8) + u8SpeicherLaengeRelevant++; + } + + // BTP 5360: Es sollen nur so viele Daten übertragen werden wie vorhanden sind oder ins Ziel passen. + u8SpeicherLaengeBenoetigt = u8SpeicherLaengeRelevant + (unsigned char)((dwStartBit)>>3); +// ASSERT(u8SpeicherLaengeBenötigt <= u8MsgLength); + if(u8SpeicherLaengeBenoetigt > u8MsgLength || u8WertByteLaenge > u8SigDataLength) + { + // Wenn Restbits, zuerst diese weg lassen. + if(u8WertRestBits != 0) + { + u8WertRestBits = 0; + --u8SpeicherLaengeRelevant; + --u8SpeicherLaengeBenoetigt; + } + // Zu übertragende Bytes auf Botschaftslänge oder Ziellänge kürzen. + msgOverflow = u8SpeicherLaengeBenoetigt > u8MsgLength ? u8SpeicherLaengeBenoetigt - u8MsgLength : 0; + sigOverflow = u8WertByteLaenge > u8SigDataLength ? u8WertByteLaenge - u8SigDataLength : 0; + if(msgOverflow < sigOverflow) + msgOverflow = sigOverflow; + if(msgOverflow >= u8WertByteLaenge)// Nichts zu übertragen. + return; + u8SpeicherLaengeRelevant -= msgOverflow; + u8WertByteLaenge -= msgOverflow; + } + + if(u8WertByteLaenge == 0)// Nichts zu übertragen. + return; + + if(dwBitCount > (unsigned)(u8SigDataLength * 8)) + dwBitCount = u8SigDataLength * 8; + + //************************************************************** + //********null setzen ungenutzter Bits im Wert-Speicher********* + //************************************************************** + if (//enthält das letzte Byte des Wert-Speichers ungenutzte Bits + (dwBitCount % 8) == 0) + { + // letztes Byte in Wert-Speicher enthält keine ungenutzten Bits + } + else + { + //letztes Byte in Wert-Speicer enthaelt ungenutzten Bits + //null setzen der ungenutzten Bits + *((pSigData) + u8WertByteLaenge - 1) &= (0xff >> (8 - (dwBitCount % 8)) ); + } + + + switch(enOrder) + { + case IL__nenLittleEndian: + { + //************************************************************** + //********Byteorder ist INTEL*********************************** + //************************************************************** + + //Startadresse des relevanten Speicherbereichs ermitteln + pau8SpeicherStart = pMsgData + (unsigned char)((dwStartBit)>>3); + + + if (//Steht der gesamte Wert nur in einem Byte im Speicher + u8SpeicherLaengeRelevant == 1) + { + //******************************************************* + //gesamter Wert steht in nur einem Byte im Speicher + //******************************************************* + //Maske anlegen um Wert-Bereich in Speicher null zu setzen + if (//Sind RestBits enthalten + u8WertRestBits == 0) + { + //keine RestBits enthalten + u8MaskeStartByte = 0; + } + else + { + //RestBits enthalten + u8MaskeStartByte = 0xff << u8WertRestBits; + } + //BitOffset in Maske beruecksichtigen + u8MaskeStartByte |= ( ~(0xff << u8BitOffset)); + + //Wert-Bereich in Speicher null setzen + *pau8SpeicherStart &= u8MaskeStartByte; + + //Wert in Wert-Bereich im Speicher schreiben + *pau8SpeicherStart |= ((*(pSigData + u8SigDataLength - 1))< 2) + { + // @StRi: Die inneren Bytes auf 0 setzen. So einfacher + //::ZeroMemory(*(pau8SpeicherStart + 1), u8SpeicherLaengeRelevant - 3); + + //Ja es gibt Bytes die mit Sicherheit null gesetzt werden muessen + for (u8ForCount = 1; u8ForCount <= (u8SpeicherLaengeRelevant - 2) ; u8ForCount++) + { + *(pau8SpeicherStart + u8ForCount) = 0; + } + } + else + { + //Nein es sind keine Bytes null zu setzen + } + + //relevante Bits in erstem relevanten SpeicherByte null setzen + //Maske erstellen + u8MaskeStartByte = ~(0xff << u8BitOffset); + //verunden + *pau8SpeicherStart &= u8MaskeStartByte; + + + if (//muss ein Offset beruecksichtigt werden + u8BitOffset == 0) + { + //es muss kein Offset beruecksichtigt werden + //*********************************************************** + //schreiben aller WertBytes in Speicher beide ab Startadresse + //*********************************************************** + u8ForCount = 0; + while (//schreiben aller WertBytes bis auf das letzte (muss verodert werden, da + //dort Bits enthalten sein koennen die nicht angetastet werden duerfen + u8ForCount < (u8WertByteLaenge - 1)) + { + *(pau8SpeicherStart + u8ForCount) = *(pSigData + u8SigDataLength - 1 - u8ForCount); + u8ForCount++; + } + //verodern des letzten WertBytes in letztes relevantes Byte in Speicher + *((pau8SpeicherStart) + u8ForCount) |= *(pSigData + u8SigDataLength - 1 - u8ForCount); + } + else + { + //es muss ein Offset beruecksichtigt werden + + + u8ForCount = 0; + while (u8ForCount < u8WertByteLaenge) + { + //schreiben lowBits + *(pau8SpeicherStart + u8ForCount) |= (*(pSigData + u8SigDataLength - 1 - u8ForCount)) << u8BitOffset; + //schreiben highBits + *(pau8SpeicherStart + u8ForCount + 1) |= (*(pSigData + u8SigDataLength - 1 - u8ForCount)) >> (8-u8BitOffset); + + u8ForCount++; + } + } + } + } + break; + case IL__nenBigEndian: + { + //************************************************************** + //********Byteorder ist MOTOROLA******************************** + //************************************************************** + + //Startadresse des relevanten Speicherbereichs ermitteln + pau8SpeicherStart = pMsgData + (u8MsgLength - 1) - (unsigned char)(dwStartBit >> 3); + + if (//Steht der gesamte Wert nur in einem Byte im Speicher + u8SpeicherLaengeRelevant == 1) + { + //********************************************************* + //gesamter Wert steht in nur einem Byte im Speicher******** + //********************************************************* + // Maske anlegen um Wert-Bereich in Speicher null zu setzen + if (//Sind RestBits enthalten + u8WertRestBits == 0) + { + //keine RestBits enthalten + u8MaskeStartByte = 0; + } + else + { + //RestBits enthalten + u8MaskeStartByte = 0xff << u8WertRestBits; + } + //BitOffset beruecksichtigen + u8MaskeStartByte |= ~(0xff << u8BitOffset); + + //Wert-Bereich in Speicher null setzen + *pau8SpeicherStart &= u8MaskeStartByte; + + //Wert in Wert-Bereich im Speicher schreiben + *pau8SpeicherStart |= *(pSigData + u8SigDataLength - 1) << u8BitOffset; + } + else + { + //********************************************************* + //Wert ist ueber mehr als ein Byte im Speicher verteilt + //********************************************************* + //letzte Bits des Wert-Bereich in Speicher null setzen + if (//Sind RestBits enthalten + u8WertRestBits == 0) + { + //keine RestBits enthalten + *(pau8SpeicherStart - u8SpeicherLaengeRelevant + 1) = 0; + } + else + { + //RestBits sind enthalten + //Maske erstellen + u8MaskeEndByte = (0xff << u8WertRestBits); + //letztes relevantes Byte in Speicher mit Maske verunden + *(pau8SpeicherStart - u8SpeicherLaengeRelevant + 1) &= u8MaskeEndByte; + } + + //Loeschen von (StartByte+1) bis (Startbyte+LaengeRelevant-2) + if (//gibt es zwischen erstem und letztem Relevanten Byte noch Bytes die komplett null gesetzt werden k”nnen + u8SpeicherLaengeRelevant > 2) + { + // @StRi. Hier ZeroMemory einbauen! + //Ja es gibt Bytes die mit sicherheit null gesetzt werden muessen + for (u8ForCount = 1; u8ForCount <= (u8SpeicherLaengeRelevant - 2) ; u8ForCount++) + { + *(pau8SpeicherStart - u8ForCount) = 0; + } + } + else + { + //Nein, es sind keine Bytes null zu setzen + } + + //relevante Bits in erstem relevanten Byte null setzen + //Maske erstellen + u8MaskeStartByte = ~(0xff << u8BitOffset); + //verunden + *pau8SpeicherStart &= u8MaskeStartByte; + + if (//muss ein Offset beruecksichtigt werden + u8BitOffset == 0) + { + //es muss kein Offset beruecksichtigt werden + //schreiben aller WertBytes bis auf das letzte (muss verodert werden, da + //dort Bits enthalten sein koennen die nicht angetastet werden duerfen + u8ForCount = 0; + while (u8ForCount < u8WertByteLaenge - 1) + { + *((pau8SpeicherStart) - u8ForCount) = *((pSigData) + u8SigDataLength - 1 - u8ForCount); + + u8ForCount++; + } + //verodern des letzten WertBytes in letztes relevantes Byte in Speicher + *((pau8SpeicherStart) - u8ForCount) |= *((pSigData) + u8SigDataLength - 1 - u8ForCount); + } + else + { + //es muss ein Offset beruecksichtigt werden + u8ForCount = 0; + while (u8ForCount < u8WertByteLaenge) + { + //schreiben lowBits + *((pau8SpeicherStart) - u8ForCount) |= ((*((pSigData) + u8SigDataLength - 1 - u8ForCount))<>(8-u8BitOffset)); + u8ForCount++; + } + } + } + } + break; + } +} + + +void vBitRead(const uint8_t* pMsgData, + uint8_t* pSigData, + uint8_t u8MsgLength, + uint8_t u8SigDataLength, + uint32_t dwBitCount, + uint32_t dwStartBit, + CAN__tenByteOrderBitAccess enOrder) +{ + //************************************************************** + //************anlegen Lokaler Variablen************************* + //************************************************************** + + //Bitoffset in erstem Byte (Anzahl der Bits bis erstes Bit des Wertes beginnt) + uint8_t u8BitOffset; + //Startadresse erstes relevantes Byte in Speicher + const uint8_t* pau8SpeicherStart; + //Relevante Laenge des Speichers in Byte + uint8_t u8SpeicherLaengeRelevant; + //Berechnete Lange des Wert-Speichers in Byte + uint8_t u8WertByteLaenge; + //Anzahl der Bits in letztem relevanten Byte des Speichers bis zum letzten Bit des Wertes + uint8_t u8WertRestBits; + //Maskierungen fuer erstes und letztes Byte + uint8_t u8MaskeEndByte; + uint8_t u8MaskeStartByte; + //Zaehlvariable fuer For-Schleifen + uint8_t u8ForCount; + + uint8_t u8SpeicherLaengeBenoetigt; + uint8_t msgOverflow; + uint8_t sigOverflow; + uint8_t u8Pos; + + + //************************************************************* + //******* berechnen lokaler Variablen fuer READ ************** + //************************************************************* + //Berechnen der Laenge des benoetigten Wert-Speichers in Byte + u8WertByteLaenge = ((unsigned char)((dwBitCount - 1) >> 3)) + 1; + + //Offset berechnen (Bits in erstem Byte bis 1.Bit des Wertes beginnt) + u8BitOffset = (unsigned char)((dwStartBit)%8); + //Anzahl der Bits in letztem relevanten Byte des Speichers bis zum letzten Bit des Wertes + u8WertRestBits = (uint8_t)(((dwBitCount) + (u8BitOffset))%8); + + //Laenge in Byte des relevanten Speicherbereichs ermitteln + u8SpeicherLaengeRelevant = ((unsigned char)(((dwBitCount) + (unsigned short)(u8BitOffset))>>3)); + if (//stehen die letzten Bits des Wertes in einem Teil des letzten Bytes + u8WertRestBits > 0) + { + //Im letzten Byte des relevanten Speichers stehen letzte Bit des Wertes (kleiner 8) + u8SpeicherLaengeRelevant++; + } + + // BTP 5360: Es sollen nur so viele Daten übertragen werden wie vorhanden sind oder ins Ziel passen. + u8SpeicherLaengeBenoetigt = u8SpeicherLaengeRelevant + (unsigned char)((dwStartBit)>>3); + if(u8SpeicherLaengeBenoetigt > u8MsgLength || u8WertByteLaenge > u8SigDataLength) + { + // Wenn Restbits, zuerst diese weg lassen. + if(u8WertRestBits != 0) + { + u8WertRestBits = 0; + --u8SpeicherLaengeRelevant; + --u8SpeicherLaengeBenoetigt; + } + // Zu übertragende Bytes auf Botschaftslänge oder Ziellänge kürzen. + msgOverflow = u8SpeicherLaengeBenoetigt > u8MsgLength ? u8SpeicherLaengeBenoetigt - u8MsgLength : 0; + sigOverflow = u8WertByteLaenge > u8SigDataLength ? u8WertByteLaenge - u8SigDataLength : 0; + if(msgOverflow < sigOverflow) + msgOverflow = sigOverflow; + if(msgOverflow >= u8WertByteLaenge)// Nichts zu übertragen. + return; + u8SpeicherLaengeRelevant -= msgOverflow; + u8WertByteLaenge -= msgOverflow; + } + + //Null setzen des Wert speichers ueber die errechnete Bytelaenge + for( u8Pos=0; u8Pos>3); + + if (//Steht der gesamte Wert nur in einem Byte im Speicher + u8SpeicherLaengeRelevant == 1) + { + //******************************************************** + //gesamter Wert steht in nur einem Byte im Speicher* + //******************************************************** + + //Maske anlegen um Wert-Bereich aus Speicher zu lesen + if (//Sind RestBits enthalten + u8WertRestBits == 0) + { + //keine RestBits enthalten + u8MaskeStartByte = 0xff; + } + else + { + //RestBits enthalten + u8MaskeStartByte = ~(0xff << u8WertRestBits); + } + //BitOffset beruecksichtigen + u8MaskeStartByte &= (0xff << u8BitOffset); + + //Wert-Bereich aus Speicher lesen um den Offset nach rechts verschieben und in Wert speichern + *(pSigData + u8SigDataLength - 1) = ((*pau8SpeicherStart) & u8MaskeStartByte) >> u8BitOffset; + } + else + { + //********************************************************* + //Wert ist ueber mehr als ein Byte im Speicher verteilt + //********************************************************* + + //Bitmaske fuer Bits aus letztem relevanten SpeicherByte erstellen + if (//Sind RestBits enthalten + u8WertRestBits == 0) + { + //keine RestBits enthalten (alle Bits des letzten Byte muessen ausgelesen werden) + u8MaskeEndByte = 0xff; + } + else + { + //RestBits enthalten + + //Maske erstellen(Maskiert alle relevanten Bits des letzten Bytes) + u8MaskeEndByte = ~(0xff << u8WertRestBits); + } + + if (//muss ein Offset beruecksichtigt werden + u8BitOffset == 0) + { + //es muss kein Offset beruecksichtigt werden + //lesen aller WertBytes in Speicher beide ab Startadresse + u8ForCount = 0; + while (u8ForCount < u8WertByteLaenge-1) + { + *((pSigData) + u8SigDataLength - 1 - u8ForCount) = *((pau8SpeicherStart) + u8ForCount); + u8ForCount++; + } + //lesen des letzten relevanten Bytes Maskiert, um nur relevante bits zu lesen + *((pSigData) + u8SigDataLength - 1 - u8ForCount) = ((*((pau8SpeicherStart) + u8ForCount)) & u8MaskeEndByte); + } + else + { + //es muss ein Offset beruecksichtigt werden + u8ForCount = 0; + while (u8ForCount < u8SpeicherLaengeRelevant -2) + { + //lesen lowBits + (*((pSigData) + u8SigDataLength - 1 - u8ForCount)) |= ((*((pau8SpeicherStart) + u8ForCount))>>u8BitOffset); + //lesen highBits + (*((pSigData) + u8SigDataLength - 1 - u8ForCount)) |= ((*((pau8SpeicherStart) + u8ForCount + 1))<<(8-u8BitOffset)) ; + u8ForCount++; + } + //lesen lowBits + (*((pSigData) + u8SigDataLength - 1 - u8ForCount)) |= ((*((pau8SpeicherStart) + u8ForCount))>>u8BitOffset); + //lesen highBits mit Maske für letztes Byte + (*((pSigData) + u8SigDataLength - 1 - u8ForCount)) |= (((*((pau8SpeicherStart) + u8ForCount + 1)) & u8MaskeEndByte)<<(8-u8BitOffset)) ; + //lesen lowBits mit Maske für letztes Byte + (*((pSigData) + u8SigDataLength - 1 - u8ForCount - 1)) |= (((*((pau8SpeicherStart) + u8ForCount +1)) & u8MaskeEndByte)>>u8BitOffset); + } + } + + } + break; + case IL__nenBigEndian: + { + + //Startadresse des relevanten Speicherbereichs ermitteln + pau8SpeicherStart = pMsgData + (u8MsgLength - 1) - (unsigned char)((dwStartBit)>>3); + + if (//Steht der gesamte Wert nur in einem Byte im Speicher + u8SpeicherLaengeRelevant == 1) + { + //********************************************************* + //gesamter Wert steht in nur einem Byte im Speicher + //********************************************************* + + //Maske anlegen um Wert-Bereich aus Speicher zu lesen + if (//Sind RestBits enthalten + u8WertRestBits == 0) + { + //keine RestBits enthalten + u8MaskeStartByte = 0xff; + } + else + { + //RestBits enthalten + u8MaskeStartByte = ~(0xff << u8WertRestBits); + } + //BitOffset beruecksichtigen + u8MaskeStartByte &= (0xff << u8BitOffset); + + //Wert-Bereich aus Speicher lesen um den Offset nach rechts verschieben und in Wert speichern + *pSigData = ((*pau8SpeicherStart) & u8MaskeStartByte) >> u8BitOffset; + } + else + { + //********************************************************* + //Wert ist ueber mehr als ein Byte im Speicher verteilt + //********************************************************* + + //Bitmaske fuer Bits aus letztem relevanten SpeicherByte erstellen + if (//Sind RestBits enthalten + u8WertRestBits == 0) + { + //keine RestBits enthalten (alle Bits des letzten Byte muessen ausgelesen werden) + u8MaskeEndByte = 0xff; + } + else + { + //RestBits enthalten + + //Maske erstellen(Maskiert alle relevanten Bits des letzten Bytes) + u8MaskeEndByte = ~(0xff << u8WertRestBits); + } + + if (//muss ein Offset beruecksichtigt werden + u8BitOffset == 0) + { + //es muss kein Offset beruecksichtigt werden + //lesen aller WertBytes in Speicher beide ab Startadresse + u8ForCount = 0; + while (u8ForCount < u8WertByteLaenge-1) + { + *((pSigData) + u8ForCount) = *((pau8SpeicherStart) - u8ForCount); + u8ForCount++; + } + //lesen des letzten relevanten Bytes Maskiert, um nur relevante bits zu lesen + *((pSigData) + u8ForCount) = (*((pau8SpeicherStart) - u8ForCount)) & u8MaskeEndByte; + } + else + { + //es muss ein Offset beruecksichtigt werden + u8ForCount = 0; + while (u8ForCount < u8SpeicherLaengeRelevant -2) + { + //lesen lowBits + (*((pSigData) + u8ForCount)) |= ((*((pau8SpeicherStart) - u8ForCount))>>u8BitOffset); + //lesen highBits + (*((pSigData) + u8ForCount)) |= ((*((pau8SpeicherStart) - u8ForCount - 1))<<(8-u8BitOffset)) ; + u8ForCount++; + } + //lesen lowBits + (*((pSigData) + u8ForCount)) |= (((*((pau8SpeicherStart) - u8ForCount))>>u8BitOffset) ); + //lesen highBits mit Maske für letztes Byte + (*((pSigData) + u8ForCount)) |= (((*((pau8SpeicherStart) - u8ForCount - 1)) & u8MaskeEndByte)<<(8-u8BitOffset)) ; + //lesen lowBits mit Maske für letztes Byte + (*((pSigData) + u8ForCount + 1)) |= (((*((pau8SpeicherStart) - u8ForCount - 1)) & u8MaskeEndByte)>>u8BitOffset); + } + } + + } + break; + } +} + +#endif /*!_WINECU_ means bigendian CPU*/ + +/*API*/ +void IL_vSetSignal( CAN_tenSignal enSigId, uint32_t u32Value ) +{ + CAN_tenMessage enMsgId; + + if( CAN_boIsSignal( enSigId ) ) + { + enMsgId = CAN__astSignalConfig[enSigId].enMsgId; + if( CAN__boIsTxMsg( enMsgId ) ) + { + vBitWrite( CAN__astTxMessageConfig[ CAN__u8TxMsgIdToMsgIndex(enMsgId) ].pu8Data, //*pMsgData, + (uint8_t *)&u32Value, //uint8_t *pSigData, + CAN__astTxMessageConfig[ CAN__u8TxMsgIdToMsgIndex(enMsgId) ].u8Dlc, //u8MsgLength, + sizeof( u32Value ), //u8SigDataLength in Byte, + CAN__astSignalConfig[enSigId].u8BitSize, // dwBitCount, + CAN__astSignalConfig[enSigId].u8StartBit, // dwStartBit, + IL__nenLittleEndian // bit order + ); + } + else + { + vBitWrite( CAN__astRxMessageConfig[ CAN__u8RxMsgIdToMsgIndex(enMsgId) ].pu8Data, //*pMsgData, + (uint8_t *)&u32Value, //uint8_t *pSigData, + CAN__astRxMessageConfig[ CAN__u8RxMsgIdToMsgIndex(enMsgId) ].u8Dlc, //u8MsgLength, + sizeof( u32Value ), //u8SigDataLength in Byte, + CAN__astSignalConfig[enSigId].u8BitSize, // dwBitCount, + CAN__astSignalConfig[enSigId].u8StartBit, // dwStartBit, + IL__nenLittleEndian // bit order + ); + } + } +} + +uint32_t IL_u32GetSignal( CAN_tenSignal enSigId ) +{ + CAN_tenMessage enMsgId; + uint32_t u32Value=0; + + if( CAN_boIsSignal( enSigId ) ) + { + enMsgId = CAN__astSignalConfig[enSigId].enMsgId; + if( CAN__boIsTxMsg( enMsgId ) ) + { + vBitRead( CAN__astTxMessageConfig[ CAN__u8TxMsgIdToMsgIndex(enMsgId) ].pu8Data, //*pMsgData, + (uint8_t *)&u32Value, //uint8_t *pSigData, + CAN__astTxMessageConfig[ CAN__u8TxMsgIdToMsgIndex(enMsgId) ].u8Dlc, //u8MsgLength, + sizeof( u32Value ), //u8SigDataLength in Byte, + CAN__astSignalConfig[enSigId].u8BitSize, // dwBitCount, + CAN__astSignalConfig[enSigId].u8StartBit, // dwStartBit, + IL__nenLittleEndian // bit order + ); + } + else + { + vBitRead( CAN__astRxMessageConfig[ CAN__u8RxMsgIdToMsgIndex(enMsgId) ].pu8Data, //*pMsgData, + (uint8_t *)&u32Value, //uint8_t *pSigData, + CAN__astRxMessageConfig[ CAN__u8RxMsgIdToMsgIndex(enMsgId) ].u8Dlc, //u8MsgLength, + sizeof( u32Value ), //u8SigDataLength in Byte, + CAN__astSignalConfig[enSigId].u8BitSize, // dwBitCount, + CAN__astSignalConfig[enSigId].u8StartBit, // dwStartBit, + IL__nenLittleEndian // bit order + ); + } + } + return u32Value; +} + + +bool IL_boGetSignalTo (CAN_tenSignal enSigId ) +{ + return IL_boGetMessageTo( CAN__astSignalConfig[enSigId].enMsgId ); +} + +bool IL_boGetSignalFv( CAN_tenSignal enSigId ) +{ + return IL_boGetMessageFv( CAN__astSignalConfig[enSigId].enMsgId ); +} + +void IL_vSetSignalSendRequest( CAN_tenSignal enSigId ) +{ + IL_vSetMessageSendRequest( CAN__astSignalConfig[enSigId].enMsgId ); +} + + +void IL_vSetMessageData( CAN_tenMessage enMsgId, uint8_t *pu8Data ) +{ + uint8_t u8Index; + uint8_t u8MsgIndex; + + uint8_t u8SrcData,u8DstData; + + if( CAN__boIsTxMsg( enMsgId ) ) + { + u8MsgIndex = CAN__u8TxMsgIdToMsgIndex(enMsgId); + for( u8Index=0; u8Index +#include "avr_compiler.h" +#include "avr32/io.h" +#include "tc.h" + + +#include "EVHD1c1.h" +#include "IVECT1c1.h" + +/* ISR routines */ +#define IVECT_MakeInterrupt(IRQLINE,PRIO) \ + __attribute__((__interrupt__)) \ + static void IVECT__v##IRQLINE##_isr( void ) \ + { \ + EVHD_vSendEvent( EVHD_nen##IRQLINE ); \ + } \ + + + IVECT_MakeConfig +#undef IVECT_MakeInterrupt + +void IVECT_vInit( void ) { + + Disable_global_interrupt(); + INTC_init_interrupts(); + +#define IVECT_MakeInterrupt(IRQLINE,PRIO) \ + INTC_register_interrupt(IVECT__v##IRQLINE##_isr,IRQLINE, PRIO); \ + + IVECT_MakeConfig +#undef IVECT_MakeInterrupt + + Enable_global_interrupt(); +} diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/IVECT1c1.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/IVECT1c1.h new file mode 100644 index 0000000..9908337 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/IVECT1c1.h @@ -0,0 +1,23 @@ +#ifndef IVECT_C1_H +#define IVECT_C1_H + +#include "IVECT1ce.h" +#include + +/* Interrupt Channels*/ +typedef enum +{ +#define IVECT_MakeInterrupt(IRQLINE,PRIO) \ + IVECT_nen##IRQLINE, \ + + IVECT_MakeConfig + +#undef IVECT_MakeInterrupt + /*must be the last entry*/ + IVECT_nenNoOfChannels +} IVECT_tenChannels; + +/* interface prototypes */ +void IVECT_vInit( void ); + +#endif /*IVECT_C1_H*/ \ No newline at end of file diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/IVECT1ce.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/IVECT1ce.h new file mode 100644 index 0000000..fdb68ec --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/IVECT1ce.h @@ -0,0 +1,16 @@ +#ifndef IVECT_CE_H +#define IVECT_CE_H + +#include "cdef.h" + +#define IVECT_MakeConfig \ + /* IRQ-Line, priority*/ \ + IVECT_MakeInterrupt( AVR32_TC0_IRQ0, AVR32_INTC_INT3 ) \ + IVECT_MakeInterrupt( AVR32_GPIO_IRQ_1, AVR32_INTC_INT0 ) \ + IVECT_MakeInterrupt( AVR32_GPIO_IRQ_3, AVR32_INTC_INT0 ) \ + +#define IVECT_MakeInterrupt( IRQLINE, PRIO ) \ + +#undef IVECT_MakeInterrupt + +#endif /*IVECT_CE_H*/ \ No newline at end of file diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/OS1c1.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/OS1c1.c new file mode 100644 index 0000000..c04bba7 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/OS1c1.c @@ -0,0 +1,230 @@ + +#include "TIMER1c1.h" + +#include "OS1c1.h" + + + +typedef struct +{ + void (*const pTaskFunc) ( void ); + const uint16_t u16ActivationCycle; + uint8_t u8Activation_cnt; + OS_tenTaskState enState; +}OS__tstConfig; + + +//Vorwärtsdeklaration der Task-Funktionen +#define OS_MakeNormalTask( TaskId, pFunc ) \ + extern void pFunc ( void ); + +#define OS_MakeAutostartTask( TaskId, pFunc ) \ + extern void pFunc ( void ); + +#define OS_MakeCyclicTask( TaskId, pFunc, Cycle, Unit ) \ + extern void pFunc ( void ); + +#define OS_MakeAlarmTask( TaskId, pFunc, Cycle, Unit ) \ + extern void pFunc ( void ); + + +OS_MakeConfig + +#undef OS_MakeNormalTask +#undef OS_MakeAutostartTask +#undef OS_MakeCyclicTask +#undef OS_MakeAlarmTask + + +//Konfiguration +#define OS_MakeNormalTask( TaskId, pFunc ) \ + { pFunc, 0, 0, OS_nenSleeping }, + +#define OS_MakeAutostartTask( TaskId, pFunc ) \ + { pFunc, 0, 1, OS_nenActivated }, + +#define OS_MakeCyclicTask( TaskId, pFunc, Cycle, Unit ) \ + { pFunc, Cycle, 0, OS_nenSleeping }, + +#define OS_MakeAlarmTask( TaskId, pFunc, Cycle, Unit ) \ + { pFunc, Cycle, 0, OS_nenSleeping }, + +OS__tstConfig OS__astConfig[OS_nenNoOfTasks] = +{ + OS_MakeConfig +}; + +#undef OS_MakeNormalTask +#undef OS_MakeAutostartTask +#undef OS_MakeCyclicTask +#undef OS_MakeAlarmTask + + +OS_tenTaskId OS__enCurrentTask; + + +void OS_vActivateTask( OS_tenTaskId enTask ) +{ + OS__vDisableInterrups(); + + OS__astConfig[enTask].u8Activation_cnt++; + + OS__vEnableInterrups(); +} + +void OS_vSchedule( void ) +{ + OS_tenTaskId enHighestTask; + OS_tenTaskId enPreeptedTask = OS_nenNoOfTasks; + bool boExit=false; + + /*Abfragen der Timer für Taskaktivierung*/ + #define OS_MakeCyclicTask( TaskId, pFunc, Cycle, Unit ) \ + TIMER_boIsTimeExpired( TIMER_nenCyclic##TaskId ) ? OS_vActivateTask( TaskId ), TIMER_vSubValue( TIMER_nenCyclic##TaskId, Cycle) : 0; + + #define OS_MakeAlarmTask( TaskId, pFunc, Cycle, Unit ) \ + TIMER_boIsTimeExpired( TIMER_nenAlarm##TaskId ) ? OS_vActivateTask( TaskId ) : 0; + + #define OS_MakeNormalTask( TaskId, pFunc ) + + #define OS_MakeAutostartTask( TaskId, pFunc ) + + OS_MakeConfig + + #undef OS_MakeCyclicTask + #undef OS_MakeAlarmTask + #undef OS_MakeNormalTask + #undef OS_MakeAutostartTask + + /*Suche aktivierten Task mit höchster Prio*/ + enHighestTask = 0; + do /*solange noch höherpriore aktivierete Tasks forhanden sind */ + { + while( /*ist der Activation Zaehler nicht gesetzt?*/ + OS__astConfig[enHighestTask].u8Activation_cnt == 0 + /*abbruch wenn Ende der Task-Liste erreicht */ + && enHighestTask < OS_nenNoOfTasks + ) + { + ++enHighestTask; + } + + /* Faelle: + 1) Kein Task ist an laufen + Kein neuen Task gefunden + -> OS_Schedule() beenden, Dadurch wird auch OS_vRun() beendet + Bedingung: enHighestTask == OS_nenNoOfTasks + OS__enCurrentTask == OS_nenNoOfTasks + 2) Kein Task ist an laufen + neuen Task gefunden + -> neuen Task starten, neue Task-Funktion in OS_Schedul aufrufen + Bedingung: enHighestTask < OS_nenNoOfTasks + OS__enCurrentTask == OS_nenNoOfTasks + 3) ein Task ist an laufen + Kein neuen Task gefunden + -> alter Task laeuft weiter, OS_Schedule() beenden + Bedingung: enHighestTask == OS_nenNoOfTasks + OS__enCurrentTask < OS_nenNoOfTasks + 4) ein Task ist an laufen + neuen Task hat kleinere prio + -> alter Task laeuft weiter, OS_Schedule() beenden + Bedingung: enHighestTask > OS__enCurrentTask + OS__enCurrentTask < OS_nenNoOfTasks + 5) ein Task ist an laufen + neuen Task hat groessere prio + -> neuer Task laeuft weiter, neue Task-Funktion in OS_Schedul aufrufen + Bedingung: enHighestTask < OS__enCurrentTask + OS__enCurrentTask < OS_nenNoOfTasks + */ + if( /*ist die Prio es neuen Task größer als die Proi des laufenden Task*/ + enHighestTask < OS__enCurrentTask + ) + { + /*Zustand des alten Task auf unterbrochen setzen*/ + if( OS__enCurrentTask < OS_nenNoOfTasks ) + { + OS__astConfig[OS__enCurrentTask].enState = OS_nenPreempted; + } + /*zu unterbrechenden Task merken */ + enPreeptedTask = OS__enCurrentTask; + /*aktueller Task ist neuer Task */ + OS__enCurrentTask = enHighestTask; + /*euen Task-State auf "running" */ + OS__astConfig[enHighestTask].enState = OS_nenRunning; + OS__vDisableInterrups(); + OS__astConfig[enHighestTask].u8Activation_cnt--; + OS__vEnableInterrups(); + /*Task-Funk aufrufen */ + OS__astConfig[enHighestTask].pTaskFunc(); + /*nach verlassen der Task-Funktion ist der Task wieder schlafend*/ + OS__astConfig[enHighestTask].enState = OS_nenSleeping; + /*laufenden Task ist der unterbrochenen Task */ + if( enPreeptedTask < OS_nenNoOfTasks ) + { + OS__astConfig[enPreeptedTask].enState = OS_nenRunning; + } + OS__enCurrentTask = enPreeptedTask; + } + else + { + boExit = true; + } + } + while( /*solange noch höherpriore aktivierete Tasks forhanden sind */ + !boExit + ); + +} + +OS_tenTaskState OS_enGetTaskState( OS_tenTaskId enTask ) +{ + OS__vDisableInterrups(); + if( OS__astConfig[enTask].enState == OS_nenSleeping + && OS__astConfig[enTask].u8Activation_cnt > 0 + ) + { + OS__vEnableInterrups(); + return OS_nenActivated; + } + else + { + OS__vEnableInterrups(); + return OS__astConfig[enTask].enState; + } +} + +OS_tenTaskId OS_enGetCurrentTaskId( void ) +{ + return OS__enCurrentTask; +} + +void OS_vInit( void ) +{ + OS__enCurrentTask = OS_nenNoOfTasks; + + /*Starten der Timer für zyklische Task-Aktivierung*/ + #define OS_MakeCyclicTask( TaskId, pFunc, Cycle, Unit ) \ + TIMER_vStart( TIMER_nenCyclic##TaskId ); + + #define OS_MakeAlarmTask( TaskId, pFunc, Cycle, Unit ) \ + + #define OS_MakeNormalTask( TaskId, pFunc ) \ + + #define OS_MakeAutostartTask( TaskId, pFunc ) \ + + OS_MakeConfig + + #undef OS_MakeCyclicTask + #undef OS_MakeAlarmTask + #undef OS_MakeNormalTask + #undef OS_MakeAutostartTask +} + +void OS_vRun( void ) +{ + OS_vSchedule(); +} + + + + diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/OS1c1.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/OS1c1.h new file mode 100644 index 0000000..c6ab0ca --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/OS1c1.h @@ -0,0 +1,104 @@ +#ifndef OS_C1_H +#define OS_C1_H + +#include "cdef.h" + +#include "OS1ce.h" + + +typedef enum +{ + OS_nenSleeping, + OS_nenActivated, + OS_nenRunning, + OS_nenPreempted +}OS_tenTaskState; + +/*enum für Task-ID*/ +#define OS_MakeNormalTask( TaskId, pFunc ) \ + TaskId, + +#define OS_MakeAutostartTask( TaskId, pFunc ) \ + TaskId, + +#define OS_MakeCyclicTask( TaskId, pFunc, Cycle, Unit ) \ + TaskId, + +#define OS_MakeAlarmTask( TaskId, pFunc, Cycle, Unit ) \ + TaskId, + + +typedef enum +{ + OS_MakeConfig + + /*Muss der letzte Eintrag sein!*/ + OS_nenNoOfTasks +}OS_tenTaskId; + +#undef OS_MakeNormalTask +#undef OS_MakeAutostartTask +#undef OS_MakeCyclicTask +#undef OS_MakeAlarmTask + +/*extern Deklaration für Task-Funktionen*/ +#define OS_MakeNormalTask( TaskId, pFunc ) \ + extern void pFunc( void ); + +#define OS_MakeAutostartTask( TaskId, pFunc ) \ + extern void pFunc( void ); + +#define OS_MakeCyclicTask( TaskId, pFunc, Cycle, Unit ) \ + extern void pFunc( void ); + +#define OS_MakeAlarmTask( TaskId, pFunc, Cycle, Unit ) \ + extern void pFunc( void ); + + OS_MakeConfig + +#undef OS_MakeNormalTask +#undef OS_MakeAutostartTask +#undef OS_MakeCyclicTask +#undef OS_MakeAlarmTask + + +/* +typedef struct +{ + void (*const pTaskFunc) ( void ); + const uint16_t u16ActivationCycle; + uint8_t u8Activation_cnt; + OS_tenTaskState enState; +}OS__tstConfig; +*/ + +#include "TIMER1c1.h" /*nur für die folgenden Makros noetig*/ + +#define OS_vActivateAlarm( TaskId, u32Delay ) \ +( TIMER_vSet( TIMER_nenAlarm##TaskId, u32Delay ), TIMER_vStart( TIMER_nenAlarm##TaskId ) ) + +#define OS_vCancelAlarm( TaskId ) \ + TIMER_vStop( TIMER_nenAlarm##TaskId ) + +#define OS_boIsAlarmActive( TaskId ) \ + TIMER_boIsTimeRunning( TIMER_nenAlarm##TaskId ) + + + + +void OS_vActivateTask( OS_tenTaskId enTask ); + +void OS_vSchedule( void ); + +OS_tenTaskState OS_enGetTaskState( OS_tenTaskId enTask ); + +OS_tenTaskId OS_enGetCurrentTaskId( void ); + +void OS_vInit( void ); + +void OS_vRun( void ); + +#define OS_TASK( NAME ) void NAME##_fkt( void ) + + +#endif /*OS_C1_H*/ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/OS1ce.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/OS1ce.h new file mode 100644 index 0000000..b8d0496 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/OS1ce.h @@ -0,0 +1,32 @@ +#ifndef OS_CE_H +#define OS_CE_H + +/*Höchste Prio ganz oben + kleinste Prio nach unten*/ +#define OS_MakeConfig \ +/* Task ID *pTaskFunc, Delay, Unit */ \ +OS_MakeNormalTask( OS_nenEvhdHigh, EVHD_vHigh_fkt ) \ +OS_MakeNormalTask( OS_nenEvhdLow, EVHD_vLow_fkt ) \ +OS_MakeAutostartTask( OS_nenTaskIdle, START_vIdle_fkt ) \ + + + +#define OS__vDisableInterrups() + +#define OS__vEnableInterrups() + +#define OS_MakeCyclicTask( TaskId, ActiveType, pFunc, Cycle, Unit ) \ + TaskId, + +#define OS_MakeAlarmTask( TaskId, ActiveType, pFunc, Cycle, Unit ) \ + TaskId, + +#define OS_MakeNormalTask( TaskId, ActiveType, pFunc ) \ + TaskId, + +#undef OS_MakeCyclicTask +#undef OS_MakeAlarmTask +#undef OS_MakeNormalTask + +#endif /*OS_CE_H*/ + diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/PINT1c1.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/PINT1c1.c new file mode 100644 index 0000000..a8b12fe --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/PINT1c1.c @@ -0,0 +1,51 @@ +#ifdef _WINECU_ +#include "HW_VIPER_c1.h" +#else /* !_WINECU_, means target*/ +#include +#include +#include "gpio.h" +#endif /* !_WINECU_ */ + +#include "EVHD1c1.h" +#include "PINT1c1.h" + +/* functions to receive interrupt group events (callbacks for EVHD) */ +#define PINT_MakeIRQHandlerStart(HWIRQGRP) \ + void PINT_vIrqHandler_##HWIRQGRP( EVHD_tenReceiveEvent enIrqGrpRxEvent ) \ + { \ + +#define PINT_MakePin(PinID, HWPin, Mode, Glitch, SendEvent) \ + if( gpio_get_pin_interrupt_flag( HWPin ) ) \ + { \ + EVHD_vSendEvent( SendEvent ); \ + gpio_clear_pin_interrupt_flag( HWPin ); \ + } \ + +#define PINT_MakeIRQHandlerEnd(HWIRGGRP) \ + } \ + +PINT_MakeConfig + +#undef PINT_MakeIRQHandlerStart +#undef PINT_MakePin +#undef PINT_MakeIRQHandlerEnd + +/* interface functions */ +#define PINT_MakeIRQHandlerStart(HWIRGGRP) \ + +#define PINT_MakePin(PinID, HWPin, Mode, Glitch, SendEvent) \ + if( Glitch != 0) \ + {\ + gpio_enable_pin_glitch_filter(HWPin);\ + }\ + gpio_enable_pin_interrupt( HWPin, Mode ); \ + +#define PINT_MakeIRQHandlerEnd(HWIRGGRP) \ + +void PINT_vInit( void ) +{ + PINT_MakeConfig +} +#undef PINT_MakeIRQHandlerStart +#undef PINT_MakePin +#undef PINT_MakeIRQHandlerEnd diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/PINT1c1.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/PINT1c1.h new file mode 100644 index 0000000..30be496 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/PINT1c1.h @@ -0,0 +1,15 @@ +#ifndef PINT_C1_H +#define PINT_C1_H + +#include "PINT1ce.h" + +typedef enum { + PINT_nenPinChange = 0, + PINT_nenRisingEdge = 1, + PINT_nenFallingEdge = 2 +} PINT_tenPinMode; + +/* interface prototypes */ +void PINT_vInit( void ); + +#endif /*PINT_C1_H*/ \ No newline at end of file diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/PINT1ce.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/PINT1ce.h new file mode 100644 index 0000000..9a1aff1 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/PINT1ce.h @@ -0,0 +1,36 @@ +#ifndef PINT_CE_H +#define PINT_CE_H + +#include "cdef.h" + +#define PINT_MakeConfig \ + PINT_MakeIRQHandlerStart(AVR32_GPIO_IRQ_1) \ + /* PinID, HW-Pin, Mode, Glitch, SendEvent */\ + PINT_MakePin( PINT_nenBtn0, GPIO_PUSH_BUTTON_0, PINT_nenFallingEdge, 0x1, EVHD_nenBtn0 ) \ + PINT_MakeIRQHandlerEnd(AVR32_GPIO_IRQ_1) \ + PINT_MakeIRQHandlerStart(AVR32_GPIO_IRQ_3) \ + /* PinID, HW-Pin, Mode, Glitch, SendEvent */\ + PINT_MakePin( PINT_nenBtn1, GPIO_PUSH_BUTTON_1, PINT_nenFallingEdge, 0x1, EVHD_nenBtn1 ) \ + PINT_MakeIRQHandlerEnd(AVR32_GPIO_IRQ_3) \ + + +#define PINT_MakeIRQHandlerStart(HWIRQGRP) \ + +#define PINT_MakePin(PinID, HWPin, Mode, Glitch, SendEvent) \ + +#define PINT_MakeIRQHandlerEnd(HWIRQGRP) \ + +#undef PINT_MakeIRQHandlerStart +#undef PINT_MakePin +#undef PINT_MakeIRQHandlerEnd + +#if 0 /* example */ +#define PINT_MakeConfig \ + PINT_MakeIRQHandlerStart(AVR32_GPIO_IRQ_4) \ + /* PinID, HW-Pin, Mode, Glitch, SendEvent */\ + PINT_MakePin( PINT_nenAD7607_Busy, AVR32_PIN_PB06, PINT_nenFallingEdge, 0x0, EVHD_nenAD7607_ConversionReady ) \ + PINT_MakeIRQHandlerEnd(AVR32_GPIO_IRQ_4) \ + +#endif /* example */ + +#endif /*PINT_CE_H*/ \ No newline at end of file diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/START1C1.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/START1C1.c new file mode 100644 index 0000000..e1fba85 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/START1C1.c @@ -0,0 +1,148 @@ +#include "START1c1.h" +#include + +#include "OS1c1.h" +#include "IVECT1c1.h" +#include "PINT1c1.h" + +/*CAN Subsystem*/ +#include "CAN1c1.h" +#include "IL1c1.h" +#include "CANIF1c1.h" +#include "CAND1c1.h" + +#define START_nTX_LOOPS (100) + +typedef enum +{ + START__nenOperationCyclic, + START__nenOperationBurst, + START__nenOperationNone +} START__tenOperationMode; + +volatile uint8_t START__u8MsgCount = 0; +volatile bool START__boSend100msMsg = false; +volatile START__tenOperationMode START__enOperationMode = START__nenOperationNone; + +extern bool CANIF__aboSendingActive[CAN__nenCh_NoOfChannels]; + +/*Clock initialisieren*/ +void START__vInitClock( void ) +{ + sysclk_init(); + wdt_disable(); +} + + + +/*Start von Allem*/ +void START_vMain( void ) +{ + gpio_enable_gpio_pin(LED0_GPIO); + gpio_configure_pin(LED0_GPIO, GPIO_DIR_OUTPUT | GPIO_INIT_LOW); + gpio_enable_gpio_pin(LED1_GPIO); + gpio_configure_pin(LED1_GPIO,GPIO_DIR_OUTPUT|GPIO_INIT_HIGH); + gpio_enable_gpio_pin(LED3_GPIO); + gpio_configure_pin(LED3_GPIO, GPIO_DIR_OUTPUT | GPIO_INIT_LOW); + START__vInitClock(); + TIMER_vInit(); + IVECT_vInit(); + PINT_vInit(); + OS_vInit(); + OS_vRun(); +} + + +/*Tasks*/ +OS_TASK( START_vIdle ) +{ + static uint8_t u8InitState = 0; + + if( u8InitState == 0) + { + /*Initialisierung der Module*/ + /*--------------------------*/ + + CAN_vInit(); + IL_vSetMessageSendCyclic(CAN_nenMsg_Dummy001,false); + CAND_vStart(CAN_nenCh0); + CAND_vEnableInterrupt(CAN_nenCh0); + + u8InitState = 1; + } + + /*Endlosschleife*/ + /*--------------*/ + while( 1 ) + { + OS_vSchedule(); + } +} + +void START_vSend100msMsg() +{ + static CAN_tstMessage stMsg = { { 0,0,0,0,0,0,0,0 },8,0x103 }; + if( START__boSend100msMsg && ( START__u8MsgCount <= START_nTX_LOOPS ) ) + { + stMsg.au8Data[0] = START__u8MsgCount; + CAND_boSend(CAN_nenCh0,&stMsg); + START__u8MsgCount++; + } + else + { + START__u8MsgCount = 0; + START__boSend100msMsg = false; + gpio_clr_gpio_pin(LED0_GPIO); + START__enOperationMode = START__nenOperationNone; + } +} + +void START_vBtn0Callback( EVHD_tenReceiveEvent enRxEvent ) +{ + if( START__enOperationMode != START__nenOperationNone ) + { + return; + } + START__enOperationMode = START__nenOperationCyclic; + gpio_set_gpio_pin(LED0_GPIO); + START__boSend100msMsg = true; +} + +void START__vCanBurst( void ); + +void START_vBtn1Callback( EVHD_tenReceiveEvent enRxEvent ) +{ + if( START__enOperationMode != START__nenOperationNone ) + { + return; + } + START__enOperationMode = START__nenOperationBurst; + gpio_set_gpio_pin(LED3_GPIO); + START__vCanBurst(); + gpio_clr_gpio_pin(LED3_GPIO); + START__enOperationMode = START__nenOperationNone; +} +void START__vCanBurst( void ) +{ + #define START__nNOOFBURSTMESSAGES (0xFFFF) + + uint16_t u16Cnt = 0; + CAN_tstMessage stMsg; + stMsg.u8Dlc = 2; + stMsg.CanId = 0x001; + + for( ; u16Cnt < START__nNOOFBURSTMESSAGES; u16Cnt++ ) + { + stMsg.au8Data[0] = (uint8_t) (0xFF & u16Cnt); + stMsg.au8Data[1] = (uint8_t) (0xFF & (u16Cnt>>8)); + CANIF__aboSendingActive[CAN_nenCh0] = true; + while( !CAND_boSend( CAN_nenCh0, &stMsg) ) + { + asm volatile ("nop"); + } + while( CANIF__aboSendingActive[CAN_nenCh0] ) + { + asm volatile ("nop"); + } + } +} \ No newline at end of file diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/START1C1.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/START1C1.h new file mode 100644 index 0000000..37a9e5b --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/START1C1.h @@ -0,0 +1,17 @@ +#ifndef START_H +#define START_H + +#include "cdef.h" + +#include "EVHD1c1.h" + +#define START_n100ms (100) + +/* Start des gesamten Systems */ +void START_vMain( void ); + +void START_vSend100msMsg(); +void START_vBtn0Callback( EVHD_tenReceiveEvent enRxEvent ); +void START_vBtn1Callback( EVHD_tenReceiveEvent enRxEvent ); + +#endif /*START_H*/ \ No newline at end of file diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/TIMER1c1.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/TIMER1c1.c new file mode 100644 index 0000000..1520935 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/TIMER1c1.c @@ -0,0 +1,122 @@ +#include +#include +#include "compiler.h" +#include "board.h" +#include "tc.h" +#include "gpio.h" + +#include "TIMER1c1.h" +#include "START1c1.h" + +#define TIMER_Make( TimerId, Unit, Callback ) \ + { Unit, Callback, 0, 0, 0, 0 }, + +#define OS_MakeCyclicTask( TaskId, pFunc, Cycle, Unit ) \ + { Unit, NULL, 0, 0, Cycle, 0 }, + +#define OS_MakeAlarmTask( TaskId, pFunc, Cycle, Unit ) \ + { Unit, NULL, 0, 0, Cycle, 0 }, + +#define OS_MakeNormalTask( TaskId, pFunc ) /*nix zu tun!*/ + +#define OS_MakeAutostartTask( TaskId, pFunc ) /*nix zu tun!*/ + + + +TIMER_tstConfig TIMER_astConfig[TIMER_nenNoOfChannels] = +{ + OS_MakeConfig + + TIMER_MakeConfig +}; + +#undef TIMER_Make +#undef OS_MakeCyclicTask +#undef OS_MakeAlarmTask +#undef OS_MakeNormalTask +#undef OS_MakeAutostartTask + + +/*Freilaufender Zähler*/ +TIMER_tstCounter TIMER__stCounter = {0,0,0}; +volatile uint32_t TIMER__u32TimerTicks1ms = 0; + +#define TC_CHANNEL 0 +#define FALSE 0 + + +void TIMER__vReadCurrentCounter( void ) +{ + static uint32_t u32LastHwTimer=0; + uint32_t u32Dif; + + u32Dif = (TIMER__u32TimerTicks1ms - u32LastHwTimer); + u32LastHwTimer = TIMER__u32TimerTicks1ms; + TIMER__stCounter.u32mSek += u32Dif; + + TIMER__stCounter.u32uSek = TIMER__stCounter.u32mSek * 1000; + TIMER__stCounter.u32Sek = TIMER__stCounter.u32mSek / 1000; + +} + + +void TIMER_vInit ( void ) +{ + volatile avr32_tc_t *tc = &AVR32_TC0; + // Options for waveform generation. + static const tc_waveform_opt_t WAVEFORM_OPT = + { + .channel = TC_CHANNEL, // Channel selection. + + .bswtrg = TC_EVT_EFFECT_NOOP, // Software trigger effect on TIOB. + .beevt = TC_EVT_EFFECT_NOOP, // External event effect on TIOB. + .bcpc = TC_EVT_EFFECT_NOOP, // RC compare effect on TIOB. + .bcpb = TC_EVT_EFFECT_NOOP, // RB compare effect on TIOB. + + .aswtrg = TC_EVT_EFFECT_NOOP, // Software trigger effect on TIOA. + .aeevt = TC_EVT_EFFECT_NOOP, // External event effect on TIOA. + .acpc = TC_EVT_EFFECT_NOOP, // RC compare effect on TIOA: toggle. + .acpa = TC_EVT_EFFECT_NOOP, // RA compare effect on TIOA: toggle (other possibilities are none, set and clear). + + .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,// Waveform selection: Up mode with automatic trigger(reset) on RC compare. + .enetrg = FALSE, // External event trigger enable. + .eevt = 0, // External event selection. + .eevtedg = TC_SEL_NO_EDGE, // External event edge selection. + .cpcdis = FALSE, // Counter disable when RC compare. + .cpcstop = FALSE, // Counter clock stopped with RC compare. + + .burst = FALSE, // Burst signal selection. + .clki = FALSE, // Clock inversion. + //.tcclks = TC_CLOCK_SOURCE_TC3 // Internal source clock 3, connected to fPBA / 8. + .tcclks = TC_CLOCK_SOURCE_TC2 // Internal source clock 3, connected to fPBC / 8. + }; + + static const tc_interrupt_t TC_INTERRUPT = + { + .etrgs = 0, + .ldrbs = 0, + .ldras = 0, + .cpcs = 1, + .cpbs = 0, + .cpas = 0, + .lovrs = 0, + .covfs = 0 + }; + + + tc_init_waveform(tc, &WAVEFORM_OPT); // Initialize the timer/counter waveform. + tc_write_rc(tc,TC_CHANNEL, 32000); + tc_configure_interrupts(tc,TC_CHANNEL,&TC_INTERRUPT); + tc_start(tc, TC_CHANNEL); +} + +void TIMER_v1msCallback( EVHD_tenReceiveEvent enRxEvent ) +{ + TIMER__u32TimerTicks1ms++; + tc_read_sr(&AVR32_TC0, TC_CHANNEL); + if( (TIMER__u32TimerTicks1ms % START_n100ms) == 0) + { + START_vSend100msMsg(); + } +} + diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/TIMER1c1.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/TIMER1c1.h new file mode 100644 index 0000000..0458ff8 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/TIMER1c1.h @@ -0,0 +1,143 @@ +#ifndef TIMER_C1_H +#define TIMER_C1_H + +#include "cdef.h" + +#include "OS1ce.h" +#include "TIMER1ce.h" +#include "EVHD1c1.h" + +#define TCD0 AVR32_TC0 + +#define TIMER_Make( TimerId, Unit, Callback ) \ + TimerId, + +#define OS_MakeCyclicTask( TaskId, pFunc, Cycle, Unit ) \ + TIMER_nenCyclic##TaskId, + +#define OS_MakeAlarmTask( TaskId, pFunc, Cycle, Unit ) \ + TIMER_nenAlarm##TaskId, + +#define OS_MakeNormalTask( TaskId, pFunc ) \ + +#define OS_MakeAutostartTask( TaskId, pFunc ) \ + +typedef enum +{ + OS_MakeConfig + + TIMER_MakeConfig + + /*Muss der letzte Eintrag sein!*/ + TIMER_nenNoOfChannels +}TIMER_tenChannel; + +#undef TIMER_Make +#undef OS_MakeCyclicTask +#undef OS_MakeAlarmTask +#undef OS_MakeNormalTask +#undef OS_MakeAutostartTask + + +typedef enum +{ + TIMER_nenUnit1us, + TIMER_nenUnit1ms, + TIMER_nenUnit1s, +}TIMER_tenUnit; + +typedef struct +{ + uint32_t u32uSek; + uint32_t u32mSek; + uint32_t u32Sek; +}TIMER_tstCounter; + +typedef struct +{ + const TIMER_tenUnit enUnit; + void (* const pfctCbExpired)( void ); //Callback, die aufgrufen wird, wenn ein Timer abgelaufen ist + uint32_t u32StartValue; + uint32_t u32StopValue; + uint32_t u32SetValue; + uint8_t biRunning : 1; +}TIMER_tstConfig; + +/*Konfiguration des TIMER-Moduls*/ +extern TIMER_tstConfig TIMER_astConfig[TIMER_nenNoOfChannels]; + +/*Freilaufender Zähler*/ +extern TIMER_tstCounter TIMER__stCounter; + +extern volatile uint32_t TIMER__u32TimerTicks1ms; + +void TIMER_vInit ( void ); + +void TIMER_v1msCallback( EVHD_tenReceiveEvent enRxEvent ); + +#define TIMER_u32GetSystemTime( /*TIMER_tenUnit*/ enUnit ) \ +( TIMER__vReadCurrentCounter(), \ + enUnit == TIMER_nenUnit1us ? TIMER__stCounter.u32uSek \ + : enUnit == TIMER_nenUnit1ms ? TIMER__stCounter.u32mSek \ + : /*TIMER_nenUnit1s*/ TIMER__stCounter.u32Sek \ +) \ + +#define TIMER_vStart( /*TIMER_tenChannel*/ enChannel ) \ +( TIMER__vReadCurrentCounter(), \ + TIMER_astConfig[enChannel].biRunning = 1, \ + TIMER_astConfig[enChannel].enUnit == TIMER_nenUnit1us ? (TIMER_astConfig[enChannel].u32StartValue = TIMER__stCounter.u32uSek) \ + : TIMER_astConfig[enChannel].enUnit == TIMER_nenUnit1ms ? (TIMER_astConfig[enChannel].u32StartValue = TIMER__stCounter.u32mSek) \ + : /*TIMER_nenUnit1s*/ (TIMER_astConfig[enChannel].u32StartValue = TIMER__stCounter.u32Sek ) \ +) \ + +#define TIMER_vStop( /*TIMER_tenChannel*/ enChannel ) \ +( TIMER__vReadCurrentCounter(), \ + TIMER_astConfig[enChannel].biRunning = 0, \ + TIMER_astConfig[enChannel].enUnit == TIMER_nenUnit1us ? (TIMER_astConfig[enChannel].u32StopValue = TIMER__stCounter.u32uSek) \ + : TIMER_astConfig[enChannel].enUnit == TIMER_nenUnit1ms ? (TIMER_astConfig[enChannel].u32StopValue = TIMER__stCounter.u32mSek) \ + : /*TIMER_nenUnit1s*/ (TIMER_astConfig[enChannel].u32StopValue = TIMER__stCounter.u32Sek ) \ +) \ + +#define TIMER_vRestart( /*TIMER_tenChannel*/ enChannel ) \ +( TIMER__vReadCurrentCounter(), \ + TIMER_astConfig[enChannel].biRunning = 1, \ + TIMER_astConfig[enChannel].enUnit == TIMER_nenUnit1us ? (TIMER_astConfig[enChannel].u32StartValue = TIMER__stCounter.u32uSek - TIMER_u32GetValue( enChannel ) )\ + : TIMER_astConfig[enChannel].enUnit == TIMER_nenUnit1ms ? (TIMER_astConfig[enChannel].u32StartValue = TIMER__stCounter.u32mSek - TIMER_u32GetValue( enChannel ) )\ + : /*TIMER_nenUnit1s*/ (TIMER_astConfig[enChannel].u32StartValue = TIMER__stCounter.u32Sek - TIMER_u32GetValue( enChannel ) )\ +) + +#define TIMER_u32GetValue( enChannel ) \ +( TIMER_astConfig[enChannel].u32StopValue - TIMER_astConfig[enChannel].u32StartValue) \ + +#define TIMER_vSet( /*TIMER_tenChannel*/ enChannel, /*uint32_t*/ u32Value ) \ +( TIMER_astConfig[enChannel].u32SetValue = u32Value ) \ + +#define TIMER_vReset TIMER_vStart + +#define TIMER_boIsTimeRunning( /*TIMER_tenChannel*/ enChannel ) \ +( TIMER_astConfig[enChannel].biRunning == 1 ) \ + + +#define TIMER__boIsTimeExpired( /*TIMER_tenChannel*/ enChannel ) \ +( TIMER__vReadCurrentCounter(), \ + TIMER_astConfig[enChannel].enUnit == TIMER_nenUnit1us ? ((TIMER__stCounter.u32uSek - TIMER_astConfig[enChannel].u32StartValue) >= TIMER_astConfig[enChannel].u32SetValue) \ + : TIMER_astConfig[enChannel].enUnit == TIMER_nenUnit1ms ? ((TIMER__stCounter.u32mSek - TIMER_astConfig[enChannel].u32StartValue) >= TIMER_astConfig[enChannel].u32SetValue) \ + : /*TIMER_nenUnit1s*/ ((TIMER__stCounter.u32Sek - TIMER_astConfig[enChannel].u32StartValue) >= TIMER_astConfig[enChannel].u32SetValue) \ +) + +#define TIMER_boIsTimeExpired( /*TIMER_tenChannel*/ enChannel ) \ +( TIMER_astConfig[enChannel].biRunning ? TIMER__boIsTimeExpired(enChannel) ? TIMER_astConfig[enChannel].biRunning = 0, true \ + : false /*Timer noch nicht abgelaufen*/ \ + : false /*Timer wurde nicht gestartet*/ \ +) + + + +#define TIMER_vSubValue( /*TIMER_tenChannel*/ enChannel, /*uint32_t*/ u32Vaule ) \ +( TIMER_astConfig[enChannel].u32StartValue += u32Vaule, \ + TIMER_astConfig[enChannel].biRunning = 1 \ +) \ + +void TIMER__vReadCurrentCounter( void ); + +#endif /*TIMER_C1_H*/ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/TIMER1ce.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/TIMER1ce.h new file mode 100644 index 0000000..6e19c8b --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/TIMER1ce.h @@ -0,0 +1,31 @@ +#ifndef TIMER_CE_H +#define TIMER_CE_H + +#include "cdef.h" + +/****************************************************************** + * * + * Timer C0 - PWM Display siehe PWM1Ce.h * + * Timer C1 - Multiplex-(ISR) PWM1Ce.h * + * Timer D0 - Mastertimer siehe TIMER1c1.c * + * Timer D1 - Extension Timer D0 " * + * * + ******************************************************************/ + + + +#define TIMER_MakeConfig \ +/* TimerID, Unint, pCallback */ \ +TIMER_Make( TIMER_nenIdleTime, TIMER_nenUnit1us, NULL ) \ +TIMER_Make( TIMER_nenIdle1s, TIMER_nenUnit1ms, NULL ) \ +TIMER_Make( TIMER_nenExea_Blitz, TIMER_nenUnit1ms, NULL ) \ + + + +#define TIMER_Make( TimerId, Unit, Callback ) \ + +#undef TIMER_Make + + + +#endif /*TIMER_CE_H*/ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf.h new file mode 100644 index 0000000..0c9292d --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Autogenerated API include file for the AVR Software Framework (ASF) + * + * Copyright (C) 2011 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef ASF_H +#define ASF_H + +/* + * This file includes all API header files for the selected drivers from ASF. + * + * The file is automatically generated and will be re-written when + * running the ASF driver selector tool. Any changes will be discarded. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#endif // ASF_H diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/boards/uc3c_ek/led.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/boards/uc3c_ek/led.h new file mode 100644 index 0000000..0b9713f --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/boards/uc3c_ek/led.h @@ -0,0 +1,185 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3C UC3C_EK board LEDs support package. + * + * This file contains definitions and services related to the LED features of + * the UC3C-EK board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _LED_H_ +#define _LED_H_ + +#include "compiler.h" + + +/*! \name Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#define LED0 0x01 +#define LED1 0x02 +#define LED2 0x04 +#define LED3 0x08 +//! @} + + +/*! \brief Gets the last state of all LEDs set through the LED API. + * + * \return State of all LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display(void); + +/*! \brief Sets the state of all LEDs. + * + * \param leds New state of all LEDs (1 bit per LED). + * + * \note The pins of all LEDs are set to GPIO output mode. + */ +extern void LED_Display(U32 leds); + +/*! \brief Gets the last state of the specified LEDs set through the LED API. + * + * \param mask LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Mask(U32 mask); + +/*! \brief Sets the state of the specified LEDs. + * + * \param mask LEDs of which to set the state (1 bit per LED). + * + * \param leds New state of the specified LEDs (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Mask(U32 mask, U32 leds); + +/*! \brief Tests the last state of the specified LEDs set through the LED API. + * + * \param leds LEDs of which to test the state (1 bit per LED). + * + * \return \c true if at least one of the specified LEDs has a state on, else + * \c false. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern bool LED_Test(U32 leds); + +/*! \brief Turns off the specified LEDs. + * + * \param leds LEDs to turn off (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Off(U32 leds); + +/*! \brief Turns on the specified LEDs. + * + * \param leds LEDs to turn on (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_On(U32 leds); + +/*! \brief Toggles the specified LEDs. + * + * \param leds LEDs to toggle (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Toggle(U32 leds); + +/*! \brief Gets as a bit-field the last state of the specified LEDs set through + * the LED API. + * + * \param field LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED, beginning with the first + * specified LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Field(U32 field); + +/*! \brief Sets as a bit-field the state of the specified LEDs. + * + * \param field LEDs of which to set the state (1 bit per LED). + * \param leds New state of the specified LEDs (1 bit per LED, beginning with + * the first specified LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Field(U32 field, U32 leds); + +/*! \brief Gets the intensity of the specified LED. + * + * \param led LED of which to get the intensity (1 bit per LED; only the least + * significant set bit is used). + * + * \return Intensity of the specified LED (0x00 to 0xFF). + * + * \warning The PWM channel of the specified LED is supposed to be used only by + * this module. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U8 LED_Get_Intensity(U32 led); + +/*! \brief Sets the intensity of the specified LEDs. + * + * \param leds LEDs of which to set the intensity (1 bit per LED). + * \param intensity New intensity of the specified LEDs (0x00 to 0xFF). + * + * \warning The PWM channels of the specified LEDs are supposed to be used only + * by this module. + * + * \note The pins of the specified LEDs are set to PWM output mode. + */ +extern void LED_Set_Intensity(U32 leds, U8 intensity); + + +#endif // _LED_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/boards/uc3c_ek/uc3c_ek.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/boards/uc3c_ek/uc3c_ek.h new file mode 100644 index 0000000..48c3430 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/boards/uc3c_ek/uc3c_ek.h @@ -0,0 +1,323 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3C UC3C_EK board header file. + * + * This file contains definitions and services related to the features of the + * UC3C_EK board. + * + * To use this board, define BOARD=UC3C_EK. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3C devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _UC3C_EK_H_ +#define _UC3C_EK_H_ + +#include "compiler.h" + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. +# include "led.h" +#endif // __AVR32_ABI_COMPILER__ + + +#ifdef AVR32_SCIF_101_H_INCLUDED +#define AVR32_SCIF_OSCCTRL0_STARTUP_2048_RCOSC 0x00000003 +#define AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC 0x00000006 +#define AVR32_SCIF_OSCCTRL32_STARTUP_8192_RCOSC 0x00000002 +#endif + + +/*! \name Oscillator Definitions + */ +//! @{ + +#define FOSC32 AVR32_SCIF_OSC32_FREQUENCY //!< Osc32 frequency: Hz. +#define OSC32_STARTUP AVR32_SCIF_OSCCTRL32_STARTUP_8192_RCOSC //!< Osc32 startup time: RCOsc periods. + +// Osc0 crystal is not mounted by default. Set the following definitions to the +// appropriate values if a custom Osc0 crystal is mounted on your STK600 +#define FOSC0 16000000 //!< Osc0 frequency: Hz. +#define OSC0_STARTUP AVR32_SCIF_OSCCTRL0_STARTUP_2048_RCOSC //!< Osc0 startup time: RCOsc periods. + +// Osc1 crystal is not mounted by default. Set the following definitions to the +// appropriate values if a custom Osc1 crystal is mounted on your board. +// #define FOSC1 12000000 //!< Osc1 frequency: Hz. +// #define OSC1_STARTUP AVR32_SCIF_OSCCTRL1_STARTUP_2048_RCOSC //!< Osc1 startup time: RCOsc periods. + +//! @} + +#define BOARD_OSC0_HZ 16000000 +#define BOARD_OSC0_STARTUP_US 2000 +#define BOARD_OSC0_IS_XTAL true +#define BOARD_OSC32_HZ 32768 +#define BOARD_OSC32_STARTUP_US 71000 +#define BOARD_OSC32_IS_XTAL true + +/*! \name SDRAM Definitions + */ +//! @{ + +//! Part header file of used SDRAM(s). +#define SDRAM_PART_HDR "mt48lc16m16a2tg7e/mt48lc16m16a2tg7e.h" + +//! Data bus width to use the SDRAM(s) with (16 or 32 bits; always 16 bits on +//! UC3). +#define SDRAM_DBW 16 +//! @} + + +/*! \name USB Definitions + */ +//! @{ +//! Multiplexed pin used for USB_ID: AVR32_USBB_USB_ID_x_x. +//! To be selected according to the AVR32_USBB_USB_ID_x_x_PIN and +//! AVR32_USBB_USB_ID_x_x_FUNCTION definitions from . +#if (defined AVR32_USBB) +# define USB_ID AVR32_USBB_ID_0_0 +#else +# define USB_ID AVR32_USBC_ID +#endif + +//! Multiplexed pin used for USB_VBOF: AVR32_USBB_USB_VBOF_x_x. +//! To be selected according to the AVR32_USBB_USB_VBOF_x_x_PIN and +//! AVR32_USBB_USB_VBOF_x_x_FUNCTION definitions from . +#if (defined AVR32_USBB) +# define USB_VBOF AVR32_USBB_VBOF_0_0 +#else +# define USB_VBOF AVR32_USBC_VBOF +#endif + +//! Active level of the USB_VBOF output pin. +# define USB_VBOF_ACTIVE_LEVEL LOW + +//! USB overcurrent detection pin. +# define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PB7 + +//! @} + + +//! Number of LEDs. +#define LED_COUNT 4 + +/*! \name GPIO Connections of LEDs + */ +//! @{ +# define LED0_GPIO AVR32_PIN_PA08 +# define LED1_GPIO AVR32_PIN_PD23 +# define LED2_GPIO AVR32_PIN_PC13 +# define LED3_GPIO AVR32_PIN_PD22 +//! @} + +/*! \name PWM Channels of LEDs + */ +//! @{ +#define LED0_PWM (-1) +#define LED1_PWM (-1) +#define LED2_PWM (-1) +#define LED3_PWM (-1) +//! @} + +/*! \name PWM Functions of LEDs + */ +//! @{ +/* TODO: Implement PWM functionality */ +#define LED0_PWM_FUNCTION (-1)//AVR32_PWM_0_FUNCTION +#define LED1_PWM_FUNCTION (-1)//AVR32_PWM_1_FUNCTION +#define LED2_PWM_FUNCTION (-1) +#define LED3_PWM_FUNCTION (-1) +//! @} + +/*! \name Color Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#define LED_MONO0_GREEN LED0 +#define LED_MONO1_GREEN LED1 +#define LED_MONO2_GREEN LED2 +#define LED_MONO3_GREEN LED3 +//! @} + +/*! \name GPIO Connections of Push Buttons + */ +//! @{ +#define GPIO_PUSH_BUTTON_0 AVR32_PIN_PA14 +#define GPIO_PUSH_BUTTON_0_PRESSED 0 +#define GPIO_PUSH_BUTTON_1 AVR32_PIN_PA29 +#define GPIO_PUSH_BUTTON_1_PRESSED 0 +//! @} + +/*! \name GPIO Connections of J33 + */ +//! @{ +# define UH AVR32_PIN_PB08 +# define UL AVR32_PIN_PB09 +# define VH AVR32_PIN_PB10 +# define VL AVR32_PIN_PB11 +# define WH AVR32_PIN_PB12 +# define WL AVR32_PIN_PB13 +# define XH AVR32_PIN_PB14 +# define XL AVR32_PIN_PB15 +# define ShV AVR32_PIN_PA21 +//! @} + +/*! \name SPI Connections of the AT45DBX Data Flash Memory + */ +//! @{ +#define AT45DBX_SPI (&AVR32_SPI1) +#define AT45DBX_SPI_NPCS 1 +#define AT45DBX_SPI_SCK_PIN AVR32_SPI1_SCK_0_1_PIN +#define AT45DBX_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_1_FUNCTION +#define AT45DBX_SPI_MISO_PIN AVR32_SPI1_MISO_0_1_PIN +#define AT45DBX_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_1_FUNCTION +#define AT45DBX_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_1_PIN +#define AT45DBX_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_1_FUNCTION +#define AT45DBX_SPI_NPCS0_PIN AVR32_SPI1_NPCS_1_2_PIN +#define AT45DBX_SPI_NPCS0_FUNCTION AVR32_SPI1_NPCS_1_2_FUNCTION +//! @} + +/*! \name GPIO and SPI Connections of the SD/MMC Connector + */ +//! @{ +#define SD_MMC_CARD_DETECT_PIN AVR32_PIN_PA28 +#define SD_MMC_WRITE_PROTECT_PIN AVR32_PIN_PD30 +#define SD_MMC_SPI (&AVR32_SPI1) +#define SD_MMC_SPI_NPCS 3 +#define SD_MMC_SPI_SCK_PIN AVR32_SPI1_SCK_0_1_PIN +#define SD_MMC_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_1_FUNCTION +#define SD_MMC_SPI_MISO_PIN AVR32_SPI1_MISO_0_1_PIN +#define SD_MMC_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_1_FUNCTION +#define SD_MMC_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_1_PIN +#define SD_MMC_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_1_FUNCTION +#define SD_MMC_SPI_NPCS_PIN AVR32_SPI1_NPCS_3_2_PIN +#define SD_MMC_SPI_NPCS_FUNCTION AVR32_SPI1_NPCS_3_2_FUNCTION +//! @} + + +//! @} + +/*! \name ET024006DHU TFT display + */ +//! @{ + +#define ET024006DHU_TE_PIN AVR32_PIN_PD19 +#define ET024006DHU_RESET_PIN AVR32_PIN_PD16 +#define ET024006DHU_BL_PIN AVR32_TC0_B0_0_2_PIN +#define ET024006DHU_BL_FUNCTION AVR32_TC0_B0_0_2_FUNCTION +#define ET024006DHU_DNC_PIN AVR32_EBI_ADDR_22_PIN +#define ET024006DHU_DNC_FUNCTION AVR32_EBI_ADDR_22_FUNCTION +#define ET024006DHU_EBI_NCS_PIN AVR32_EBI_NCS_PIN +#define ET024006DHU_EBI_NCS_FUNCTION AVR32_EBI_NCS_FUNCTION + +//! @} +/*! \name Optional SPI connection to the TFT + */ +//! @{ + +#define ET024006DHU_SPI (&AVR32_SPI1) +#define ET024006DHU_SPI_NPCS 1 +#define ET024006DHU_SPI_SCK_PIN AVR32_SPI1_SCK_0_1_PIN +#define ET024006DHU_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_1_FUNCTION +#define ET024006DHU_SPI_MISO_PIN AVR32_SPI1_MISO_0_1_PIN +#define ET024006DHU_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_1_FUNCTION +#define ET024006DHU_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_1_PIN +#define ET024006DHU_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_1_FUNCTION +#define ET024006DHU_SPI_NPCS_PIN AVR32_SPI1_NPCS_2_2_PIN +#define ET024006DHU_SPI_NPCS_FUNCTION AVR32_SPI1_NPCS_2_2_FUNCTION + +//! @} + + +/*! \name Audio amplifier connection to the DAC + */ +//! @{ + +#define TPA6130_TWI (&AVR32_TWIM0_ADDRESS) +#define TPA6130_TWI_SCL_PIN AVR32_TWIMS0_TWCK_0_1_PIN +#define TPA6130_TWI_SCL_FUNCTION AVR32_TWIMS0_TWCK_0_1_FUNCTION +#define TPA6130_TWI_SDA_PIN AVR32_TWIMS0_TWD_0_0_PIN +#define TPA6130_TWI_SDA_FUNCTION AVR32_TWIMS0_TWD_0_0_FUNCTION + +/*! \name USART connection to the UC3B board controller + */ +//! @{ +#define USART (&AVR32_USART2) +#define USART_RXD_PIN AVR32_USART2_RXD_0_1_PIN +#define USART_RXD_FUNCTION AVR32_USART2_RXD_0_1_FUNCTION +#define USART_TXD_PIN AVR32_USART2_TXD_0_1_PIN +#define USART_TXD_FUNCTION AVR32_USART2_TXD_0_1_FUNCTION +#define USART_IRQ AVR32_USART2_IRQ +#define USART_IRQ_GROUP AVR32_USART2_IRQ_GROUP +#define USART_SYSCLK SYSCLK_USART2 +//! @} + +#define ADC_VEXT_PIN AVR32_PKGANA_ADCIN5_0_0_PIN +#define ADC_VEXT_FUNCTION AVR32_PKGANA_ADCIN5_0_0_FUNCTION + +/*! \name LCD Connections of the ET024006DHU display + */ +//! @{ +#define ET024006DHU_SMC_USE_NCS 0 +#define ET024006DHU_SMC_COMPONENT_CS "smc_et024006dhu.h" + +#define ET024006DHU_EBI_DATA_0 AVR32_EBI_DATA_0 +#define ET024006DHU_EBI_DATA_1 AVR32_EBI_DATA_1 +#define ET024006DHU_EBI_DATA_2 AVR32_EBI_DATA_2 +#define ET024006DHU_EBI_DATA_3 AVR32_EBI_DATA_3 +#define ET024006DHU_EBI_DATA_4 AVR32_EBI_DATA_4 +#define ET024006DHU_EBI_DATA_5 AVR32_EBI_DATA_5 +#define ET024006DHU_EBI_DATA_6 AVR32_EBI_DATA_6 +#define ET024006DHU_EBI_DATA_7 AVR32_EBI_DATA_7 +#define ET024006DHU_EBI_DATA_8 AVR32_EBI_DATA_8 +#define ET024006DHU_EBI_DATA_9 AVR32_EBI_DATA_9 +#define ET024006DHU_EBI_DATA_10 AVR32_EBI_DATA_10 +#define ET024006DHU_EBI_DATA_11 AVR32_EBI_DATA_11 +#define ET024006DHU_EBI_DATA_12 AVR32_EBI_DATA_12 +#define ET024006DHU_EBI_DATA_13 AVR32_EBI_DATA_13 +#define ET024006DHU_EBI_DATA_14 AVR32_EBI_DATA_14 +#define ET024006DHU_EBI_DATA_15 AVR32_EBI_DATA_15 + +#define ET024006DHU_EBI_ADDR_21 AVR32_EBI_ADDR_22 + +#define ET024006DHU_EBI_NWE AVR32_EBI_NWE0 +#define ET024006DHU_EBI_NRD AVR32_EBI_NRD +#define ET024006DHU_EBI_NCS AVR32_EBI_NCS_0 +//! @} + +#endif // _UC3C_EK_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/canif/canif.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/canif/canif.c new file mode 100644 index 0000000..6af0fd8 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/canif/canif.c @@ -0,0 +1,115 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief CANIF driver for AVR32 UC3. + * + * This file contains basic functions for the AVR32 CAN, with support for all + * modes, settings and clock speeds. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a CANIF module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include "compiler.h" +#include "preprocessor.h" +#include "canif.h" + +void canif_clear_all_mob(uint8_t ch, + uint8_t nb_mob) +{ + uint8_t mob_number; + + for (mob_number = 0; mob_number < nb_mob; mob_number++) { + CANIF_clr_mob(ch,mob_number) + } +} + +uint8_t canif_get_mob_free(uint8_t ch) +{ + uint8_t mob_number = CANIF_mob_get_mob_free(ch); + + if ((mob_number & 0x20) == 0x20) { + return (NO_MOB); + } + + return mob_number; +} + +uint8_t canif_get_mob_status(uint8_t ch, + uint8_t mob) +{ + uint8_t mob_status; + + // Test if MOb ENABLE or DISABLE + if (!(CANIF_mob_enable_status(ch, mob))) { + return(MOB_DISABLE); + } + + mob_status = CANIF_mob_get_status(ch,mob); + + mob_status &= ((1<> AVR32_CANIF_CANSR_CES_OFFSET ) +#define CANIF_channel_overload_status(ch) ( (AVR32_CANIF.channel[ch].cansr&AVR32_CANIF_CANSR_OVS_MASK) >> AVR32_CANIF_CANSR_OVS_OFFSET ) +#define CANIF_channel_receive_status(ch) ( (AVR32_CANIF.channel[ch].cansr&AVR32_CANIF_CANSR_RS_MASK) >> AVR32_CANIF_CANSR_RS_OFFSET ) +#define CANIF_channel_transmit_status(ch) ( (AVR32_CANIF.channel[ch].cansr&AVR32_CANIF_CANSR_TS_MASK) >> AVR32_CANIF_CANSR_TS_OFFSET ) + +//! CANIFCFG Register Access +#define CANIF_CHANNEL_MODE_NORMAL 0 +#define CANIF_CHANNEL_MODE_LISTENING 1 +#define CANIF_CHANNEL_MODE_LOOPBACK 2 +#define CANIF_get_channel_mode(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_CMODE_MASK)>> AVR32_CANIF_CANCFG_CMODE_OFFSET) ) +#define CANIF_set_channel_mode(ch,mode) { AVR32_CANIF.channel[ch].cancfg &= ~(AVR32_CANIF_CANCFG_CMODE_MASK); \ + AVR32_CANIF.channel[ch].cancfg |= (mode<> AVR32_CANIF_CANCFG_OVRM_OFFSET) ) +#define CANIF_set_overrun_mode(ch) { AVR32_CANIF.channel[ch].cancfg |= (1<> AVR32_CANIF_CANCFG_PHS1_OFFSET) ) +#define CANIF_set_phs1(ch,phs1) { AVR32_CANIF.channel[ch].cancfg &= ~(AVR32_CANIF_CANCFG_PHS1_MASK); \ + AVR32_CANIF.channel[ch].cancfg |= (phs1<> AVR32_CANIF_CANCFG_PHS2_OFFSET) ) +#define CANIF_set_phs2(ch,phs2) { AVR32_CANIF.channel[ch].cancfg &= ~(AVR32_CANIF_CANCFG_PHS2_MASK); \ + AVR32_CANIF.channel[ch].cancfg |= (phs2<> AVR32_CANIF_CANCFG_PRES_OFFSET) ) +#define CANIF_set_pres(ch,pres) { AVR32_CANIF.channel[ch].cancfg &= ~(AVR32_CANIF_CANCFG_PRES_MASK); \ + AVR32_CANIF.channel[ch].cancfg |= (pres<> AVR32_CANIF_CANCFG_PRS_OFFSET) ) +#define CANIF_set_prs(ch,prs) { AVR32_CANIF.channel[ch].cancfg &= ~(AVR32_CANIF_CANCFG_PRS_MASK); \ + AVR32_CANIF.channel[ch].cancfg |= (prs<> AVR32_CANIF_CANCFG_SJW_OFFSET) ) +#define CANIF_set_sjw(ch,sjw) { AVR32_CANIF.channel[ch].cancfg &= ~(AVR32_CANIF_CANCFG_SJW_MASK); \ + AVR32_CANIF.channel[ch].cancfg |= (sjw<> AVR32_CANIF_CANCFG_SM_OFFSET) ) +#define CANIF_set_sm(ch,sm) { AVR32_CANIF.channel[ch].cancfg |= (sm<> AVR32_CANIF_CANFC_EMODE_OFFSET) } +#define CANIF_get_tec(ch) { ((AVR32_CANIF.channel[ch].canfc & AVR32_CANIF_CANFC_TEC_MASK)>> AVR32_CANIF_CANFC_TEC_OFFSET) } +#define CANIF_get_rec(ch) { ((AVR32_CANIF.channel[ch].canfc & AVR32_CANIF_CANFC_REC_MASK)>> AVR32_CANIF_CANFC_REC_OFFSET) } + +//! CANIFIER Register Access +#define CANIF_enable_wakeup_interrupt(ch) { AVR32_CANIF.channel[ch].canier = AVR32_CANIF_CANIER_WKUPIM_MASK; } +#define CANIF_enable_interrupt(ch) { AVR32_CANIF.channel[ch].canier = AVR32_CANIF_CANIER_TXOKIM_MASK | \ + AVR32_CANIF_CANIER_RXOKIM_MASK | \ + AVR32_CANIF_CANIER_CERRIM_MASK | \ + AVR32_CANIF_CANIER_BOFFIM_MASK | \ + AVR32_CANIF_CANIER_WKUPIM_MASK; } + +//! CANIFIDR Register Access +#define CANIF_disable_wakeup_interrupt(ch) { AVR32_CANIF.channel[ch].canidr = AVR32_CANIF_CANIDR_WKUPIM_MASK; } +#define CANIF_disable_interrupt(ch) { AVR32_CANIF.channel[ch].canidr = AVR32_CANIF_CANIDR_TXOKIM_MASK | \ + AVR32_CANIF_CANIDR_RXOKIM_MASK | \ + AVR32_CANIF_CANIDR_CERRIM_MASK | \ + AVR32_CANIF_CANIDR_BOFFIM_MASK; } + +//! CANIFISCR Register Access +#define CANIF_get_interrupt_status(ch) ( AVR32_CANIF.channel[ch].canisr) +#define CANIF_get_interrupt_error_status(ch) ( AVR32_CANIF.channel[ch].canisr & 0x3F) +#define CANIF_get_interrupt_lastmob_selected(ch)( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_LSMOB_MASK)>> AVR32_CANIF_CANISR_LSMOB_OFFSET )) +#define CANIF_get_interrupt_wakeup_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_WKUP_MASK)>> AVR32_CANIF_CANISR_WKUP_OFFSET )) +#define CANIF_get_interrupt_berr_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_BERR_MASK)>> AVR32_CANIF_CANISR_BERR_OFFSET )) +#define CANIF_get_interrupt_serr_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_SERR_MASK)>> AVR32_CANIF_CANISR_SERR_OFFSET )) +#define CANIF_get_interrupt_cerr_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_cERR_MASK)>> AVR32_CANIF_CANISR_CERR_OFFSET )) +#define CANIF_get_interrupt_ferr_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_FERR_MASK)>> AVR32_CANIF_CANISR_FERR_OFFSET )) +#define CANIF_get_interrupt_aerr_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_AERR_MASK)>> AVR32_CANIF_CANISR_AERR_OFFSET )) +#define CANIF_get_interrupt_boff_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_BOFF_MASK)>> AVR32_CANIF_CANISR_BOFF_OFFSET )) +#define CANIF_clr_interrupt_status(ch) { AVR32_CANIF.channel[ch].caniscr = CANIF_get_interrupt_status(ch); } + +//! MOBCTRL Register Access +#define CANIF_get_mobctrl(ch,mob) (((unsigned volatile long*)&(AVR32_CANIF.channel[ch].mobctrl))[mob*3]) +#define CANIF_set_mobctrl(ch,mob,val) (((unsigned volatile long*)&(AVR32_CANIF.channel[ch].mobctrl))[mob*3]=val) +#define CANIF_mobctrl(ch,mob) (((unsigned volatile long*)&(AVR32_CANIF.channel[ch].mobctrl))[mob*3]) +#define CANIF_mob_clr_automode(ch,mob) { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)&~(1<>AVR32_CANIF_DLC_OFFSET ) +#define CANIF_mob_clr_dir(ch,mob) { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)&~(1<> AVR32_CANIF_DIR_OFFSET ) + +//! MOBSR Register Access +#define CANIF_mob_get_status(ch,mob) (((unsigned volatile long*) &(AVR32_CANIF.channel[ch].mobsr))[mob*3]) +#define CANIF_mob_set_status(ch,mob,val) {((unsigned volatile long*) &(AVR32_CANIF.channel[ch].mobscr))[mob*3]=val;} +#define CANIF_mob_clear_status(ch,mob) {CANIF_mob_set_status(ch,mob,0x0F)} + +//! MOBSCH Register Access +#define CANIF_mob_get_mob_free(ch) ((AVR32_CANIF.channel[ch].mobsch&AVR32_CANIF_MOBSCH_MAV_MASK)>>AVR32_CANIF_MOBSCH_MAV_OFFSET) +#define CANIF_mob_get_mob_rxok(ch) ((AVR32_CANIF.channel[ch].mobsch&AVR32_CANIF_MOBSCH_MRXOK_MASK)>>AVR32_CANIF_MOBSCH_MRXOK_OFFSET) +#define CANIF_mob_get_mob_txok(ch) ((AVR32_CANIF.channel[ch].mobsch&AVR32_CANIF_MOBSCH_MTXOK_MASK)>>AVR32_CANIF_MOBSCH_MTXOK_OFFSET) + +//! MOBER Register Access +#define CANIF_mob_enable(ch,mob) {AVR32_CANIF.channel[ch].mober = 1<> mob)&1) + +//! MOBIER Register Access +#define CANIF_mob_enable_interrupt(ch,mob) {AVR32_CANIF.channel[ch].mobier = 1<> mob)& 1) + +//! MTXISCR Register Access +#define CANIF_mob_clear_txok_status(ch,mob) {AVR32_CANIF.channel[ch].mtxiscr = 1<> mob)& 1) + +#define CANIF_SIZE_OF_CANIF_MSG (sizeof(can_msg_t)) +#define CANIF_config_tx(ch,mob) {CANIF_mob_set_dir(ch,mob) } +#define CANIF_config_rx(ch,mob) {CANIF_mob_clr_dir(ch,mob) } + +#define CANIF_mob_allocate(ch) (CANIF_mob_get_mob_free(ch)) +#define CANIF_mob_free_get_addr_data(ch) (CANIF_SIZE_OF_CANIF_MSG*CANIF_mob_get_mob_free(ch)+CANIF_get_ram_add(ch)) +#define CANIF_mob_free_get_ptr_data(ch) ((can_msg_t *)(CANIF_SIZE_OF_CANIF_MSG*CANIF_mob_get_mob_free(ch)+CANIF_get_ram_add(ch))) +#define CANIF_mob_free(ch,mob) {CANIF_mob_disable(ch,mob)} +#define CANIF_mob_get_addr_data(ch,mob) ((CANIF_SIZE_OF_CANIF_MSG*mob+CANIF_get_ram_add(ch))) +#define CANIF_mob_get_ptr_data(ch,mob) ((can_msg_t *)(CANIF_SIZE_OF_CANIF_MSG*mob+CANIF_get_ram_add(ch))) + +#define CANIF_set_idemask(ch,mob) {(CANIF_mob_get_ptr_data(ch,mob))->ide_mask_bit = 1;} +#define CANIF_clr_idemask(ch,mob) {(CANIF_mob_get_ptr_data(ch,mob))->ide_mask_bit = 0);} +#define CANIF_get_idemask(ch,mob) ((CANIF_mob_get_ptr_data(ch,mob))->ide_mask_bit) +#define CANIF_set_rtrmask(ch,mob) {(CANIF_mob_get_ptr_data(ch,mob))->rtr_mask_bit = 1;} +#define CANIF_clr_rtrmask(ch,mob) {(CANIF_mob_get_ptr_data(ch,mob))->rtr_mask_bit = 0;} +#define CANIF_get_rtrmask(ch,mob) ((CANIF_mob_get_ptr_data(ch,mob))->rtr_mask_bit) +#define CANIF_set_ide(ch,mob) {(CANIF_mob_get_ptr_data(ch,mob))->ide_bit = 1;} +#define CANIF_clr_ide(ch,mob) {(CANIF_mob_get_ptr_data(ch,mob))->ide_bit = 0;} +#define CANIF_get_ide(ch,mob) ((CANIF_mob_get_ptr_data(ch,mob))->ide_bit) +#define CANIF_set_rtr(ch,mob) {(CANIF_mob_get_ptr_data(ch,mob))->rtr_bit = 1;} +#define CANIF_clr_rtr(ch,mob) {(CANIF_mob_get_ptr_data(ch,mob))->rtr_bit = 0;} +#define CANIF_get_rtr(ch,mob) ((CANIF_mob_get_ptr_data(ch,mob))->rtr_bit ) + +#define CANIF_set_ext_id(ch,mob,_id) {(CANIF_mob_get_ptr_data(ch,mob))->id = (1<id & 0x1FFFFFFF ) +#define CANIF_set_std_id(ch,mob,_id) {(CANIF_mob_get_ptr_data(ch,mob))->id = (_id);} +#define CANIF_get_std_id(ch,mob) ((CANIF_mob_get_ptr_data(ch,mob))->id & 0x000007FF ) + +#define CANIF_set_ext_idmask(ch,mob,mask) {(CANIF_mob_get_ptr_data(ch,mob))->id_mask = mask;} +#define CANIF_set_std_idmask(ch,mob,mask) {(CANIF_mob_get_ptr_data(ch,mob))->id_mask = mask;} + +#define CANIF_clr_mob(ch,mob) {(CANIF_mob_get_ptr_data(ch,mob))->id = 0; \ + (CANIF_mob_get_ptr_data(ch,mob))->id_mask = 0; \ + (CANIF_mob_get_ptr_data(ch,mob))->data.u64 = 0;} + +#define CANIF_set_data(ch,mob,_data) {(CANIF_mob_get_ptr_data(ch,mob))->data.u64 = _data;} + +/*! \brief Gets the mob status. + */ +extern uint8_t canif_get_mob_status(uint8_t ch, uint8_t mob); + +/*! \brief Config Baudrate with fixed baudrate + */ +extern uint8_t canif_fixed_baudrate(uint8_t ch); + +/*! \brief Clear all mob of a channel + */ +extern void canif_clear_all_mob(uint8_t ch, + uint8_t nb_mob); +//______________________________________________________________________________ + +#endif // _CANIF_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/flashc/flashc.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/flashc/flashc.c new file mode 100644 index 0000000..1a22bc9 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/flashc/flashc.c @@ -0,0 +1,1136 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FLASHC driver for AVR32 UC3. + * + * AVR32 Flash Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a FLASHC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include +#include +#include "compiler.h" +#include "flashc.h" + + +/*! \name FLASHC Writable Bit-Field Registers + */ +//! @{ + +typedef union +{ + unsigned long fcr; + avr32_flashc_fcr_t FCR; +} u_avr32_flashc_fcr_t; + +typedef union +{ + unsigned long fcmd; + avr32_flashc_fcmd_t FCMD; +} u_avr32_flashc_fcmd_t; + +//! @} + + +/*! \name Flash Properties + */ +//! @{ + + +unsigned int flashc_get_flash_size(void) +{ +#if (AVR32_FLASHC_H_VERSION >= 300) + static const unsigned int FLASH_SIZE[1 << AVR32_FLASHC_PR_FSZ_SIZE] = + { + 4 << 10, + 8 << 10, + 16 << 10, + 32 << 10, + 48 << 10, + 64 << 10, + 96 << 10, + 128 << 10, + 192 << 10, + 256 << 10, + 384 << 10, + 512 << 10, + 768 << 10, + 1024 << 10, + 2048 << 10 + }; + return FLASH_SIZE[(AVR32_FLASHC.pr & AVR32_FLASHC_PR_FSZ_MASK) >> AVR32_FLASHC_PR_FSZ_OFFSET]; +#else // in older flashc version, FSZ is located in FSR register + static const unsigned int FLASH_SIZE[1 << AVR32_FLASHC_FSR_FSZ_SIZE] = + { + 32 << 10, + 64 << 10, + 128 << 10, + 256 << 10, + 384 << 10, + 512 << 10, + 768 << 10, + 1024 << 10 + }; + return FLASH_SIZE[(AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FSZ_MASK) >> AVR32_FLASHC_FSR_FSZ_OFFSET]; +#endif +} + + +unsigned int flashc_get_page_count(void) +{ + return flashc_get_flash_size() / AVR32_FLASHC_PAGE_SIZE; +} + + +unsigned int flashc_get_page_count_per_region(void) +{ + return flashc_get_page_count() / AVR32_FLASHC_REGIONS; +} + + +unsigned int flashc_get_page_region(int page_number) +{ + return ((page_number >= 0) ? page_number : flashc_get_page_number()) / flashc_get_page_count_per_region(); +} + + +unsigned int flashc_get_region_first_page_number(unsigned int region) +{ + return region * flashc_get_page_count_per_region(); +} + + +//! @} + + +/*! \name FLASHC Control + */ +//! @{ + + +unsigned int flashc_get_wait_state(void) +{ + return (AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_FWS_MASK) >> AVR32_FLASHC_FCR_FWS_OFFSET; +} + + +void flashc_set_wait_state(unsigned int wait_state) +{ + u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr}; + u_avr32_flashc_fcr.FCR.fws = wait_state; + AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr; +} + + +void flashc_set_bus_freq(unsigned int cpu_f_hz) +{ + if(cpu_f_hz >= AVR32_FLASHC_FWS_0_MAX_FREQ) + { + // Set 1 WS. + flashc_set_wait_state(1); + } + else + { + // Set 0 WS. + flashc_set_wait_state(0); + } +} + +bool flashc_is_ready_int_enabled(void) +{ + return ((AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_FRDY_MASK) != 0); +} + + +void flashc_enable_ready_int(bool enable) +{ + u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr}; + u_avr32_flashc_fcr.FCR.frdy = (enable != false); + AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr; +} + + +bool flashc_is_lock_error_int_enabled(void) +{ + return ((AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_LOCKE_MASK) != 0); +} + + +void flashc_enable_lock_error_int(bool enable) +{ + u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr}; + u_avr32_flashc_fcr.FCR.locke = (enable != false); + AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr; +} + + +bool flashc_is_prog_error_int_enabled(void) +{ + return ((AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_PROGE_MASK) != 0); +} + + +void flashc_enable_prog_error_int(bool enable) +{ + u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr}; + u_avr32_flashc_fcr.FCR.proge = (enable != false); + AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr; +} + + +//! @} + + +/*! \name FLASHC Status + */ +//! @{ + + +bool flashc_is_ready(void) +{ + return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FRDY_MASK) != 0); +} + + +void flashc_default_wait_until_ready(void) +{ + while (!flashc_is_ready()); +} + + +void (*volatile flashc_wait_until_ready)(void) = flashc_default_wait_until_ready; + + +/*! \brief Gets the error status of the FLASHC. + * + * \return The error status of the FLASHC built up from + * \c AVR32_FLASHC_FSR_LOCKE_MASK and \c AVR32_FLASHC_FSR_PROGE_MASK. + * + * \warning This hardware error status is cleared by all functions reading the + * Flash Status Register (FSR). This function is therefore not part of + * the driver's API which instead presents \ref flashc_is_lock_error + * and \ref flashc_is_programming_error. + */ +static unsigned int flashc_get_error_status(void) +{ + return AVR32_FLASHC.fsr & (AVR32_FLASHC_FSR_LOCKE_MASK | + AVR32_FLASHC_FSR_PROGE_MASK); +} + + +//! Sticky error status of the FLASHC. +//! This variable is updated by functions that issue FLASHC commands. It +//! contains the cumulated FLASHC error status of all the FLASHC commands issued +//! by a function. +static unsigned int flashc_error_status = 0; + + +bool flashc_is_lock_error(void) +{ + return ((flashc_error_status & AVR32_FLASHC_FSR_LOCKE_MASK) != 0); +} + + +bool flashc_is_programming_error(void) +{ + return ((flashc_error_status & AVR32_FLASHC_FSR_PROGE_MASK) != 0); +} + + +//! @} + + +/*! \name FLASHC Command Control + */ +//! @{ + + +unsigned int flashc_get_command(void) +{ + return (AVR32_FLASHC.fcmd & AVR32_FLASHC_FCMD_CMD_MASK) >> AVR32_FLASHC_FCMD_CMD_OFFSET; +} + + +unsigned int flashc_get_page_number(void) +{ + return (AVR32_FLASHC.fcmd & AVR32_FLASHC_FCMD_PAGEN_MASK) >> AVR32_FLASHC_FCMD_PAGEN_OFFSET; +} + + +void flashc_issue_command(unsigned int command, int page_number) +{ + u_avr32_flashc_fcmd_t u_avr32_flashc_fcmd; + flashc_wait_until_ready(); + u_avr32_flashc_fcmd.fcmd = AVR32_FLASHC.fcmd; + u_avr32_flashc_fcmd.FCMD.cmd = command; + if (page_number >= 0) u_avr32_flashc_fcmd.FCMD.pagen = page_number; + u_avr32_flashc_fcmd.FCMD.key = AVR32_FLASHC_FCMD_KEY_KEY; + AVR32_FLASHC.fcmd = u_avr32_flashc_fcmd.fcmd; + flashc_error_status = flashc_get_error_status(); + flashc_wait_until_ready(); +} + + +//! @} + + +/*! \name FLASHC Global Commands + */ +//! @{ + + +void flashc_no_operation(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_NOP, -1); +} + + +void flashc_erase_all(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EA, -1); +} + + +//! @} + + +/*! \name FLASHC Protection Mechanisms + */ +//! @{ + + +bool flashc_is_security_bit_active(void) +{ + return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_SECURITY_MASK) != 0); +} + + +void flashc_activate_security_bit(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_SSB, -1); +} + + +unsigned int flashc_get_bootloader_protected_size(void) +{ + unsigned int bootprot = (1 << AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE) - 1 - + flashc_read_gp_fuse_bitfield(AVR32_FLASHC_FGPFRLO_BOOTPROT_OFFSET, + AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE); + return (bootprot) ? AVR32_FLASHC_PAGE_SIZE << bootprot : 0; +} + + +unsigned int flashc_set_bootloader_protected_size(unsigned int bootprot_size) +{ + flashc_set_gp_fuse_bitfield(AVR32_FLASHC_FGPFRLO_BOOTPROT_OFFSET, + AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE, + (1 << AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE) - 1 - + ((bootprot_size) ? + 32 - clz((((min(max(bootprot_size, AVR32_FLASHC_PAGE_SIZE << 1), + AVR32_FLASHC_PAGE_SIZE << + ((1 << AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE) - 1)) + + AVR32_FLASHC_PAGE_SIZE - 1) / + AVR32_FLASHC_PAGE_SIZE) << 1) - 1) - 1 : + 0)); + return flashc_get_bootloader_protected_size(); +} + + +bool flashc_is_external_privileged_fetch_locked(void) +{ + return (!flashc_read_gp_fuse_bit(AVR32_FLASHC_FGPFRLO_EPFL_OFFSET)); +} + + +void flashc_lock_external_privileged_fetch(bool lock) +{ + flashc_set_gp_fuse_bit(AVR32_FLASHC_FGPFRLO_EPFL_OFFSET, !lock); +} + + +bool flashc_is_page_region_locked(int page_number) +{ + return flashc_is_region_locked(flashc_get_page_region(page_number)); +} + + +bool flashc_is_region_locked(unsigned int region) +{ + return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_LOCK0_MASK << (region & (AVR32_FLASHC_REGIONS - 1))) != 0); +} + + +void flashc_lock_page_region(int page_number, bool lock) +{ + flashc_issue_command((lock) ? AVR32_FLASHC_FCMD_CMD_LP : AVR32_FLASHC_FCMD_CMD_UP, page_number); +} + + +void flashc_lock_region(unsigned int region, bool lock) +{ + flashc_lock_page_region(flashc_get_region_first_page_number(region), lock); +} + + +void flashc_lock_all_regions(bool lock) +{ + unsigned int error_status = 0; + unsigned int region = AVR32_FLASHC_REGIONS; + while (region) + { + flashc_lock_region(--region, lock); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; +} + + +//! @} + + +/*! \name Access to General-Purpose Fuses + */ +//! @{ + + +bool flashc_read_gp_fuse_bit(unsigned int gp_fuse_bit) +{ + return ((flashc_read_all_gp_fuses() & 1ULL << (gp_fuse_bit & 0x3F)) != 0); +} + + +U64 flashc_read_gp_fuse_bitfield(unsigned int pos, unsigned int width) +{ + return flashc_read_all_gp_fuses() >> (pos & 0x3F) & ((1ULL << min(width, 64)) - 1); +} + + +U8 flashc_read_gp_fuse_byte(unsigned int gp_fuse_byte) +{ + return flashc_read_all_gp_fuses() >> ((gp_fuse_byte & 0x07) << 3); +} + + +U64 flashc_read_all_gp_fuses(void) +{ + return AVR32_FLASHC.fgpfrlo | (U64)AVR32_FLASHC.fgpfrhi << 32; +} + + +bool flashc_erase_gp_fuse_bit(unsigned int gp_fuse_bit, bool check) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EGPB, gp_fuse_bit & 0x3F); + return (check) ? flashc_read_gp_fuse_bit(gp_fuse_bit) : true; +} + + +bool flashc_erase_gp_fuse_bitfield(unsigned int pos, unsigned int width, bool check) +{ + unsigned int error_status = 0; + unsigned int gp_fuse_bit; + pos &= 0x3F; + width = min(width, 64); + for (gp_fuse_bit = pos; gp_fuse_bit < pos + width; gp_fuse_bit++) + { + flashc_erase_gp_fuse_bit(gp_fuse_bit, false); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; + return (check) ? (flashc_read_gp_fuse_bitfield(pos, width) == (1ULL << width) - 1) : true; +} + + +bool flashc_erase_gp_fuse_byte(unsigned int gp_fuse_byte, bool check) +{ + unsigned int error_status; + unsigned int current_gp_fuse_byte; + U64 value = flashc_read_all_gp_fuses(); + flashc_erase_all_gp_fuses(false); + error_status = flashc_error_status; + for (current_gp_fuse_byte = 0; current_gp_fuse_byte < 8; current_gp_fuse_byte++, value >>= 8) + { + if (current_gp_fuse_byte != gp_fuse_byte) + { + flashc_write_gp_fuse_byte(current_gp_fuse_byte, value); + error_status |= flashc_error_status; + } + } + flashc_error_status = error_status; + return (check) ? (flashc_read_gp_fuse_byte(gp_fuse_byte) == 0xFF) : true; +} + + +bool flashc_erase_all_gp_fuses(bool check) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EAGPF, -1); + return (check) ? (flashc_read_all_gp_fuses() == 0xFFFFFFFFFFFFFFFFULL) : true; +} + + +void flashc_write_gp_fuse_bit(unsigned int gp_fuse_bit, bool value) +{ + if (!value) + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_WGPB, gp_fuse_bit & 0x3F); +} + + +void flashc_write_gp_fuse_bitfield(unsigned int pos, unsigned int width, U64 value) +{ + unsigned int error_status = 0; + unsigned int gp_fuse_bit; + pos &= 0x3F; + width = min(width, 64); + for (gp_fuse_bit = pos; gp_fuse_bit < pos + width; gp_fuse_bit++, value >>= 1) + { + flashc_write_gp_fuse_bit(gp_fuse_bit, value & 0x01); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; +} + + +void flashc_write_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_PGPFB, (gp_fuse_byte & 0x07) | value << 3); +} + + +void flashc_write_all_gp_fuses(U64 value) +{ + unsigned int error_status = 0; + unsigned int gp_fuse_byte; + for (gp_fuse_byte = 0; gp_fuse_byte < 8; gp_fuse_byte++, value >>= 8) + { + flashc_write_gp_fuse_byte(gp_fuse_byte, value); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; +} + + +void flashc_set_gp_fuse_bit(unsigned int gp_fuse_bit, bool value) +{ + if (value) + flashc_erase_gp_fuse_bit(gp_fuse_bit, false); + else + flashc_write_gp_fuse_bit(gp_fuse_bit, false); +} + + +void flashc_set_gp_fuse_bitfield(unsigned int pos, unsigned int width, U64 value) +{ + unsigned int error_status = 0; + unsigned int gp_fuse_bit; + pos &= 0x3F; + width = min(width, 64); + for (gp_fuse_bit = pos; gp_fuse_bit < pos + width; gp_fuse_bit++, value >>= 1) + { + flashc_set_gp_fuse_bit(gp_fuse_bit, value & 0x01); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; +} + + +void flashc_set_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value) +{ + unsigned int error_status; + switch (value) + { + case 0xFF: + flashc_erase_gp_fuse_byte(gp_fuse_byte, false); + break; + case 0x00: + flashc_write_gp_fuse_byte(gp_fuse_byte, 0x00); + break; + default: + flashc_erase_gp_fuse_byte(gp_fuse_byte, false); + error_status = flashc_error_status; + flashc_write_gp_fuse_byte(gp_fuse_byte, value); + flashc_error_status |= error_status; + } +} + + +void flashc_set_all_gp_fuses(U64 value) +{ + unsigned int error_status; + switch (value) + { + case 0xFFFFFFFFFFFFFFFFULL: + flashc_erase_all_gp_fuses(false); + break; + case 0x0000000000000000ULL: + flashc_write_all_gp_fuses(0x0000000000000000ULL); + break; + default: + flashc_erase_all_gp_fuses(false); + error_status = flashc_error_status; + flashc_write_all_gp_fuses(value); + flashc_error_status |= error_status; + } +} + + +//! @} + + +/*! \name Access to Flash Pages + */ +//! @{ + + +void flashc_clear_page_buffer(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_CPB, -1); +} + + +bool flashc_is_page_erased(void) +{ + return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_QPRR_MASK) != 0); +} + + +bool flashc_quick_page_read(int page_number) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_QPR, page_number); + return flashc_is_page_erased(); +} + + +bool flashc_erase_page(int page_number, bool check) +{ + bool page_erased = true; + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EP, page_number); + if (check) + { + unsigned int error_status = flashc_error_status; + page_erased = flashc_quick_page_read(-1); + flashc_error_status |= error_status; + } + return page_erased; +} + + +bool flashc_erase_all_pages(bool check) +{ + bool all_pages_erased = true; + unsigned int error_status = 0; + unsigned int page_number = flashc_get_page_count(); + while (page_number) + { + all_pages_erased &= flashc_erase_page(--page_number, check); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; + return all_pages_erased; +} + + +void flashc_write_page(int page_number) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_WP, page_number); +} + + +bool flashc_quick_user_page_read(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_QPRUP, -1); + return flashc_is_page_erased(); +} + + +bool flashc_erase_user_page(bool check) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EUP, -1); + return (check) ? flashc_quick_user_page_read() : true; +} + + +void flashc_write_user_page(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_WUP, -1); +} + + +volatile void *flashc_memset8(volatile void *dst, U8 src, size_t nbytes, bool erase) +{ + return flashc_memset16(dst, src | (U16)src << 8, nbytes, erase); +} + + +volatile void *flashc_memset16(volatile void *dst, U16 src, size_t nbytes, bool erase) +{ + return flashc_memset32(dst, src | (U32)src << 16, nbytes, erase); +} + + +volatile void *flashc_memset32(volatile void *dst, U32 src, size_t nbytes, bool erase) +{ + return flashc_memset64(dst, src | (U64)src << 32, nbytes, erase); +} + + +volatile void *flashc_memset64(volatile void *dst, U64 src, size_t nbytes, bool erase) +{ + // Use aggregated pointers to have several alignments available for a same address. + UnionCVPtr flash_array_end; + UnionVPtr dest; + Union64 source = {0}; + StructCVPtr dest_end; + UnionCVPtr flash_page_source_end; + bool incomplete_flash_page_end; + Union64 flash_dword; + UnionVPtr tmp; + unsigned int error_status = 0; + unsigned int i; + + // Reformat arguments. + flash_array_end.u8ptr = AVR32_FLASH + flashc_get_flash_size(); + dest.u8ptr = dst; + for (i = (Get_align((U32)dest.u8ptr, sizeof(U64)) - 1) & (sizeof(U64) - 1); + src; i = (i - 1) & (sizeof(U64) - 1)) + { + source.u8[i] = src; + src >>= 8; + } + dest_end.u8ptr = dest.u8ptr + nbytes; + + // If destination is outside flash, go to next flash page if any. + if (dest.u8ptr < AVR32_FLASH) + { + dest.u8ptr = AVR32_FLASH; + } + else if (flash_array_end.u8ptr <= dest.u8ptr && dest.u8ptr < AVR32_FLASHC_USER_PAGE) + { + dest.u8ptr = AVR32_FLASHC_USER_PAGE; + } + + // If end of destination is outside flash, move it to the end of the previous flash page if any. + if (dest_end.u8ptr > AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE) + { + dest_end.u8ptr = AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE; + } + else if (AVR32_FLASHC_USER_PAGE >= dest_end.u8ptr && dest_end.u8ptr > flash_array_end.u8ptr) + { + dest_end.u8ptr = flash_array_end.u8ptr; + } + + // Align each end of destination pointer with its natural boundary. + dest_end.u16ptr = (U16 *)Align_down((U32)dest_end.u8ptr, sizeof(U16)); + dest_end.u32ptr = (U32 *)Align_down((U32)dest_end.u16ptr, sizeof(U32)); + dest_end.u64ptr = (U64 *)Align_down((U32)dest_end.u32ptr, sizeof(U64)); + + // While end of destination is not reached... + while (dest.u8ptr < dest_end.u8ptr) + { + // Clear the page buffer in order to prepare data for a flash page write. + flashc_clear_page_buffer(); + error_status |= flashc_error_status; + + // Determine where the source data will end in the current flash page. + flash_page_source_end.u64ptr = + (U64 *)min((U32)dest_end.u64ptr, + Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) + AVR32_FLASHC_PAGE_SIZE); + + // Determine if the current destination page has an incomplete end. + incomplete_flash_page_end = (Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) >= + Align_down((U32)dest_end.u8ptr, AVR32_FLASHC_PAGE_SIZE)); + + // Use a flash double-word buffer to manage unaligned accesses. + flash_dword.u64 = source.u64; + + // If destination does not point to the beginning of the current flash page... + if (!Test_align((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE)) + { + // Fill the beginning of the page buffer with the current flash page data. + // This is required by the hardware, even if page erase is not requested, + // in order to be able to write successfully to erased parts of flash + // pages that have already been written to. + for (tmp.u8ptr = (U8 *)Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE); + tmp.u64ptr < (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64)); + tmp.u64ptr++) + *tmp.u64ptr = *tmp.u64ptr; + + // If destination is not 64-bit aligned... + if (!Test_align((U32)dest.u8ptr, sizeof(U64))) + { + // Fill the beginning of the flash double-word buffer with the current + // flash page data. + // This is required by the hardware, even if page erase is not + // requested, in order to be able to write successfully to erased parts + // of flash pages that have already been written to. + for (i = 0; i < Get_align((U32)dest.u8ptr, sizeof(U64)); i++) + flash_dword.u8[i] = *tmp.u8ptr++; + + // Align the destination pointer with its 64-bit boundary. + dest.u64ptr = (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64)); + + // If the current destination double-word is not the last one... + if (dest.u64ptr < dest_end.u64ptr) + { + // Write the flash double-word buffer to the page buffer and reinitialize it. + *dest.u64ptr++ = flash_dword.u64; + flash_dword.u64 = source.u64; + } + } + } + + // Write the source data to the page buffer with 64-bit alignment. + for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--) + *dest.u64ptr++ = source.u64; + + // If the current destination page has an incomplete end... + if (incomplete_flash_page_end) + { + // This is required by the hardware, even if page erase is not requested, + // in order to be able to write successfully to erased parts of flash + // pages that have already been written to. + { + tmp.u8ptr = (volatile U8 *)dest_end.u8ptr; + + // If end of destination is not 64-bit aligned... + if (!Test_align((U32)dest_end.u8ptr, sizeof(U64))) + { + // Fill the end of the flash double-word buffer with the current flash page data. + for (i = Get_align((U32)dest_end.u8ptr, sizeof(U64)); i < sizeof(U64); i++) + flash_dword.u8[i] = *tmp.u8ptr++; + + // Write the flash double-word buffer to the page buffer. + *dest.u64ptr++ = flash_dword.u64; + } + + // Fill the end of the page buffer with the current flash page data. + for (; !Test_align((U32)tmp.u64ptr, AVR32_FLASHC_PAGE_SIZE); tmp.u64ptr++) + *tmp.u64ptr = *tmp.u64ptr; + } + } + + // If the current flash page is in the flash array... + if (dest.u8ptr <= AVR32_FLASHC_USER_PAGE) + { + // Erase the current page if requested and write it from the page buffer. + if (erase) + { + flashc_erase_page(-1, false); + error_status |= flashc_error_status; + } + flashc_write_page(-1); + error_status |= flashc_error_status; + + // If the end of the flash array is reached, go to the User page. + if (dest.u8ptr >= flash_array_end.u8ptr) + dest.u8ptr = AVR32_FLASHC_USER_PAGE; + } + // If the current flash page is the User page... + else + { + // Erase the User page if requested and write it from the page buffer. + if (erase) + { + flashc_erase_user_page(false); + error_status |= flashc_error_status; + } + flashc_write_user_page(); + error_status |= flashc_error_status; + } + } + + // Update the FLASHC error status. + flashc_error_status = error_status; + + // Return the initial destination pointer as the standard memset function does. + return dst; +} + + +volatile void *flashc_memcpy(volatile void *dst, const void *src, size_t nbytes, bool erase) +{ + // Use aggregated pointers to have several alignments available for a same address. + UnionCVPtr flash_array_end; + UnionVPtr dest; + UnionCPtr source; + StructCVPtr dest_end; + UnionCVPtr flash_page_source_end; + bool incomplete_flash_page_end; + Union64 flash_dword; + bool flash_dword_pending = false; + UnionVPtr tmp; + unsigned int error_status = 0; + unsigned int i, j; + + // Reformat arguments. + flash_array_end.u8ptr = AVR32_FLASH + flashc_get_flash_size(); + dest.u8ptr = dst; + source.u8ptr = src; + dest_end.u8ptr = dest.u8ptr + nbytes; + + // If destination is outside flash, go to next flash page if any. + if (dest.u8ptr < AVR32_FLASH) + { + source.u8ptr += AVR32_FLASH - dest.u8ptr; + dest.u8ptr = AVR32_FLASH; + } + else if (flash_array_end.u8ptr <= dest.u8ptr && dest.u8ptr < AVR32_FLASHC_USER_PAGE) + { + source.u8ptr += AVR32_FLASHC_USER_PAGE - dest.u8ptr; + dest.u8ptr = AVR32_FLASHC_USER_PAGE; + } + + // If end of destination is outside flash, move it to the end of the previous flash page if any. + if (dest_end.u8ptr > AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE) + { + dest_end.u8ptr = AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE; + } + else if (AVR32_FLASHC_USER_PAGE >= dest_end.u8ptr && dest_end.u8ptr > flash_array_end.u8ptr) + { + dest_end.u8ptr = flash_array_end.u8ptr; + } + + // Align each end of destination pointer with its natural boundary. + dest_end.u16ptr = (U16 *)Align_down((U32)dest_end.u8ptr, sizeof(U16)); + dest_end.u32ptr = (U32 *)Align_down((U32)dest_end.u16ptr, sizeof(U32)); + dest_end.u64ptr = (U64 *)Align_down((U32)dest_end.u32ptr, sizeof(U64)); + + // While end of destination is not reached... + while (dest.u8ptr < dest_end.u8ptr) + { + // Clear the page buffer in order to prepare data for a flash page write. + flashc_clear_page_buffer(); + error_status |= flashc_error_status; + + // Determine where the source data will end in the current flash page. + flash_page_source_end.u64ptr = + (U64 *)min((U32)dest_end.u64ptr, + Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) + AVR32_FLASHC_PAGE_SIZE); + + // Determine if the current destination page has an incomplete end. + incomplete_flash_page_end = (Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) >= + Align_down((U32)dest_end.u8ptr, AVR32_FLASHC_PAGE_SIZE)); + + // If destination does not point to the beginning of the current flash page... + if (!Test_align((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE)) + { + // Fill the beginning of the page buffer with the current flash page data. + // This is required by the hardware, even if page erase is not requested, + // in order to be able to write successfully to erased parts of flash + // pages that have already been written to. + for (tmp.u8ptr = (U8 *)Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE); + tmp.u64ptr < (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64)); + tmp.u64ptr++) + *tmp.u64ptr = *tmp.u64ptr; + + // If destination is not 64-bit aligned... + if (!Test_align((U32)dest.u8ptr, sizeof(U64))) + { + // Fill the beginning of the flash double-word buffer with the current + // flash page data. + // This is required by the hardware, even if page erase is not + // requested, in order to be able to write successfully to erased parts + // of flash pages that have already been written to. + for (i = 0; i < Get_align((U32)dest.u8ptr, sizeof(U64)); i++) + flash_dword.u8[i] = *tmp.u8ptr++; + + // Fill the end of the flash double-word buffer with the source data. + for (; i < sizeof(U64); i++) + flash_dword.u8[i] = *source.u8ptr++; + + // Align the destination pointer with its 64-bit boundary. + dest.u64ptr = (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64)); + + // If the current destination double-word is not the last one... + if (dest.u64ptr < dest_end.u64ptr) + { + // Write the flash double-word buffer to the page buffer. + *dest.u64ptr++ = flash_dword.u64; + } + // If the current destination double-word is the last one, the flash + // double-word buffer must be kept for later. + else flash_dword_pending = true; + } + } + + // Read the source data with the maximal possible alignment and write it to + // the page buffer with 64-bit alignment. + switch (Get_align((U32)source.u8ptr, sizeof(U32))) + { + case 0: + for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--) + *dest.u64ptr++ = *source.u64ptr++; + break; + + case sizeof(U16): + for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--) + { + for (j = 0; j < sizeof(U64) / sizeof(U16); j++) flash_dword.u16[j] = *source.u16ptr++; + *dest.u64ptr++ = flash_dword.u64; + } + break; + + default: + for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--) + { + for (j = 0; j < sizeof(U64); j++) flash_dword.u8[j] = *source.u8ptr++; + *dest.u64ptr++ = flash_dword.u64; + } + } + + // If the current destination page has an incomplete end... + if (incomplete_flash_page_end) + { + // If the flash double-word buffer is in use, do not initialize it. + if (flash_dword_pending) i = Get_align((U32)dest_end.u8ptr, sizeof(U64)); + // If the flash double-word buffer is free... + else + { + // Fill the beginning of the flash double-word buffer with the source data. + for (i = 0; i < Get_align((U32)dest_end.u8ptr, sizeof(U64)); i++) + flash_dword.u8[i] = *source.u8ptr++; + } + + // This is required by the hardware, even if page erase is not requested, + // in order to be able to write successfully to erased parts of flash + // pages that have already been written to. + { + tmp.u8ptr = (volatile U8 *)dest_end.u8ptr; + + // If end of destination is not 64-bit aligned... + if (!Test_align((U32)dest_end.u8ptr, sizeof(U64))) + { + // Fill the end of the flash double-word buffer with the current flash page data. + for (; i < sizeof(U64); i++) + flash_dword.u8[i] = *tmp.u8ptr++; + + // Write the flash double-word buffer to the page buffer. + *dest.u64ptr++ = flash_dword.u64; + } + + // Fill the end of the page buffer with the current flash page data. + for (; !Test_align((U32)tmp.u64ptr, AVR32_FLASHC_PAGE_SIZE); tmp.u64ptr++) + *tmp.u64ptr = *tmp.u64ptr; + } + } + + // If the current flash page is in the flash array... + if (dest.u8ptr <= AVR32_FLASHC_USER_PAGE) + { + // Erase the current page if requested and write it from the page buffer. + if (erase) + { + flashc_erase_page(-1, false); + error_status |= flashc_error_status; + } + flashc_write_page(-1); + error_status |= flashc_error_status; + + // If the end of the flash array is reached, go to the User page. + if (dest.u8ptr >= flash_array_end.u8ptr) + { + source.u8ptr += AVR32_FLASHC_USER_PAGE - dest.u8ptr; + dest.u8ptr = AVR32_FLASHC_USER_PAGE; + } + } + // If the current flash page is the User page... + else + { + // Erase the User page if requested and write it from the page buffer. + if (erase) + { + flashc_erase_user_page(false); + error_status |= flashc_error_status; + } + flashc_write_user_page(); + error_status |= flashc_error_status; + } + } + + // Update the FLASHC error status. + flashc_error_status = error_status; + + // Return the initial destination pointer as the standard memcpy function does. + return dst; +} + + +#if UC3C +void flashc_set_flash_waitstate_and_readmode(unsigned long cpu_f_hz) +{ + //! Device-specific data + #undef AVR32_FLASHC_FWS_0_MAX_FREQ + #undef AVR32_FLASHC_FWS_1_MAX_FREQ + #undef AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ + #undef AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ + #define AVR32_FLASHC_FWS_0_MAX_FREQ 33000000 + #define AVR32_FLASHC_FWS_1_MAX_FREQ 66000000 + #define AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ 33000000 + #define AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ 72000000 + // These defines are missing from or wrong in the toolchain header files uc3cxxx.h + // Put a Bugzilla + + if(cpu_f_hz > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ) // > 33MHz + { + // Set a wait-state + flashc_set_wait_state(1); + if(cpu_f_hz <= AVR32_FLASHC_FWS_1_MAX_FREQ) // <= 66MHz and >33Mhz + { + // Disable the high-speed read mode. + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1); + } + else // > 66Mhz + { + // Enable the high-speed read mode. + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1); + } + } + else // <= 33 MHz + { + // Disable wait-state + flashc_set_wait_state(0); + + // Disable the high-speed read mode. + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1); + + } +} +#endif // UC3C device-specific implementation + +//! @} diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/flashc/flashc.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/flashc/flashc.h new file mode 100644 index 0000000..a0da1ed --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/flashc/flashc.h @@ -0,0 +1,1018 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FLASHC driver for AVR32 UC3. + * + * AVR32 Flash Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a FLASHC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _FLASHC_H_ +#define _FLASHC_H_ + +#include +#include +#include "compiler.h" + +//! Number of flash regions defined by the FLASHC. +#define AVR32_FLASHC_REGIONS (AVR32_FLASHC_FLASH_SIZE /\ + (AVR32_FLASHC_PAGES_PR_REGION * AVR32_FLASHC_PAGE_SIZE)) + + +/*! \name Flash Properties + */ +//! @{ + +/*! \brief Gets the size of the whole flash array. + * + * \return The size of the whole flash array in bytes. + */ +extern unsigned int flashc_get_flash_size(void); + +/*! \brief Gets the total number of pages in the flash array. + * + * \return The total number of pages in the flash array. + */ +extern unsigned int flashc_get_page_count(void); + +/*! \brief Gets the number of pages in each flash region. + * + * \return The number of pages in each flash region. + */ +extern unsigned int flashc_get_page_count_per_region(void); + +/*! \brief Gets the region number of a page. + * + * \param page_number The page number: + * \arg \c 0 to (flashc_get_page_count() - 1): a page number within + * the flash array; + * \arg < 0: the current page number. + * + * \return The region number of the specified page. + */ +extern unsigned int flashc_get_page_region(int page_number); + +/*! \brief Gets the number of the first page of a region. + * + * \param region The region number: \c 0 to (AVR32_FLASHC_REGIONS - 1). + * + * \return The number of the first page of the specified region. + */ +extern unsigned int flashc_get_region_first_page_number(unsigned int region); + +//! @} + + +/*! \name FLASHC Control + */ +//! @{ + +/*! \brief Gets the number of wait states of flash read accesses. + * + * \return The number of wait states of flash read accesses. + */ +extern unsigned int flashc_get_wait_state(void); + +/*! \brief Sets the number of wait states of flash read accesses. + * + * \param wait_state The number of wait states of flash read accesses: \c 0 to + * \c 1. + */ +extern void flashc_set_wait_state(unsigned int wait_state); + +/*! \brief Depending on the CPU frequency, set the wait states of flash read + * accesses. + * + * \param cpu_f_hz The CPU frequency + */ +extern void flashc_set_bus_freq(unsigned int cpu_f_hz); +/*! \brief Alias on the flashc_set_bus_freq() function. + * + * \param cpu_f_hz The CPU frequency + */ +#define flash_set_bus_freq(cpu_f_hz) flashc_set_bus_freq(cpu_f_hz) + +/*! \brief Tells whether the Flash Ready interrupt is enabled. + * + * \return Whether the Flash Ready interrupt is enabled. + */ +extern bool flashc_is_ready_int_enabled(void); + +/*! \brief Enables or disables the Flash Ready interrupt. + * + * \param enable Whether to enable the Flash Ready interrupt: \c true or + * \c false. + */ +extern void flashc_enable_ready_int(bool enable); + +/*! \brief Tells whether the Lock Error interrupt is enabled. + * + * \return Whether the Lock Error interrupt is enabled. + */ +extern bool flashc_is_lock_error_int_enabled(void); + +/*! \brief Enables or disables the Lock Error interrupt. + * + * \param enable Whether to enable the Lock Error interrupt: \c true or + * \c false. + */ +extern void flashc_enable_lock_error_int(bool enable); + +/*! \brief Tells whether the Programming Error interrupt is enabled. + * + * \return Whether the Programming Error interrupt is enabled. + */ +extern bool flashc_is_prog_error_int_enabled(void); + +/*! \brief Enables or disables the Programming Error interrupt. + * + * \param enable Whether to enable the Programming Error interrupt: \c true or + * \c false. + */ +extern void flashc_enable_prog_error_int(bool enable); + +//! @} + + +/*! \name FLASHC Status + */ +//! @{ + +/*! \brief Tells whether the FLASHC is ready to run a new command. + * + * \return Whether the FLASHC is ready to run a new command. + */ +extern bool flashc_is_ready(void); + +/*! \brief Waits actively until the FLASHC is ready to run a new command. + * + * This is the default function assigned to \ref flashc_wait_until_ready. + */ +extern void flashc_default_wait_until_ready(void); + +//! Pointer to the function used by the driver when it needs to wait until the +//! FLASHC is ready to run a new command. +//! The default function is \ref flashc_default_wait_until_ready. +//! The user may change this pointer to use another implementation. +extern void (*volatile flashc_wait_until_ready)(void); + +/*! \brief Tells whether a Lock Error has occurred during the last function + * called that issued one or more FLASHC commands. + * + * \return Whether a Lock Error has occurred during the last function called + * that issued one or more FLASHC commands. + */ +extern bool flashc_is_lock_error(void); + +/*! \brief Tells whether a Programming Error has occurred during the last + * function called that issued one or more FLASHC commands. + * + * \return Whether a Programming Error has occurred during the last function + * called that issued one or more FLASHC commands. + */ +extern bool flashc_is_programming_error(void); + +//! @} + + +/*! \name FLASHC Command Control + */ +//! @{ + +/*! \brief Gets the last issued FLASHC command. + * + * \return The last issued FLASHC command. + */ +extern unsigned int flashc_get_command(void); + +/*! \brief Gets the current FLASHC page number. + * + * \return The current FLASHC page number. + */ +extern unsigned int flashc_get_page_number(void); + +/*! \brief Issues a FLASHC command. + * + * \param command The command: \c AVR32_FLASHC_FCMD_CMD_x. + * \param page_number The page number to apply the command to: + * \arg \c 0 to (flashc_get_page_count() - 1): a page number within + * the flash array; + * \arg < 0: use this to apply the command to the current page number + * or if the command does not apply to any page number; + * \arg this argument may have other meanings according to the command. See + * the FLASHC chapter of the MCU datasheet. + * + * \warning A Lock Error is issued if the command violates the protection + * mechanism. + * + * \warning A Programming Error is issued if the command is invalid. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_issue_command(unsigned int command, int page_number); + +//! @} + + +/*! \name FLASHC Global Commands + */ +//! @{ + +/*! \brief Issues a No Operation command to the FLASHC. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_no_operation(void); + +/*! \brief Issues an Erase All command to the FLASHC. + * + * This command erases all bits in the flash array, the general-purpose fuse + * bits and the Security bit. The User page is not erased. + * + * This command also ensures that all volatile memories, such as register file + * and RAMs, are erased before the Security bit is erased, i.e. deactivated. + * + * \warning A Lock Error is issued if at least one region is locked or the + * bootloader protection is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern void flashc_erase_all(void); + +//! @} + + +/*! \name FLASHC Protection Mechanisms + */ +//! @{ + +/*! \brief Tells whether the Security bit is active. + * + * \return Whether the Security bit is active. + */ +extern bool flashc_is_security_bit_active(void); + +/*! \brief Activates the Security bit. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_activate_security_bit(void); + +/*! \brief Gets the bootloader protected size. + * + * \return The bootloader protected size in bytes. + */ +extern unsigned int flashc_get_bootloader_protected_size(void); + +/*! \brief Sets the bootloader protected size. + * + * \param bootprot_size The wanted bootloader protected size in bytes. If this + * size is not supported, the actual size will be the + * nearest greater available size or the maximal possible + * size if the requested size is too large. + * + * \return The actual bootloader protected size in bytes. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern unsigned int flashc_set_bootloader_protected_size(unsigned int bootprot_size); + +/*! \brief Tells whether external privileged fetch is locked. + * + * \return Whether external privileged fetch is locked. + */ +extern bool flashc_is_external_privileged_fetch_locked(void); + +/*! \brief Locks or unlocks external privileged fetch. + * + * \param lock Whether to lock external privileged fetch: \c true or \c false. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_lock_external_privileged_fetch(bool lock); + +/*! \brief Tells whether the region of a page is locked. + * + * \param page_number The page number: + * \arg \c 0 to (flashc_get_page_count() - 1): a page number within + * the flash array; + * \arg < 0: the current page number. + * + * \return Whether the region of the specified page is locked. + */ +extern bool flashc_is_page_region_locked(int page_number); + +/*! \brief Tells whether a region is locked. + * + * \param region The region number: \c 0 to (AVR32_FLASHC_REGIONS - 1). + * + * \return Whether the specified region is locked. + */ +extern bool flashc_is_region_locked(unsigned int region); + +/*! \brief Locks or unlocks the region of a page. + * + * \param page_number The page number: + * \arg \c 0 to (flashc_get_page_count() - 1): a page number within + * the flash array; + * \arg < 0: the current page number. + * \param lock Whether to lock the region of the specified page: \c true or + * \c false. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_lock_page_region(int page_number, bool lock); + +/*! \brief Locks or unlocks a region. + * + * \param region The region number: \c 0 to (AVR32_FLASHC_REGIONS - 1). + * \param lock Whether to lock the specified region: \c true or \c false. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_lock_region(unsigned int region, bool lock); + +/*! \brief Locks or unlocks all regions. + * + * \param lock Whether to lock the regions: \c true or \c false. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_lock_all_regions(bool lock); + +//! @} + + +/*! \name Access to General-Purpose Fuses + */ +//! @{ + +/*! \brief Reads a general-purpose fuse bit. + * + * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 63. + * + * \return The value of the specified general-purpose fuse bit. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern bool flashc_read_gp_fuse_bit(unsigned int gp_fuse_bit); + +/*! \brief Reads a general-purpose fuse bit-field. + * + * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to + * \c 63. + * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to + * \c 64. + * + * \return The value of the specified general-purpose fuse bit-field. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern U64 flashc_read_gp_fuse_bitfield(unsigned int pos, unsigned int width); + +/*! \brief Reads a general-purpose fuse byte. + * + * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 7. + * + * \return The value of the specified general-purpose fuse byte. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern U8 flashc_read_gp_fuse_byte(unsigned int gp_fuse_byte); + +/*! \brief Reads all general-purpose fuses. + * + * \return The value of all general-purpose fuses as a word. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern U64 flashc_read_all_gp_fuses(void); + +/*! \brief Erases a general-purpose fuse bit. + * + * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 63. + * \param check Whether to check erase: \c true or \c false. + * + * \return Whether the erase succeeded or always \c true if erase check was not + * requested. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern bool flashc_erase_gp_fuse_bit(unsigned int gp_fuse_bit, bool check); + +/*! \brief Erases a general-purpose fuse bit-field. + * + * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to + * \c 63. + * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to + * \c 64. + * \param check Whether to check erase: \c true or \c false. + * + * \return Whether the erase succeeded or always \c true if erase check was not + * requested. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern bool flashc_erase_gp_fuse_bitfield(unsigned int pos, unsigned int width, bool check); + +/*! \brief Erases a general-purpose fuse byte. + * + * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 7. + * \param check Whether to check erase: \c true or \c false. + * + * \return Whether the erase succeeded or always \c true if erase check was not + * requested. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern bool flashc_erase_gp_fuse_byte(unsigned int gp_fuse_byte, bool check); + +/*! \brief Erases all general-purpose fuses. + * + * \param check Whether to check erase: \c true or \c false. + * + * \return Whether the erase succeeded or always \c true if erase check was not + * requested. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern bool flashc_erase_all_gp_fuses(bool check); + +/*! \brief Writes a general-purpose fuse bit. + * + * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 63. + * \param value The value of the specified general-purpose fuse bit. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits; in other words, an erase operation + * must first be done if some bits need to be set to 1. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_write_gp_fuse_bit(unsigned int gp_fuse_bit, bool value); + +/*! \brief Writes a general-purpose fuse bit-field. + * + * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to + * \c 63. + * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to + * \c 64. + * \param value The value of the specified general-purpose fuse bit-field. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits; in other words, an erase operation + * must first be done if some bits need to be set to 1. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_write_gp_fuse_bitfield(unsigned int pos, unsigned int width, U64 value); + +/*! \brief Writes a general-purpose fuse byte. + * + * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 7. + * \param value The value of the specified general-purpose fuse byte. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits; in other words, an erase operation + * must first be done if some bits need to be set to 1. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_write_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value); + +/*! \brief Writes all general-purpose fuses. + * + * \param value The value of all general-purpose fuses as a word. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits; in other words, an erase operation + * must first be done if some bits need to be set to 1. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_write_all_gp_fuses(U64 value); + +/*! \brief Sets a general-purpose fuse bit with the appropriate erase and write + * operations. + * + * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 63. + * \param value The value of the specified general-purpose fuse bit. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_set_gp_fuse_bit(unsigned int gp_fuse_bit, bool value); + +/*! \brief Sets a general-purpose fuse bit-field with the appropriate erase and + * write operations. + * + * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to + * \c 63. + * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to + * \c 64. + * \param value The value of the specified general-purpose fuse bit-field. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_set_gp_fuse_bitfield(unsigned int pos, unsigned int width, U64 value); + +/*! \brief Sets a general-purpose fuse byte with the appropriate erase and write + * operations. + * + * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 7. + * \param value The value of the specified general-purpose fuse byte. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_set_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value); + +/*! \brief Sets all general-purpose fuses with the appropriate erase and write + * operations. + * + * \param value The value of all general-purpose fuses as a word. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note The actual number of general-purpose fuse bits implemented by hardware + * is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are + * fixed at 1 by hardware. + */ +extern void flashc_set_all_gp_fuses(U64 value); + +//! @} + + +/*! \name Access to Flash Pages + */ +//! @{ + +/*! \brief Clears the page buffer. + * + * This command resets all bits in the page buffer to one. Write accesses to the + * page buffer can only change page buffer bits from one to zero. + * + * \warning The page buffer is not automatically reset after a page write. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_clear_page_buffer(void); + +/*! \brief Tells whether the page to which the last Quick Page Read or Quick + * Page Read User Page command was applied was erased. + * + * \return Whether the page to which the last Quick Page Read or Quick Page Read + * User Page command was applied was erased. + */ +extern bool flashc_is_page_erased(void); + +/*! \brief Applies the Quick Page Read command to a page. + * + * \param page_number The page number: + * \arg \c 0 to (flashc_get_page_count() - 1): a page number within + * the flash array; + * \arg < 0: the current page number. + * + * \return Whether the specified page is erased. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern bool flashc_quick_page_read(int page_number); + +/*! \brief Erases a page. + * + * \param page_number The page number: + * \arg \c 0 to (flashc_get_page_count() - 1): a page number within + * the flash array; + * \arg < 0: the current page number. + * \param check Whether to check erase: \c true or \c false. + * + * \return Whether the erase succeeded or always \c true if erase check was not + * requested. + * + * \warning A Lock Error is issued if the command is applied to a page belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern bool flashc_erase_page(int page_number, bool check); + +/*! \brief Erases all pages within the flash array. + * + * \param check Whether to check erase: \c true or \c false. + * + * \return Whether the erase succeeded or always \c true if erase check was not + * requested. + * + * \warning A Lock Error is issued if at least one region is locked or the + * bootloader protection is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern bool flashc_erase_all_pages(bool check); + +/*! \brief Writes a page from the page buffer. + * + * \param page_number The page number: + * \arg \c 0 to (flashc_get_page_count() - 1): a page number within + * the flash array; + * \arg < 0: the current page number. + * + * \warning A Lock Error is issued if the command is applied to a page belonging + * to a locked region or to the bootloader protected area. + * + * \warning The page buffer is not automatically reset after a page write. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits; in other words, an erase operation + * must first be done if some bits need to be set to 1. + */ +extern void flashc_write_page(int page_number); + +/*! \brief Issues a Quick Page Read User Page command to the FLASHC. + * + * \return Whether the User page is erased. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern bool flashc_quick_user_page_read(void); + +/*! \brief Erases the User page. + * + * \param check Whether to check erase: \c true or \c false. + * + * \return Whether the erase succeeded or always \c true if erase check was not + * requested. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern bool flashc_erase_user_page(bool check); + +/*! \brief Writes the User page from the page buffer. + * + * \warning The page buffer is not automatically reset after a page write. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits; in other words, an erase operation + * must first be done if some bits need to be set to 1. + */ +extern void flashc_write_user_page(void); + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the repeated \a src source byte. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Source byte. + * \param nbytes Number of bytes to set. + * \param erase Whether to erase before writing: \c true or \c false. + * + * \return The value of \a dst. + * + * \warning This function may be called with \a erase set to \c false only if + * the destination consists only of erased words, i.e. this function + * can not be used to write only one bit of a previously written word. + * E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the + * resulting value in flash may be different from \c 0x00000000. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern volatile void *flashc_memset8(volatile void *dst, U8 src, size_t nbytes, bool erase); + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the repeated \a src big-endian source half-word. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Source half-word. + * \param nbytes Number of bytes to set. + * \param erase Whether to erase before writing: \c true or \c false. + * + * \return The value of \a dst. + * + * \warning This function may be called with \a erase set to \c false only if + * the destination consists only of erased words, i.e. this function + * can not be used to write only one bit of a previously written word. + * E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the + * resulting value in flash may be different from \c 0x00000000. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern volatile void *flashc_memset16(volatile void *dst, U16 src, size_t nbytes, bool erase); + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the repeated \a src big-endian source word. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Source word. + * \param nbytes Number of bytes to set. + * \param erase Whether to erase before writing: \c true or \c false. + * + * \return The value of \a dst. + * + * \warning This function may be called with \a erase set to \c false only if + * the destination consists only of erased words, i.e. this function + * can not be used to write only one bit of a previously written word. + * E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the + * resulting value in flash may be different from \c 0x00000000. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern volatile void *flashc_memset32(volatile void *dst, U32 src, size_t nbytes, bool erase); + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the repeated \a src big-endian source double-word. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Source double-word. + * \param nbytes Number of bytes to set. + * \param erase Whether to erase before writing: \c true or \c false. + * + * \return The value of \a dst. + * + * \warning This function may be called with \a erase set to \c false only if + * the destination consists only of erased words, i.e. this function + * can not be used to write only one bit of a previously written word. + * E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the + * resulting value in flash may be different from \c 0x00000000. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern volatile void *flashc_memset64(volatile void *dst, U64 src, size_t nbytes, bool erase); + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the repeated \a src big-endian source pattern. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Source double-word. + * \param src_width \a src width in bits: 8, 16, 32 or 64. + * \param nbytes Number of bytes to set. + * \param erase Whether to erase before writing: \c true or \c false. + * + * \return The value of \a dst. + * + * \warning This function may be called with \a erase set to \c false only if + * the destination consists only of erased words, i.e. this function + * can not be used to write only one bit of a previously written word. + * E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the + * resulting value in flash may be different from \c 0x00000000. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +#define flashc_memset(dst, src, src_width, nbytes, erase) \ + TPASTE2(flashc_memset, src_width)((dst), (src), (nbytes), (erase)) + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the source pointed to by \a src. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Pointer to source data. + * \param nbytes Number of bytes to copy. + * \param erase Whether to erase before writing: \c true or \c false. + * + * \return The value of \a dst. + * + * \warning If copying takes place between areas that overlap, the behavior is + * undefined. + * + * \warning This function may be called with \a erase set to \c false only if + * the destination consists only of erased words, i.e. this function + * can not be used to write only one bit of a previously written word. + * E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the + * resulting value in flash may be different from \c 0x00000000. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern volatile void *flashc_memcpy(volatile void *dst, const void *src, size_t nbytes, bool erase); + +#if UC3C + +/*! \brief Depednding to the CPU frequency, set the wait states of flash read + * accesses and enable or disable the High speed read mode. + * + * \param cpu_f_hz The CPU frequency + */ +void flashc_set_flash_waitstate_and_readmode(unsigned long cpu_f_hz); +#endif // UC3C device-specific implementation + +//! @} + + +#endif // _FLASHC_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/gpio/gpio.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/gpio/gpio.c new file mode 100644 index 0000000..6b30ef0 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/gpio/gpio.c @@ -0,0 +1,649 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief GPIO software driver interface for AVR UC3. + * + * - Compiler: GCC and IAR for AVR + * - Supported devices: All AVR UC3 devices with a GPIO module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2010 - 2011 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include "gpio.h" + +//! GPIO module instance. +#define GPIO AVR32_GPIO + + +/*! \name Peripheral Bus Interface + */ +//! @{ + + +int gpio_enable_module(const gpio_map_t gpiomap, uint32_t size) +{ + int status = GPIO_SUCCESS; + uint32_t i; + + for (i = 0; i < size; i++) + { + status |= gpio_enable_module_pin(gpiomap->pin, gpiomap->function); + gpiomap++; + } + + return status; +} + + +int gpio_enable_module_pin(uint32_t pin, uint32_t function) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + // Enable the correct function. + switch (function) + { + case 0: // A function. + gpio_port->pmr0c = 1 << (pin & 0x1F); + gpio_port->pmr1c = 1 << (pin & 0x1F); +#if (AVR32_GPIO_H_VERSION >= 210) + gpio_port->pmr2c = 1 << (pin & 0x1F); +#endif + break; + + case 1: // B function. + gpio_port->pmr0s = 1 << (pin & 0x1F); + gpio_port->pmr1c = 1 << (pin & 0x1F); +#if (AVR32_GPIO_H_VERSION >= 210) + gpio_port->pmr2c = 1 << (pin & 0x1F); +#endif + break; + + case 2: // C function. + gpio_port->pmr0c = 1 << (pin & 0x1F); + gpio_port->pmr1s = 1 << (pin & 0x1F); +#if (AVR32_GPIO_H_VERSION >= 210) + gpio_port->pmr2c = 1 << (pin & 0x1F); +#endif + break; + + case 3: // D function. + gpio_port->pmr0s = 1 << (pin & 0x1F); + gpio_port->pmr1s = 1 << (pin & 0x1F); +#if (AVR32_GPIO_H_VERSION >= 210) + gpio_port->pmr2c = 1 << (pin & 0x1F); +#endif + break; + +#if (AVR32_GPIO_H_VERSION >= 210) + case 4: // E function. + gpio_port->pmr0c = 1 << (pin & 0x1F); + gpio_port->pmr1c = 1 << (pin & 0x1F); + gpio_port->pmr2s = 1 << (pin & 0x1F); + break; + + case 5: // F function. + gpio_port->pmr0s = 1 << (pin & 0x1F); + gpio_port->pmr1c = 1 << (pin & 0x1F); + gpio_port->pmr2s = 1 << (pin & 0x1F); + break; + + case 6: // G function. + gpio_port->pmr0c = 1 << (pin & 0x1F); + gpio_port->pmr1s = 1 << (pin & 0x1F); + gpio_port->pmr2s = 1 << (pin & 0x1F); + break; + + case 7: // H function. + gpio_port->pmr0s = 1 << (pin & 0x1F); + gpio_port->pmr1s = 1 << (pin & 0x1F); + gpio_port->pmr2s = 1 << (pin & 0x1F); + break; +#endif + + default: + return GPIO_INVALID_ARGUMENT; + } + + // Disable GPIO control. + gpio_port->gperc = 1 << (pin & 0x1F); + + return GPIO_SUCCESS; +} + + +void gpio_enable_gpio(const gpio_map_t gpiomap, uint32_t size) +{ + uint32_t i; + + for (i = 0; i < size; i++) + { + gpio_enable_gpio_pin(gpiomap->pin); + gpiomap++; + } +} + + +void gpio_enable_gpio_pin(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->oderc = 1 << (pin & 0x1F); + gpio_port->gpers = 1 << (pin & 0x1F); +} + + +// The open-drain mode is not synthesized on the current AVR32 products. +// If one day some AVR32 products have this feature, the corresponding part +// numbers should be listed in the #if below. +// Note that other functions are available in this driver to use pins with open +// drain in GPIO mode. The advantage of the open-drain mode functions over these +// other functions is that they can be used not only in GPIO mode but also in +// module mode. +#if 0 + + +void gpio_enable_pin_open_drain(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->odmers = 1 << (pin & 0x1F); +} + + +void gpio_disable_pin_open_drain(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->odmerc = 1 << (pin & 0x1F); +} + + +#endif + + +void gpio_enable_pin_pull_up(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->puers = 1 << (pin & 0x1F); +#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_212_H_INCLUDED) + gpio_port->pderc = 1 << (pin & 0x1F); +#endif +} + + +void gpio_disable_pin_pull_up(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->puerc = 1 << (pin & 0x1F); +} + +#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_212_H_INCLUDED) +// Added support of Pull-up Resistor, Pull-down Resistor and Buskeeper Control. + +/*! \brief Enables the pull-down resistor of a pin. + * + * \param pin The pin number. + */ +void gpio_enable_pin_pull_down(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->puerc = 1 << (pin & 0x1F); + gpio_port->pders = 1 << (pin & 0x1F); +} + +/*! \brief Disables the pull-down resistor of a pin. + * + * \param pin The pin number. + */ +void gpio_disable_pin_pull_down(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->pderc = 1 << (pin & 0x1F); +} + +/*! \brief Enables the buskeeper functionality on a pin. + * + * \param pin The pin number. + */ +void gpio_enable_pin_buskeeper(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->puers = 1 << (pin & 0x1F); + gpio_port->pders = 1 << (pin & 0x1F); +} + +/*! \brief Disables the buskeeper functionality on a pin. + * + * \param pin The pin number. + */ +void gpio_disable_pin_buskeeper(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->puerc = 1 << (pin & 0x1F); + gpio_port->pderc = 1 << (pin & 0x1F); +} + +#endif + +void gpio_configure_pin(uint32_t pin, uint32_t flags) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + /* Both pull-up and pull-down set means buskeeper */ +#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_212_H_INCLUDED) + if (flags & GPIO_PULL_DOWN) + gpio_port->pders = 1 << (pin & 0x1F); + else + gpio_port->pderc = 1 << (pin & 0x1F); +#endif + if (flags & GPIO_PULL_UP) + gpio_port->puers = 1 << (pin & 0x1F); + else + gpio_port->puerc = 1 << (pin & 0x1F); + + /* Enable open-drain mode if requested */ +#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_212_H_INCLUDED) + if (flags & GPIO_OPEN_DRAIN) + gpio_port->odmers = 1 << (pin & 0x1F); + else + gpio_port->odmerc = 1 << (pin & 0x1F); + + if (flags & GPIO_OPEN_DRAIN) + gpio_port->pders = 1 << (pin & 0x1F); + else + gpio_port->pderc = 1 << (pin & 0x1F); +#endif + +#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_212_H_INCLUDED) + /* Select drive strength */ + if (flags & GPIO_DRIVE_LOW) + gpio_port->odcr0s = 1 << (pin & 0x1F); + else + gpio_port->odcr0c = 1 << (pin & 0x1F); + if (flags & GPIO_DRIVE_HIGH) + gpio_port->odcr1s = 1 << (pin & 0x1F); + else + gpio_port->odcr1c = 1 << (pin & 0x1F); +#endif + + /* Select interrupt level for group */ + if (flags & GPIO_INTERRUPT) { + if (flags & GPIO_BOTHEDGES) + { + gpio_port->imr0c = 1 << (pin & 0x1F); + gpio_port->imr1c = 1 << (pin & 0x1F); + } + else if (flags & GPIO_RISING) + { + gpio_port->imr0s = 1 << (pin & 0x1F); + gpio_port->imr1c = 1 << (pin & 0x1F); + } + else if (flags & GPIO_FALLING) + { + gpio_port->imr0c = 1 << (pin & 0x1F); + gpio_port->imr1s = 1 << (pin & 0x1F); + } + } + + /* Select direction and initial pin state */ + if (flags & GPIO_DIR_OUTPUT) { + if (flags & GPIO_INIT_HIGH) + gpio_port->ovrs = 1 << (pin & 0x1F); + else + gpio_port->ovrc = 1 << (pin & 0x1F); + gpio_port->oders = 1 << (pin & 0x1F); + } else { + gpio_port->oderc = 1 << (pin & 0x1F); + } + + /* Enable GPIO */ + gpio_port->gpers = 1 << (pin & 0x1F); +} + +void gpio_configure_group(uint32_t port, uint32_t mask, uint32_t flags) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[port]; + + /* Both pull-up and pull-down set means buskeeper */ +#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_212_H_INCLUDED) + if (flags & GPIO_PULL_DOWN) + gpio_port->pders = mask; + else + gpio_port->pderc = mask; +#endif + if (flags & GPIO_PULL_UP) + gpio_port->puers = mask; + else + gpio_port->puerc = mask; + + /* Enable open-drain mode if requested */ +#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_212_H_INCLUDED) + if (flags & GPIO_OPEN_DRAIN) + gpio_port->odmers = mask; + else + gpio_port->odmerc = mask; + + if (flags & GPIO_OPEN_DRAIN) + gpio_port->pders = mask; + else + gpio_port->pderc = mask; +#endif + +#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_212_H_INCLUDED) + /* Select drive strength */ + if (flags & GPIO_DRIVE_LOW) + gpio_port->odcr0s = mask; + else + gpio_port->odcr0c = mask; + if (flags & GPIO_DRIVE_HIGH) + gpio_port->odcr1s = mask; + else + gpio_port->odcr1c = mask; +#endif + + /* Select interrupt level for group */ + if (flags & GPIO_INTERRUPT) { + if (flags & GPIO_BOTHEDGES) + { + gpio_port->imr0c = mask; + gpio_port->imr1c = mask; + } + else if (flags & GPIO_RISING) + { + gpio_port->imr0s = mask; + gpio_port->imr1c = mask; + } + else if (flags & GPIO_FALLING) + { + gpio_port->imr0c = mask; + gpio_port->imr1s = mask; + } + } + + /* Select direction and initial pin state */ + if (flags & GPIO_DIR_OUTPUT) { + if (flags & GPIO_INIT_HIGH) + gpio_port->ovrs = mask; + else + gpio_port->ovrc = mask; + gpio_port->oders = mask; + } else { + gpio_port->oderc = mask; + } + + /* Enable GPIO */ + gpio_port->gpers = mask; +} + +int gpio_get_pin_value(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + return (gpio_port->pvr >> (pin & 0x1F)) & 1; +} + + +int gpio_get_gpio_pin_output_value(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + return (gpio_port->ovr >> (pin & 0x1F)) & 1; +} + + +int gpio_get_gpio_open_drain_pin_output_value(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + return ((gpio_port->oder >> (pin & 0x1F)) & 1) ^ 1; +} + + +void gpio_set_gpio_pin(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->ovrs = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 1. + gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + +void gpio_set_pin_high(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->ovrs = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 1. +} + +void gpio_set_group_high(uint32_t port, uint32_t mask) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[port]; + gpio_port->ovrs = mask; // Value to be driven on the I/O group: 1. +} + + +void gpio_set_pin_low(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0. +} + +void gpio_clr_gpio_pin(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0. + gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + +void gpio_set_group_low(uint32_t port, uint32_t mask) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[port]; + gpio_port->ovrc = mask; // Value to be driven on the I/O group: 0. +} + +void gpio_tgl_gpio_pin(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->ovrt = 1 << (pin & 0x1F); // Toggle the I/O line. + gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + +void gpio_toggle_pin(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->ovrt = 1 << (pin & 0x1F); // Toggle the I/O line. +} + +void gpio_toggle_group(uint32_t port, uint32_t mask) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[port]; + gpio_port->ovrt = mask; // Toggle the I/O port. +} + +void gpio_set_gpio_open_drain_pin(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + gpio_port->oderc = 1 << (pin & 0x1F); // The GPIO output driver is disabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + + +void gpio_clr_gpio_open_drain_pin(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0. + gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + + +void gpio_tgl_gpio_open_drain_pin(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line if the GPIO output driver is enabled: 0. + gpio_port->odert = 1 << (pin & 0x1F); // The GPIO output driver is toggled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + + +void gpio_enable_pin_glitch_filter(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->gfers = 1 << (pin & 0x1F); +} + + +void gpio_disable_pin_glitch_filter(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->gferc = 1 << (pin & 0x1F); +} + +/*! \brief Configure the edge detector of an input pin + * + * \param pin The pin number. + * \param mode The edge detection mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE + * or \ref GPIO_FALLING_EDGE). + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +static int gpio_configure_edge_detector(uint32_t pin, uint32_t mode) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + // Configure the edge detector. + switch (mode) + { + case GPIO_PIN_CHANGE: + gpio_port->imr0c = 1 << (pin & 0x1F); + gpio_port->imr1c = 1 << (pin & 0x1F); + break; + + case GPIO_RISING_EDGE: + gpio_port->imr0s = 1 << (pin & 0x1F); + gpio_port->imr1c = 1 << (pin & 0x1F); + break; + + case GPIO_FALLING_EDGE: + gpio_port->imr0c = 1 << (pin & 0x1F); + gpio_port->imr1s = 1 << (pin & 0x1F); + break; + + default: + return GPIO_INVALID_ARGUMENT; + } + + return GPIO_SUCCESS; +} + + +int gpio_enable_pin_interrupt(uint32_t pin, uint32_t mode) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + // Enable the glitch filter. + gpio_port->gfers = 1 << (pin & 0x1F); + + // Configure the edge detector. + if(GPIO_INVALID_ARGUMENT == gpio_configure_edge_detector(pin, mode)) + return(GPIO_INVALID_ARGUMENT); + + // Enable interrupt. + gpio_port->iers = 1 << (pin & 0x1F); + + return GPIO_SUCCESS; +} + + +void gpio_disable_pin_interrupt(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->ierc = 1 << (pin & 0x1F); +} + + +int gpio_get_pin_interrupt_flag(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + return (gpio_port->ifr >> (pin & 0x1F)) & 1; +} + + +void gpio_clear_pin_interrupt_flag(uint32_t pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; +#if (AVR32_GPIO_H_VERSION == 211) + // Save interrupt enable register. + uint32_t const gpio_ier = gpio_port->ier; + + // Disable interrupt. + gpio_port->ierc = 1 << (pin & 0x1F); + + // Clear pin interrupt. + gpio_port->ifrc = 1 << (pin & 0x1F); + + // Restore interrupt enable register. + gpio_port->ier = gpio_ier; +#else + gpio_port->ifrc = 1 << (pin & 0x1F); +#endif +} + + +//# +//# Peripheral Event System Support. +//# +#if UC3L +int gpio_configure_pin_periph_event_mode(uint32_t pin, uint32_t mode, uint32_t use_igf) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + if(true == use_igf) + { + // Enable the glitch filter. + gpio_port->gfers = 1 << (pin & 0x1F); + } + else + { + // Disable the glitch filter. + gpio_port->gferc = 1 << (pin & 0x1F); + } + + // Configure the edge detector. + return(gpio_configure_edge_detector(pin, mode)); +} + +#endif + +//! @} diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/gpio/gpio.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/gpio/gpio.h new file mode 100644 index 0000000..ad4ca0f --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/gpio/gpio.h @@ -0,0 +1,680 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief GPIO software driver interface for AVR UC3. + * + * - Compiler: GCC and IAR for AVR + * - Supported devices: All AVR UC3 devices with a GPIO module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2010 - 2011 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _GPIO_H_ +#define _GPIO_H_ + +#include +#include "compiler.h" + +/*! \name Return Values of the GPIO API + */ +//! @{ +#define GPIO_SUCCESS 0 //!< Function successfully completed. +#define GPIO_INVALID_ARGUMENT 1 //!< Input parameters are out of range. +//! @} + + +/*! \name Interrupt Trigger Modes + */ +//! @{ +#define GPIO_PIN_CHANGE 0 //!< Interrupt triggered upon pin change. +#define GPIO_RISING_EDGE 1 //!< Interrupt triggered upon rising edge. +#define GPIO_FALLING_EDGE 2 //!< Interrupt triggered upon falling edge. +//! @} + +/*! \name Common defines for GPIO_FLAGS parameter + */ +//! @{ +#define GPIO_DIR_INPUT (0 << 0) //!< Pin is Input +#define GPIO_DIR_OUTPUT (1 << 0) //!< Pin is Output +#define GPIO_INIT_LOW (0 << 1) //!< Initial Ouptput State is Low +#define GPIO_INIT_HIGH (1 << 1) //!< Initial Ouptput State is High +#define GPIO_PULL_UP (1 << 2) //!< Pull-Up (when input) +#define GPIO_PULL_DOWN (2 << 2) //!< Pull-Down (when input) +#define GPIO_BUSKEEPER (3 << 2) //!< Bus Keeper +#define GPIO_DRIVE_MIN (0 << 4) //!< Drive Min Configuration +#define GPIO_DRIVE_LOW (1 << 4) //!< Drive Low Configuration +#define GPIO_DRIVE_HIGH (2 << 4) //!< Drive High Configuration +#define GPIO_DRIVE_MAX (3 << 4) //!< Drive Max Configuration +#define GPIO_OPEN_DRAIN (1 << 6) //!< Open-Drain (when output) +#define GPIO_INTERRUPT (1 << 7) //!< Enable Pin/Group Interrupt +#define GPIO_BOTHEDGES (3 << 7) //!< Sense Both Edges +#define GPIO_RISING (5 << 7) //!< Sense Risign Edge +#define GPIO_FALLING (7 << 7) //!< Sense Falling Edge +//! @} + +//! A type definition of pins and modules connectivity. +typedef struct +{ + unsigned char pin; //!< Module pin. + unsigned char function; //!< Module function. +} gpio_map_t[]; + + +/*! \name Peripheral Bus Interface + * + * Low-speed interface with a non-deterministic number of clock cycles per + * access. + * + * This interface operates with lower clock frequencies (fPB <= fCPU), and its + * timing is not deterministic since it needs to access a shared bus which may + * be heavily loaded. + * + * \note This interface is immediately available without initialization. + */ +//! @{ + +/*! \brief Enables specific module modes for a set of pins. + * + * \param gpiomap The pin map. + * \param size The number of pins in \a gpiomap. + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +extern int gpio_enable_module(const gpio_map_t gpiomap, uint32_t size); + +/*! \brief Enables a specific module mode for a pin. + * + * \param pin The pin number.\n + * Refer to the product header file `uc3x.h' (where x is the part + * number; e.g. x = a0512) for module pins. E.g., to enable a PWM + * channel output, the pin number can be AVR32_PWM_3_PIN for PWM + * channel 3. + * \param function The pin function.\n + * Refer to the product header file `uc3x.h' (where x is the + * part number; e.g. x = a0512) for module pin functions. E.g., + * to enable a PWM channel output, the pin function can be + * AVR32_PWM_3_FUNCTION for PWM channel 3. + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +extern int gpio_enable_module_pin(uint32_t pin, uint32_t function); + +/*! \brief Enables the GPIO mode of a set of pins. + * + * \param gpiomap The pin map. + * \param size The number of pins in \a gpiomap. + */ +extern void gpio_enable_gpio(const gpio_map_t gpiomap, uint32_t size); + +/*! \brief Enables the GPIO mode of a pin. + * + * \param pin The pin number.\n + * Refer to the product header file `uc3x.h' (where x is the part + * number; e.g. x = a0512) for pin definitions. E.g., to enable the + * GPIO mode of PX21, AVR32_PIN_PX21 can be used. Module pins such as + * AVR32_PWM_3_PIN for PWM channel 3 can also be used to release + * module pins for GPIO. + */ +extern void gpio_enable_gpio_pin(uint32_t pin); + +// The open-drain mode is not synthesized on the current AVR32 products. +// If one day some AVR32 products have this feature, the corresponding part +// numbers should be listed in the #if below. +// Note that other functions are available in this driver to use pins with open +// drain in GPIO mode. The advantage of the open-drain mode functions over these +// other functions is that they can be used not only in GPIO mode but also in +// module mode. +#if 0 + +/*! \brief Enables the open-drain mode of a pin. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_open_drain(uint32_t pin); + +/*! \brief Disables the open-drain mode of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_open_drain(uint32_t pin); + +#endif + +/*! \brief Enables the pull-up resistor of a pin. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_pull_up(uint32_t pin); + +/*! \brief Disables the pull-up resistor of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_pull_up(uint32_t pin); + +#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_212_H_INCLUDED) +// Added support of Pull-up Resistor, Pull-down Resistor and Buskeeper Control. + +/*! \brief Enables the pull-down resistor of a pin. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_pull_down(uint32_t pin); + +/*! \brief Disables the pull-down resistor of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_pull_down(uint32_t pin); + +/*! \brief Enables the buskeeper functionality on a pin. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_buskeeper(uint32_t pin); + +/*! \brief Disables the buskeeper functionality on a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_buskeeper(uint32_t pin); + +#endif + +/*! \brief Configuration functionality on a pin. + * + * \param pin The pin number. + * \param flags The configuration. + */ +extern void gpio_configure_pin(uint32_t pin, uint32_t flags); + +/*! \brief Configuration functionality on a port. + * + * \param port The port number. + * \param mask The mask. + * \param flags The configuration. + */ +extern void gpio_configure_group(uint32_t port, uint32_t mask, uint32_t flags); + +/*! \brief Returns the value of a pin. + * + * \param pin The pin number. + * + * \return The pin value. + */ +extern int gpio_get_pin_value(uint32_t pin); + +/*! + * \brief Check if the pin is in low logical level. + * + * \param pin The pin number. + * \return bool 1 if the pin is in low logical level + * 0 if the pin is not in low logical level + */ + #define gpio_pin_is_low(pin)\ + (gpio_get_pin_value(pin)?0:1) + +/*! + * \brief Check if the pin is in high logical level. + * + * \param pin The pin number. + * \return bool 1 if the pin is in high logical level + * 0 if the pin is not in high logical level + */ +#define gpio_pin_is_high(pin) \ + (gpio_get_pin_value(pin)?1:0) + +/*! \brief Returns the output value set for a GPIO pin. + * + * \param pin The pin number. + * + * \return The pin output value. + * + * \note This function must be used in conjunction with \ref gpio_set_gpio_pin, + * \ref gpio_clr_gpio_pin and \ref gpio_tgl_gpio_pin. + */ +extern int gpio_get_gpio_pin_output_value(uint32_t pin); + +/*! \brief Returns the output value set for a GPIO pin using open drain. + * + * \param pin The pin number. + * + * \return The pin output value. + * + * \note This function must be used in conjunction with + * \ref gpio_set_gpio_open_drain_pin, \ref gpio_clr_gpio_open_drain_pin + * and \ref gpio_tgl_gpio_open_drain_pin. + */ +extern int gpio_get_gpio_open_drain_pin_output_value(uint32_t pin); + +/*! \brief Drives a GPIO pin to 1. + * + * \param pin The pin number. + */ +extern void gpio_set_gpio_pin(uint32_t pin); + +/*! \brief Drives a GPIO pin to 1. + * + * \param pin The pin number. + * + * \note The function \ref gpio_configure_pin must be called before. + */ +extern void gpio_set_pin_high(uint32_t pin); + + +/*! \brief Drives a GPIO port to 1. + * + * \param port The port number. + * \param mask The mask. + */ +extern void gpio_set_group_high(uint32_t port, uint32_t mask); + +/*! \brief Drives a GPIO pin to 0. + * + * \param pin The pin number. + */ +extern void gpio_clr_gpio_pin(uint32_t pin); + +/*! \brief Drives a GPIO pin to 0. + * + * \param pin The pin number. + * + * \note The function \ref gpio_configure_pin must be called before. + */ +extern void gpio_set_pin_low(uint32_t pin); + +/*! \brief Drives a GPIO port to 0. + * + * \param port The port number. + * \param mask The mask. + */ +extern void gpio_set_group_low(uint32_t port, uint32_t mask); + +/*! \brief Toggles a GPIO pin. + * + * \param pin The pin number. + */ +extern void gpio_tgl_gpio_pin(uint32_t pin); + +/*! \brief Toggles a GPIO pin. + * + * \param pin The pin number. + * + * \note The function \ref gpio_configure_pin must be called before. + */ +extern void gpio_toggle_pin(uint32_t pin); + +/*! \brief Toggles a GPIO group. + * + * \param port The port number. + * \param mask The mask. + */ +extern void gpio_toggle_group(uint32_t port, uint32_t mask); + +/*! \brief Drives a GPIO pin to 1 using open drain. + * + * \param pin The pin number. + */ +extern void gpio_set_gpio_open_drain_pin(uint32_t pin); + +/*! \brief Drives a GPIO pin to 0 using open drain. + * + * \param pin The pin number. + */ +extern void gpio_clr_gpio_open_drain_pin(uint32_t pin); + +/*! \brief Toggles a GPIO pin using open drain. + * + * \param pin The pin number. + */ +extern void gpio_tgl_gpio_open_drain_pin(uint32_t pin); + +/*! \brief Enables the glitch filter of a pin. + * + * When the glitch filter is enabled, a glitch with duration of less than 1 + * clock cycle is automatically rejected, while a pulse with duration of 2 clock + * cycles or more is accepted. For pulse durations between 1 clock cycle and 2 + * clock cycles, the pulse may or may not be taken into account, depending on + * the precise timing of its occurrence. Thus for a pulse to be guaranteed + * visible it must exceed 2 clock cycles, whereas for a glitch to be reliably + * filtered out, its duration must not exceed 1 clock cycle. The filter + * introduces 2 clock cycles latency. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_glitch_filter(uint32_t pin); + +/*! \brief Disables the glitch filter of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_glitch_filter(uint32_t pin); + +/*! \brief Enables the interrupt of a pin with the specified settings. + * + * \param pin The pin number. + * \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or + * \ref GPIO_FALLING_EDGE). + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +extern int gpio_enable_pin_interrupt(uint32_t pin, uint32_t mode); + +/*! \brief Disables the interrupt of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_interrupt(uint32_t pin); + +/*! \brief Gets the interrupt flag of a pin. + * + * \param pin The pin number. + * + * \return The pin interrupt flag. + */ +extern int gpio_get_pin_interrupt_flag(uint32_t pin); + +/*! \brief Clears the interrupt flag of a pin. + * + * \param pin The pin number. + */ +extern void gpio_clear_pin_interrupt_flag(uint32_t pin); + +//! @} + + +#if (defined AVR32_GPIO_LOCAL_ADDRESS) +/*! \name Local Bus Interface + * + * High-speed interface with only one clock cycle per access. + * + * This interface operates with high clock frequency (fCPU), and its timing is + * deterministic since it does not need to access a shared bus which may be + * heavily loaded. + * + * \warning To use this interface, the clock frequency of the peripheral bus on + * which the GPIO peripheral is connected must be set to the CPU clock + * frequency (fPB = fCPU). + * + * \note This interface has to be initialized in order to be available. + */ +//! @{ + +/*! \brief Enables the local bus interface for GPIO. + * + * \note This function must have been called at least once before using other + * functions in this interface. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void gpio_local_init(void) +{ + Set_system_register(AVR32_CPUCR, + Get_system_register(AVR32_CPUCR) | AVR32_CPUCR_LOCEN_MASK); +} + +/*! \brief Enables the output driver of a pin. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init must have been called beforehand. + * + * \note This function does not enable the GPIO mode of the pin. + * \ref gpio_enable_gpio_pin can be called for this purpose. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void gpio_local_enable_pin_output_driver(uint32_t pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F); +} + +/*! \brief Disables the output driver of a pin. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init must have been called beforehand. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void gpio_local_disable_pin_output_driver(uint32_t pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F); +} + +/*! \brief Returns the value of a pin. + * + * \param pin The pin number. + * + * \return The pin value. + * + * \note \ref gpio_local_init must have been called beforehand. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +static inline int gpio_local_get_pin_value(uint32_t pin) +{ + return (AVR32_GPIO_LOCAL.port[pin >> 5].pvr >> (pin & 0x1F)) & 1; +} + +/*! \brief Drives a GPIO pin to 1. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init must have been called beforehand. + * + * \note This function does not enable the GPIO mode of the pin nor its output + * driver. \ref gpio_enable_gpio_pin and + * \ref gpio_local_enable_pin_output_driver can be called for this + * purpose. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void gpio_local_set_gpio_pin(uint32_t pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].ovrs = 1 << (pin & 0x1F); +} + +/*! \brief Drives a GPIO pin to 0. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init must have been called beforehand. + * + * \note This function does not enable the GPIO mode of the pin nor its output + * driver. \ref gpio_enable_gpio_pin and + * \ref gpio_local_enable_pin_output_driver can be called for this + * purpose. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void gpio_local_clr_gpio_pin(uint32_t pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F); +} + +/*! \brief Toggles a GPIO pin. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init must have been called beforehand. + * + * \note This function does not enable the GPIO mode of the pin nor its output + * driver. \ref gpio_enable_gpio_pin and + * \ref gpio_local_enable_pin_output_driver can be called for this + * purpose. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void gpio_local_tgl_gpio_pin(uint32_t pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].ovrt = 1 << (pin & 0x1F); +} + +/*! \brief Initializes the configuration of a GPIO pin so that it can be used + * with GPIO open-drain functions. + * + * \note This function must have been called at least once before using + * \ref gpio_local_set_gpio_open_drain_pin, + * \ref gpio_local_clr_gpio_open_drain_pin or + * \ref gpio_local_tgl_gpio_open_drain_pin. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void gpio_local_init_gpio_open_drain_pin(uint32_t pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F); +} + +/*! \brief Drives a GPIO pin to 1 using open drain. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must + * have been called beforehand. + * + * \note This function does not enable the GPIO mode of the pin. + * \ref gpio_enable_gpio_pin can be called for this purpose. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void gpio_local_set_gpio_open_drain_pin(uint32_t pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F); +} + +/*! \brief Drives a GPIO pin to 0 using open drain. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must + * have been called beforehand. + * + * \note This function does not enable the GPIO mode of the pin. + * \ref gpio_enable_gpio_pin can be called for this purpose. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void gpio_local_clr_gpio_open_drain_pin(uint32_t pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F); +} + +/*! \brief Toggles a GPIO pin using open drain. + * + * \param pin The pin number. + * + * \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must + * have been called beforehand. + * + * \note This function does not enable the GPIO mode of the pin. + * \ref gpio_enable_gpio_pin can be called for this purpose. + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void gpio_local_tgl_gpio_open_drain_pin(uint32_t pin) +{ + AVR32_GPIO_LOCAL.port[pin >> 5].odert = 1 << (pin & 0x1F); +} + +//! @} +#endif // AVR32_GPIO_LOCAL_ADDRESS + +#if UC3L +//! @{ +/*! \name Peripheral Event System support + * + * The GPIO can be programmed to output peripheral events whenever an interrupt + * condition is detected, such as pin value change, or only when a rising or + * falling edge is detected. + * + */ + +/*! \brief Enables the peripheral event generation of a pin. + * + * \param pin The pin number. + * + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void gpio_enable_pin_periph_event(uint32_t pin) +{ + AVR32_GPIO.port[pin >> 5].oderc = 1 << (pin & 0x1F); // The GPIO output driver is disabled for that pin. + AVR32_GPIO.port[pin >> 5].evers = 1 << (pin & 0x1F); +} + +/*! \brief Disables the peripheral event generation of a pin. + * + * \param pin The pin number. + * + */ +#if (defined __GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void gpio_disable_pin_periph_event(uint32_t pin) +{ + AVR32_GPIO.port[pin >> 5].everc = 1 << (pin & 0x1F); +} + +/*! \brief Configure the peripheral event trigger mode of a pin + * + * \param pin The pin number. + * \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or + * \ref GPIO_FALLING_EDGE). + * \param use_igf use the Input Glitch Filter (true) or not (false). + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +extern int gpio_configure_pin_periph_event_mode(uint32_t pin, uint32_t mode, uint32_t use_igf); + +//! @} +#endif + + +#endif // _GPIO_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/intc/exception.S b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/intc/exception.S new file mode 100644 index 0000000..933002e --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/intc/exception.S @@ -0,0 +1,237 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Exception and interrupt vectors. + * + * This file maps all events supported by an AVR32. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#if !__AVR32_UC__ && !__AVR32_AP__ + #error Implementation of the AVR32 architecture not supported by the INTC driver. +#endif + + +#include + + +//! @{ +//! \verbatim + + + .section .exception, "ax", @progbits + + +// Start of Exception Vector Table. + + // EVBA must be aligned with a power of two strictly greater than the EVBA- + // relative offset of the last vector. + .balign 0x200 + + // Export symbol. + .global _evba + .type _evba, @function +_evba: + + .org 0x000 + // Unrecoverable Exception. +_handle_Unrecoverable_Exception: + rjmp $ + + .org 0x004 + // TLB Multiple Hit. +_handle_TLB_Multiple_Hit: + rjmp $ + + .org 0x008 + // Bus Error Data Fetch. +_handle_Bus_Error_Data_Fetch: + rjmp $ + + .org 0x00C + // Bus Error Instruction Fetch. +_handle_Bus_Error_Instruction_Fetch: + rjmp $ + + .org 0x010 + // NMI. +_handle_NMI: + rjmp $ + + .org 0x014 + // Instruction Address. +_handle_Instruction_Address: + rjmp $ + + .org 0x018 + // ITLB Protection. +_handle_ITLB_Protection: + rjmp $ + + .org 0x01C + // Breakpoint. +_handle_Breakpoint: + rjmp $ + + .org 0x020 + // Illegal Opcode. +_handle_Illegal_Opcode: + rjmp $ + + .org 0x024 + // Unimplemented Instruction. +_handle_Unimplemented_Instruction: + rjmp $ + + .org 0x028 + // Privilege Violation. +_handle_Privilege_Violation: + rjmp $ + + .org 0x02C + // Floating-Point: UNUSED IN AVR32UC and AVR32AP. +_handle_Floating_Point: + rjmp $ + + .org 0x030 + // Coprocessor Absent: UNUSED IN AVR32UC. +_handle_Coprocessor_Absent: + rjmp $ + + .org 0x034 + // Data Address (Read). +_handle_Data_Address_Read: + rjmp $ + + .org 0x038 + // Data Address (Write). +_handle_Data_Address_Write: + rjmp $ + + .org 0x03C + // DTLB Protection (Read). +_handle_DTLB_Protection_Read: + rjmp $ + + .org 0x040 + // DTLB Protection (Write). +_handle_DTLB_Protection_Write: + rjmp $ + + .org 0x044 + // DTLB Modified: UNUSED IN AVR32UC. +_handle_DTLB_Modified: + rjmp $ + + .org 0x050 + // ITLB Miss. +_handle_ITLB_Miss: + rjmp $ + + .org 0x060 + // DTLB Miss (Read). +_handle_DTLB_Miss_Read: + rjmp $ + + .org 0x070 + // DTLB Miss (Write). +_handle_DTLB_Miss_Write: + rjmp $ + + .org 0x100 + // Supervisor Call. +_handle_Supervisor_Call: + rjmp $ + + +// Interrupt support. +// The interrupt controller must provide the offset address relative to EVBA. +// Important note: +// All interrupts call a C function named _get_interrupt_handler. +// This function will read group and interrupt line number to then return in +// R12 a pointer to a user-provided interrupt handler. + + .balign 4 + + .irp priority, 0, 1, 2, 3 +_int\priority: +#if __AVR32_UC__ + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. No other register is saved by hardware. +#elif __AVR32_AP__ + // PC and SR are automatically saved in respectively RAR_INTx and RSR_INTx by + // the CPU upon interrupt entry. No other register is saved by hardware. + pushm r8-r12, lr +#endif + mov r12, \priority // Pass the int_level parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. +#if __AVR32_UC__ + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. +#elif __AVR32_AP__ + breq spint\priority // If this was a spurious interrupt (R12 == NULL), branch. + st.w --sp, r12 // Push the pointer to the interrupt handler onto the system stack since no register may be altered. + popm r8-r12, lr, pc // Restore registers and jump to the handler. +spint\priority: + popm r8-r12, lr +#endif + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + .endr + + +// Constant data area. + + .balign 4 + + // Values to store in the interrupt priority registers for the various interrupt priority levels. + // The interrupt priority registers contain the interrupt priority level and + // the EVBA-relative interrupt vector offset. + .global ipr_val + .type ipr_val, @object +ipr_val: + .word (AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int0 - _evba),\ + (AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int1 - _evba),\ + (AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int2 - _evba),\ + (AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int3 - _evba) + + +//! \endverbatim +//! @} diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/intc/intc.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/intc/intc.c new file mode 100644 index 0000000..26be0d2 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/intc/intc.c @@ -0,0 +1,214 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief INTC driver for AVR32 UC3. + * + * AVR32 Interrupt Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include +#include "compiler.h" +#include "preprocessor.h" +#include "intc.h" + +// define _evba from exception.S +extern void _evba; + +//! Values to store in the interrupt priority registers for the various interrupt priority levels. +extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS]; + +__int_handler _get_interrupt_handler(unsigned int int_level); + +//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space. +//! Each line handler table contains a set of pointers to interrupt handlers. +#if (defined __GNUC__) +#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \ +static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)]; +#elif (defined __ICCAVR32__) +#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \ +static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)]; +#endif +MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~); +#undef DECL_INT_LINE_HANDLER_TABLE + +//! Table containing for each interrupt group the number of interrupt request +//! lines and a pointer to the table of interrupt line handlers. +static const struct +{ + unsigned int num_irqs; + volatile __int_handler *_int_line_handler_table; +} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] = +{ +#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \ + {AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP}, + MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~) +#undef INSERT_INT_LINE_HANDLER_TABLE +}; + + +/*! \brief Default interrupt handler. + * + * \note Taken and adapted from Newlib. + */ +#if (defined __GNUC__) +__attribute__((__interrupt__)) +#elif (defined __ICCAVR32__) +__interrupt +#endif +static void _unhandled_interrupt(void) +{ + // Catch unregistered interrupts. + while (true); +} + + +/*! \brief Gets the interrupt handler of the current event at the \a int_level + * interrupt priority level (called from exception.S). + * + * \param int_level Interrupt priority level to handle. + * + * \return Interrupt handler to execute. + * + * \note Taken and adapted from Newlib. + */ +__int_handler _get_interrupt_handler(unsigned int int_level) +{ + // ICR3 is mapped first, ICR0 last. + // Code in exception.S puts int_level in R12 which is used by AVR32-GCC to + // pass a single argument to a function. + unsigned int int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_level]; + unsigned int int_req = AVR32_INTC.irr[int_grp]; + + // As an interrupt may disappear while it is being fetched by the CPU + // (spurious interrupt caused by a delayed response from an MCU peripheral to + // an interrupt flag clear or interrupt disable instruction), check if there + // are remaining interrupt lines to process. + // If a spurious interrupt occurs, the status register (SR) contains an + // execution mode and interrupt level masks corresponding to a level 0 + // interrupt, whatever the interrupt priority level causing the spurious + // event. This behavior has been chosen because a spurious interrupt has not + // to be a priority one and because it may not cause any trouble to other + // interrupts. + // However, these spurious interrupts place the hardware in an unstable state + // and could give problems in other/future versions of the CPU, so the + // software has to be written so that they never occur. The only safe way of + // achieving this is to always clear or disable peripheral interrupts with the + // following sequence: + // 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR. + // 2: Perform the bus access to the peripheral register that clears or + // disables the interrupt. + // 3: Wait until the interrupt has actually been cleared or disabled by the + // peripheral. This is usually performed by reading from a register in the + // same peripheral (it DOES NOT have to be the same register that was + // accessed in step 2, but it MUST be in the same peripheral), what takes + // bus system latencies into account, but peripheral internal latencies + // (generally 0 cycle) also have to be considered. + // 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR. + // Note that steps 1 and 4 are useless inside interrupt handlers as the + // corresponding interrupt level is automatically masked by IxM (unless IxM is + // explicitly cleared by the software). + // + // Get the right IRQ handler. + // + // If several interrupt lines are active in the group, the interrupt line with + // the highest number is selected. This is to be coherent with the + // prioritization of interrupt groups performed by the hardware interrupt + // controller. + // + // If no handler has been registered for the pending interrupt, + // _unhandled_interrupt will be selected thanks to the initialization of + // _int_line_handler_table_x by INTC_init_interrupts. + // + // exception.S will provide the interrupt handler with a clean interrupt stack + // frame, with nothing more pushed onto the stack. The interrupt handler must + // manage the `rete' instruction, what can be done thanks to pure assembly, + // inline assembly or the `__attribute__((__interrupt__))' C function + // attribute. + return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL; +} + +//! Init EVBA address. This sequence might also be done in the utils/startup/startup_uc3.S file. +static __inline__ void INTC_init_evba(void) +{ + Set_system_register(AVR32_EVBA, (int)&_evba ); +} + +void INTC_init_interrupts(void) +{ + unsigned int int_grp, int_req; + + INTC_init_evba(); + + // For all interrupt groups, + for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++) + { + // For all interrupt request lines of each group, + for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++) + { + // Assign _unhandled_interrupt as default interrupt handler. + _int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt; + } + + // Set the interrupt group priority register to its default value. + // By default, all interrupt groups are linked to the interrupt priority + // level 0 and to the interrupt vector _int0. + AVR32_INTC.ipr[int_grp] = ipr_val[AVR32_INTC_INT0]; + } +} + + +void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level) +{ + // Determine the group of the IRQ. + unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP; + + // Store in _int_line_handler_table_x the pointer to the interrupt handler, so + // that _get_interrupt_handler can retrieve it when the interrupt is vectored. + _int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler; + + // Program the corresponding IPRX register to set the interrupt priority level + // and the interrupt vector offset that will be fetched by the core interrupt + // system. + // NOTE: The _intx functions are intermediate assembly functions between the + // core interrupt system and the user interrupt handler. + AVR32_INTC.ipr[int_grp] = ipr_val[int_level & (AVR32_INTC_IPR_INTLEVEL_MASK >> AVR32_INTC_IPR_INTLEVEL_OFFSET)]; +} diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/intc/intc.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/intc/intc.h new file mode 100644 index 0000000..1c5a7c1 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/intc/intc.h @@ -0,0 +1,90 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief INTC driver for AVR32 UC3. + * + * AVR32 Interrupt Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _INTC_H_ +#define _INTC_H_ + +#include "compiler.h" + + +//! Maximal number of interrupt request lines per group. +#define AVR32_INTC_MAX_NUM_IRQS_PER_GRP 32 + +//! Number of interrupt priority levels. +#define AVR32_INTC_NUM_INT_LEVELS (1 << AVR32_INTC_IPR_INTLEVEL_SIZE) + + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +/*! \brief Initializes the hardware interrupt controller driver. + * + * \note Taken and adapted from Newlib. + */ +extern void INTC_init_interrupts(void); + +/*! \brief Registers an interrupt handler. + * + * \param handler Interrupt handler to register. + * \param irq IRQ of the interrupt handler to register. + * \param int_level Interrupt priority level to assign to the group of this IRQ. + * + * \warning The interrupt handler must manage the `rete' instruction, what can + * be done thanks to pure assembly, inline assembly or the + * `__attribute__((__interrupt__))' C function attribute. + * + * \warning If several interrupt handlers of a same group are registered with + * different priority levels, only the latest priority level set will + * be effective. + * + * \note Taken and adapted from Newlib. + */ +extern void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level); + +#endif // __AVR32_ABI_COMPILER__ + + +#endif // _INTC_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/pm_uc3c.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/pm_uc3c.c new file mode 100644 index 0000000..ff6f1c0 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/pm_uc3c.c @@ -0,0 +1,277 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Power Manager(PM) driver interface. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 UC3C devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ +#include "pm_uc3c.h" + +#ifndef AVR32_PM_VERSION_RESETVALUE + #error Cannot use this software module with the current device. +#else + #if AVR32_PM_VERSION_RESETVALUE < 0x400 + #error Cannot use this software module with the current device + #endif +#endif + +/*! \name PM Writable Bit-Field Registers + */ +//! @{ + +typedef union +{ + unsigned long cfdctrl; + avr32_pm_cfdctrl_t CFDCTRL; +} u_avr32_pm_cfdctrl_t; + +typedef union +{ + unsigned long cpusel; + avr32_pm_cpusel_t CPUSEL; +} u_avr32_pm_cpusel_t; + +typedef union +{ + unsigned long pbasel; + avr32_pm_pbasel_t PBASEL; +} u_avr32_pm_pbasel_t; + +typedef union +{ + unsigned long pbbsel; + avr32_pm_pbbsel_t PBBSEL; +} u_avr32_pm_pbbsel_t; + +typedef union +{ + unsigned long pbcsel; + avr32_pm_pbcsel_t PBCSEL; +} u_avr32_pm_pbcsel_t; + +//! @} + + +/** + ** Clock Functions + **/ + +long pm_set_mclk_source(pm_clk_src_t src) +{ + // Unlock the write-protected MCCTRL register + AVR32_ENTER_CRITICAL_REGION( ); + PM_UNLOCK(AVR32_PM_MCCTRL); + AVR32_PM.mcctrl = src; + AVR32_LEAVE_CRITICAL_REGION( ); + + return PASS; +} + +long pm_config_mainclk_safety(bool cfd, bool final) +{ + u_avr32_pm_cfdctrl_t u_avr32_pm_cfdctrl = {AVR32_PM.cfdctrl}; + + // Check if the CFDCTRL register is read-only. + if(AVR32_PM.cfdctrl & AVR32_PM_CFDCTRL_SFV_MASK) + return -1; + + // Unlock the write-protected CFDCTRL register + AVR32_ENTER_CRITICAL_REGION( ); + // Modify + u_avr32_pm_cfdctrl.CFDCTRL.cfden = cfd; + u_avr32_pm_cfdctrl.CFDCTRL.sfv = final; + // Write back + PM_UNLOCK(AVR32_PM_CFDCTRL); + AVR32_PM.cfdctrl = u_avr32_pm_cfdctrl.cfdctrl; + AVR32_LEAVE_CRITICAL_REGION( ); + + return PASS; +} + +long pm_set_clk_domain_div(pm_clk_domain_t clock_domain, pm_divratio_t divratio) +{ + u_avr32_pm_cpusel_t u_avr32_pm_cpusel = {AVR32_PM.cpusel}; + +//# Implementation note: the CPUSEL and PBASEL and PBBSEL registers all have the +//# same structure. + +//# Implementation note: the ckSEL registers are contiguous and memory-mapped in +//# that order: CPUSEL, HSBSEL, PBASEL, PBBSEL. + +#ifdef AVR32SFW_INPUT_CHECK + // Check the divratio + if((divratio > PM_CPUSEL_DIVRATIO_MAX)||(divratio < 0)) + return -1; +#endif + + // ckSEL must not be written while SR.CKRDY is 0. + if(!(AVR32_PM.sr & AVR32_PM_SR_CKRDY_MASK)) + return -1; + + // Modify + u_avr32_pm_cpusel.CPUSEL.cpudiv= 1; + u_avr32_pm_cpusel.CPUSEL.cpusel = divratio; + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected ckSEL register + PM_UNLOCK(AVR32_PM_CPUSEL + clock_domain*sizeof(avr32_pm_cpusel_t)); + // Update + *(&(AVR32_PM.cpusel) + clock_domain)= u_avr32_pm_cpusel.cpusel; + AVR32_LEAVE_CRITICAL_REGION( ); + + return PASS; +} + +long pm_disable_clk_domain_div(pm_clk_domain_t clock_domain) +{ + u_avr32_pm_cpusel_t u_avr32_pm_cpusel = {AVR32_PM.cpusel}; + +//# Implementation note: the CPUSEL and PBASEL and PBBSEL and PBCSEL registers all have the +//# same structure. + +//# Implementation note: the ckSEL registers are contiguous and memory-mapped in +//# that order: CPUSEL, HSBSEL, PBASEL, PBBSEL, PBCSEL. + + // ckSEL must not be written while SR.CKRDY is 0. + if(!(AVR32_PM.sr & AVR32_PM_SR_CKRDY_MASK)) + return -1; + + // Modify + u_avr32_pm_cpusel.CPUSEL.cpudiv= DISABLE; + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected ckSEL register + PM_UNLOCK(AVR32_PM_CPUSEL + clock_domain*sizeof(avr32_pm_cpusel_t)); + // Update + *(&(AVR32_PM.cpusel) + clock_domain)= u_avr32_pm_cpusel.cpusel; + AVR32_LEAVE_CRITICAL_REGION( ); + + return PASS; +} + +long pm_wait_for_clk_ready(void) +{ + unsigned int timeout = PM_POLL_TIMEOUT; + while (!(AVR32_PM.sr & AVR32_PM_SR_CKRDY_MASK)) + { + if(--timeout == 0) + return -1; + } + return PASS; +} + + + +/** + ** Module Functions + **/ + +long pm_enable_module(unsigned long module) +{ + unsigned long domain = module>>5; +//# Implementation note: the ckMASK registers are contiguous and memory-mapped +//# in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK. + unsigned long *regptr = (unsigned long*)(&(AVR32_PM.cpumask) + domain); + unsigned long regvalue; + + + // Read + regvalue = *regptr; + // Modify + regvalue |= (1<<(module%32)); + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected ckMASK register + PM_UNLOCK(AVR32_PM_CPUMASK + domain*sizeof(avr32_pm_cpumask_t)); + // Write + *regptr = regvalue; + AVR32_LEAVE_CRITICAL_REGION( ); + + return PASS; +} + +long pm_disable_module(unsigned long module) +{ + unsigned long domain = module>>5; +//# Implementation note: the ckMASK registers are contiguous and memory-mapped +//# in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK. + volatile unsigned long *regptr = (volatile unsigned long*)(&(AVR32_PM.cpumask) + domain); + unsigned long regvalue; + + + // Read + regvalue = *regptr; + // Modify + regvalue &= ~(1<<(module%32)); + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected ckMASK register + PM_UNLOCK(AVR32_PM_CPUMASK + domain*sizeof(avr32_pm_cpumask_t)); + // Write + *regptr = regvalue; + AVR32_LEAVE_CRITICAL_REGION( ); + + return PASS; +} + + + +/** + ** Sleep Functions + **/ +// Implemented as inline in pm_uc3c.h + + + +/** + ** Reset Functions + **/ +// Implemented as inline in pm_uc3c.h + + + +/** + ** Interrupt Functions + **/ +// Implemented as inline in pm_uc3c.h + + + +/** + ** Misc Functions + **/ +// Implemented as inline in pm_uc3c.h diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/pm_uc3c.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/pm_uc3c.h new file mode 100644 index 0000000..c01d382 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/pm_uc3c.h @@ -0,0 +1,392 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Power Manager(PM) driver interface. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 UC3C devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ +#ifndef _PM_UC3C_H_ +#define _PM_UC3C_H_ + +#define _PM_UC3C_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "compiler.h" + +// These defines are missing from or wrong in the toolchain header file ip_xxx.h or part.h +#ifdef AVR32_PM_410_H_INCLUDED +// Optionnal #undef AVR32_PM_UNLOCK_KEY_VALUE if the define values is wrong. +#define AVR32_PM_UNLOCK_KEY_VALUE 0x000000AA +#endif + +//! Device-specific data + +//! The clock sources of the power manager. +typedef enum +{ + PM_CLK_SRC_SLOW = AVR32_PM_MCSEL_SLOW, + PM_CLK_SRC_OSC0 = AVR32_PM_MCSEL_OSC0, + PM_CLK_SRC_OSC1 = AVR32_PM_MCSEL_OSC1, + PM_CLK_SRC_PLL0 = AVR32_PM_MCSEL_PLL0, + PM_CLK_SRC_PLL1 = AVR32_PM_MCSEL_PLL1, + PM_CLK_SRC_RC8M = AVR32_PM_MCSEL_RCOSC8, + PM_CLK_SRC_RCRIPOSC = AVR32_PM_MCSEL_CRIPOSC, + PM_CLK_SRC_RC120M = AVR32_PM_MCSEL_RC120M, + PM_CLK_SRC_INVALID +} pm_clk_src_t; + +//! The clock domains of the power manager. +typedef enum +{ + PM_CLK_DOMAIN_0 = AVR32_PM_CLK_GRP_CPU, + PM_CLK_DOMAIN_1 = AVR32_PM_CLK_GRP_HSB, + PM_CLK_DOMAIN_2 = AVR32_PM_CLK_GRP_PBA, + PM_CLK_DOMAIN_3 = AVR32_PM_CLK_GRP_PBB, + PM_CLK_DOMAIN_4 = AVR32_PM_CLK_GRP_PBC, + PM_CLK_DOMAIN_INVALID +} pm_clk_domain_t; + + +//! The possible synchronous clock division ratio. +typedef enum +{ + PM_CKSEL_DIVRATIO_2 = 0, // Divide the main clock by 2^1 + PM_CKSEL_DIVRATIO_4, // Divide the main clock by 2^2 + PM_CKSEL_DIVRATIO_8, // Divide the main clock by 2^3 + PM_CKSEL_DIVRATIO_16, // Divide the main clock by 2^4 + PM_CKSEL_DIVRATIO_32, // Divide the main clock by 2^5 + PM_CKSEL_DIVRATIO_64, // Divide the main clock by 2^6 + PM_CKSEL_DIVRATIO_128, // Divide the main clock by 2^7 + PM_CKSEL_DIVRATIO_256 // Divide the main clock by 2^8 +} pm_divratio_t; + +//! The timeguard used for polling (expressed in ticks). +#define PM_POLL_TIMEOUT 100000 + +//! Define "not supported" for the power manager features. +#define PM_NOT_SUPPORTED (-10000) + + +//! Unlock PM register macro +#define PM_UNLOCK(reg) (AVR32_PM.unlock = (unsigned long)(AVR32_PM_UNLOCK_KEY_VALUE << AVR32_PM_UNLOCK_KEY_OFFSET)|(reg)) + + +/*! \name Clock Functions + */ +//! @{ + +/*! \brief Set the main clock. + * + * \param src The clock to use as the main clock. + * + * \warning The input clock to use as the main clock must be enabled before calling + * this function, otherwise a deadlock will occur. + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured when trying to set the main clock. + */ +extern long pm_set_mclk_source(pm_clk_src_t src); + +/*! \brief Configure the main clock safety mechanisms. + * + * \note Refer to the section Clock Failure Detector of the PM chapter in the datasheet + * + * \warning The Critical Path Oscillator (CRIPOSC) must be enabled before + * enabling the Over Clock Protection mechanism. + * + * \param cfd Enable/disable the Clock Failure Detection mechanism + * \param final If true, make this configuration definitive + * + * \return Status. + * \retval =0 Success. + * \retval <0 An error occured. + */ +extern long pm_config_mainclk_safety(bool cfd, bool final); + +/*! \brief Set the division ratio for a clock domain. + * + * \param clock_domain The clock domain to alter. + * \param divratio The division ratio to set. + * + * \warning Care should be taken that each new frequency of the synchronous clocks + * does not exceed the maximum frequency for each clock domain. + * + * \return Status. + * \retval =0 Success. + * \retval <0 An error occured. + */ +extern long pm_set_clk_domain_div(pm_clk_domain_t clock_domain, pm_divratio_t divratio); + +/*! \brief Disable the division ratio for a clock domain. + * + * \param clock_domain The clock domain to alter. + * + * \warning Care should be taken that each new frequency of the synchronous clocks + * does not exceed the maximum frequency for each clock domain. + * + * \return Status. + * \retval =0 Success. + * \retval <0 An error occured. + */ +extern long pm_disable_clk_domain_div(pm_clk_domain_t clock_domain); + +/*! \brief Wait actively for the clock settings to be effective. + * + * \note To avoid an infinite loop, this function checks the clock ready flag + * PM_POLL_TIMEOUT times. + * + * \return Status. + * \retval 0 Success. + * \retval <0 Unable to reach a clock ready status within the polling limit. + */ +extern long pm_wait_for_clk_ready(void); + +//! @} + + +/*! \name Module Functions + */ +//! @{ + +/*! \brief Enable the clock of a module. + * + * \param module The module to clock (use one of the defines in the part-specific + * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the + * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks") + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured. + */ +extern long pm_enable_module(unsigned long module); + +/*! \brief Disable the clock of a module. + * + * \param module The module to shut down (use one of the defines in the part-specific + * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the + * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks") + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured. + */ +extern long pm_disable_module(unsigned long module); + + +//! @} + +/*! \name Sleep Functions + */ +//! @{ + +/*! \brief Sets the MCU in the specified sleep mode + * + * \note Precautions should be taken before entering sleep mode. Refer to the + * datasheet chapter 'Power Manager'. + * + * \param sleep_mode The sleep mode index + */ +#define SLEEP(sleep_mode) {__asm__ __volatile__ ("sleep "STRINGZ(sleep_mode));} + +/*! \brief Returns MCU wake cause + * + * \return The MCU wake cause which can be masked with the + * \c AVR32_PM_WCAUSE_x_MASK bit-masks to isolate specific causes. + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline unsigned long pm_get_wake_cause(void) +{ + return AVR32_PM.wcause; +} + +/*! \brief Enable one or several asynchronous wake-up source. + * + * \param awen_mask Mask of asynchronous wake-up sources (use one of the defines + * AVR32_PM_AWEN_xxxxWEN_MASK in the part-specific header file under + * "toolchain folder"/avr32/inc(lude)/avr32/) + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void pm_asyn_wake_up_enable(unsigned long awen_mask) +{ + AVR32_PM.awen |= awen_mask; +} + +/*! \brief Disable one or several asynchronous wake-up sources + * + * \param awen_mask Mask of asynchronous wake-up sources (use one of the defines + * AVR32_PM_AWEN_xxxxWEN_MASK in the part-specific header file under + * "toolchain folder"/avr32/inc(lude)/avr32/) + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void pm_asyn_wake_up_disable(unsigned long awen_mask) +{ + AVR32_PM.awen &= ~awen_mask; +} + +//! @} + + + +/*! \name Reset Functions + */ +//! @{ + +/*! \brief Returns MCU last reset cause + * + * \return The MCU last reset cause which can be masked with the + * \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes. + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline unsigned long pm_get_reset_cause(void) +{ + return AVR32_PM.rcause; +} + +//! @} + + + +/*! \name Interrupt Functions + */ +//! @{ + +/*! \brief Enable power manager interrupts. + * + * \param mask the interrupts to enable. + * + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void pm_enable_interrupts(unsigned long mask) +{ + AVR32_PM.ier |= mask; +} + +/*! \brief Disable power manager interrupts. + * + * \param mask the interrupts to disable. + * + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void pm_disable_interrupts(unsigned long mask) +{ + AVR32_PM.idr |= mask; +} + +/*! \brief Read the enabled power manager interrupts. + * + * \return mask of the enabled interrupts. + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline unsigned long pm_get_enabled_interrupts(void) +{ + return(AVR32_PM.imr); +} + +/*! \brief Read the interrupts status of the power manager. + * + * \return mask of the interrupts that have been triggered. + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline unsigned long pm_get_interrupts_status(void) +{ + return(AVR32_PM.isr); +} + +/*! \brief Clear raised interrupts from the power manager. + * + * \param mask The interrupts to clear. + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void pm_clear_interrupt_status(unsigned long mask) +{ + AVR32_PM.icr |= mask; +} + +//! @} + + + +/*! \name Misc Functions + */ +//! @{ + +/*! \brief Get the PM status + * + * \return The content of the PM Status register. + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline unsigned long pm_get_status(void) +{ + return AVR32_PM.sr; +} + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif // _PM_UC3C_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/power_clocks_lib.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/power_clocks_lib.c new file mode 100644 index 0000000..af71e60 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/power_clocks_lib.c @@ -0,0 +1,575 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief High-level library abstracting features such as oscillators/pll/dfll + * configuration, clock configuration, System-sensible parameters + * configuration, buses clocks configuration, sleep mode, reset. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ +#include "power_clocks_lib.h" + + +//! Device-specific data +#if UC3L +static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param); // FORWARD declaration +#endif + +#if UC3C +static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param); // FORWARD declaration +#endif + +long int pcl_configure_clocks(pcl_freq_param_t *param) +{ +#ifndef AVR32_PM_VERSION_RESETVALUE + // Implementation for UC3A, UC3A3, UC3B parts. + return(pm_configure_clocks(param)); +#else + #if (defined AVR32_PM_410_H_INCLUDED ) || (defined AVR32_PM_412_H_INCLUDED ) + // Implementation for UC3C parts. + return(pcl_configure_clocks_uc3c(param)); + #else + // Implementation for UC3L parts. + return(pcl_configure_clocks_uc3l(param)); + #endif +#endif +} + + +//! Device-specific implementation +#if UC3L +// FORWARD declaration +static long int pcl_configure_synchronous_clocks( pm_clk_src_t main_clk_src, + unsigned long main_clock_freq_hz, + pcl_freq_param_t *param); + +long int pcl_configure_clocks_rcsys(pcl_freq_param_t *param) +{ + // Supported main clock sources: PCL_MC_RCSYS + + // Supported synchronous clocks frequencies if RCSYS is the main clock source: + // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz. + + // NOTE: by default, this implementation doesn't perform thorough checks on the + // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + +#ifdef AVR32SFW_INPUT_CHECK + // Verify that fCPU >= fPBx + if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f)) + return(-1); +#endif + +#ifdef AVR32SFW_INPUT_CHECK + // Verify that the target frequencies are reachable. + if((param->cpu_f > SCIF_SLOWCLOCK_FREQ_HZ) || (param->pba_f > SCIF_SLOWCLOCK_FREQ_HZ) + || (param->pbb_f > SCIF_SLOWCLOCK_FREQ_HZ)) + return(-1); +#endif + + return(pcl_configure_synchronous_clocks(PM_CLK_SRC_SLOW, SCIF_SLOWCLOCK_FREQ_HZ, param)); +} + + +long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param) +{ + // Supported main clock sources: PCL_MC_RC120M + + // Supported synchronous clocks frequencies if RC120M is the main clock source: + // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz. + + // NOTE: by default, this implementation doesn't perform thorough checks on the + // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + +#ifdef AVR32SFW_INPUT_CHECK + // Verify that fCPU >= fPBx + if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f)) + return(-1); +#endif + +#ifdef AVR32SFW_INPUT_CHECK + // Verify that the target frequencies are reachable. + if((param->cpu_f > SCIF_RC120M_FREQ_HZ) || (param->pba_f > SCIF_RC120M_FREQ_HZ) + || (param->pbb_f > SCIF_RC120M_FREQ_HZ)) + return(-1); +#endif + + // Start the 120MHz internal RCosc (RC120M) clock + scif_start_rc120M(); + + return(pcl_configure_synchronous_clocks(PM_CLK_SRC_RC120M, SCIF_RC120M_FREQ_HZ, param)); +} + + +long int pcl_configure_clocks_osc0(pcl_freq_param_t *param) +{ + // Supported main clock sources: PCL_MC_OSC0 + + // Supported synchronous clocks frequencies if OSC0 is the main clock source: + // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example) + // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz. + + // NOTE: by default, this implementation doesn't perform thorough checks on the + // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + + unsigned long main_clock_freq; + + +#ifdef AVR32SFW_INPUT_CHECK + // Verify that fCPU >= fPBx + if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f)) + return(-1); +#endif + + main_clock_freq = param->osc0_f; +#ifdef AVR32SFW_INPUT_CHECK + // Verify that the target frequencies are reachable. + if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq) + || (param->pbb_f > main_clock_freq)) + return(-1); +#endif + // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency. + scif_configure_osc_crystalmode(SCIF_OSC0, main_clock_freq); + // Enable the OSC0 + scif_enable_osc(SCIF_OSC0, param->osc0_startup, true); + + return(pcl_configure_synchronous_clocks(PM_CLK_SRC_OSC0, main_clock_freq, param)); +} + + +long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param) +{ + // Supported main clock sources: PCL_MC_DFLL + + // Supported synchronous clocks frequencies if DFLL is the main clock source: + // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example) + // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz. + + // NOTE: by default, this implementation doesn't perform thorough checks on the + // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + + unsigned long main_clock_freq; + scif_gclk_opt_t *pgc_dfllif_ref_opt; + + +#ifdef AVR32SFW_INPUT_CHECK + // Verify that fCPU >= fPBx + if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f)) + return(-1); +#endif + + main_clock_freq = param->dfll_f; +#ifdef AVR32SFW_INPUT_CHECK + // Verify that the target DFLL output frequency is in the correct range. + if((main_clock_freq > SCIF_DFLL_MAXFREQ_HZ) || (main_clock_freq < SCIF_DFLL_MINFREQ_HZ)) + return(-1); + // Verify that the target frequencies are reachable. + if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq) + || (param->pbb_f > main_clock_freq)) + return(-1); +#endif + pgc_dfllif_ref_opt = (scif_gclk_opt_t *)param->pextra_params; + // Implementation note: this implementation configures the DFLL in closed-loop + // mode (because it gives the best accuracy) which enables the generic clock CLK_DFLLIF_REF + // as a reference (RCSYS being used as the generic clock source, undivided). + scif_dfll0_closedloop_configure_and_start(pgc_dfllif_ref_opt, main_clock_freq, true); + + return(pcl_configure_synchronous_clocks(PM_CLK_SRC_DFLL0, main_clock_freq, param)); +} + + +static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param) +{ + // Supported main clock sources: PCL_MC_RCSYS, PCL_MC_OSC0, PCL_MC_DFLL0, PCL_MC_RC120M + + // Supported synchronous clocks frequencies if RCSYS is the main clock source: + // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz. + + // Supported synchronous clocks frequencies if RC120M is the main clock source: + // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz. + + // Supported synchronous clocks frequencies if OSC0 is the main clock source: + // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example) + // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz. + + // Supported synchronous clocks frequencies if DFLL is the main clock source: + // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example) + // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz. + + // NOTE: by default, this implementation doesn't perform thorough checks on the + // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + + +#ifdef AVR32SFW_INPUT_CHECK + // Verify that fCPU >= fPBx + if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f)) + return(-1); +#endif + + if(PCL_MC_RCSYS == param->main_clk_src) + { + return(pcl_configure_clocks_rcsys(param)); + } + else if(PCL_MC_RC120M == param->main_clk_src) + { + return(pcl_configure_clocks_rc120m(param)); + } + else if(PCL_MC_OSC0 == param->main_clk_src) + { + return(pcl_configure_clocks_osc0(param)); + } + else // PCL_MC_DFLL0 == param->main_clk_src + { + return(pcl_configure_clocks_dfll0(param)); + } +} + +static long int pcl_configure_synchronous_clocks(pm_clk_src_t main_clk_src, unsigned long main_clock_freq_hz, pcl_freq_param_t *param) +{ + //# + //# Set the Synchronous clock division ratio for each clock domain + //# + pm_set_all_cksel(main_clock_freq_hz, param->cpu_f, param->pba_f, param->pbb_f); + + //# + //# Set the Flash wait state and the speed read mode (depending on the target CPU frequency). + //# +#if UC3L + flashcdw_set_flash_waitstate_and_readmode(param->cpu_f); +#elif UC3C + flashc_set_flash_waitstate_and_readmode(param->cpu_f); +#endif + + + //# + //# Switch the main clock source to the selected clock. + //# + pm_set_mclk_source(main_clk_src); + + return PASS; +} + +#endif // UC3L device-specific implementation + +//! UC3C Device-specific implementation +#if UC3C +static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param) +{ + #define PM_MAX_MUL ((1 << AVR32_SCIF_PLLMUL_SIZE) - 1) + #define AVR32_PM_PBA_MAX_FREQ 66000000 + #define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ 240000000 + #define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ 160000000 + + // Implementation for UC3C parts. + // Supported frequencies: + // Fosc0 mul div PLL div2_en cpu_f pba_f Comment + // 12 15 1 192 1 12 12 + // 12 9 3 40 1 20 20 PLL out of spec + // 12 15 1 192 1 24 12 + // 12 9 1 120 1 30 15 + // 12 9 3 40 0 40 20 PLL out of spec + // 12 15 1 192 1 48 12 + // 12 15 1 192 1 48 24 + // 12 8 1 108 1 54 27 + // 12 9 1 120 1 60 15 + // 12 9 1 120 1 60 30 + // 12 10 1 132 1 66 16.5 + // + unsigned long in_cpu_f = param->cpu_f; + unsigned long in_osc0_f = param->osc0_f; + unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0; + unsigned long pll_freq, rest; + bool b_div2_pba, b_div2_cpu; + + // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency. + scif_configure_osc_crystalmode(SCIF_OSC0, in_osc0_f); + // Enable the OSC0 + scif_enable_osc(SCIF_OSC0, param->osc0_startup, true); + // Set the main clock source as being OSC0. + pm_set_mclk_source(PM_CLK_SRC_OSC0); + + // Start with CPU freq config + if (in_cpu_f == in_osc0_f) + { + param->cpu_f = in_osc0_f; + param->pba_f = in_osc0_f; + return PASS; + } + else if (in_cpu_f < in_osc0_f) + { + // TBD + } + + rest = in_cpu_f % in_osc0_f; + + for (div = 1; div < 32; div++) + { + if ((div * rest) % in_osc0_f == 0) + break; + } + if (div == 32) + return FAIL; + + mul = (in_cpu_f * div) / in_osc0_f; + + if (mul > PM_MAX_MUL) + return FAIL; + + // export 2power from PLL div to div2_cpu + while (!(div % 2)) + { + div /= 2; + div2_cpu++; + } + + // Here we know the mul and div parameter of the PLL config. + // . Check out if the PLL has a valid in_cpu_f. + // . Try to have for the PLL frequency (VCO output) the highest possible value + // to reduce jitter. + while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ) + { + if (2 * mul > PM_MAX_MUL) + break; + mul *= 2; + div2_cpu++; + } + + if (div2_cpu != 0) + { + div2_cpu--; + div2_en = 1; + } + + pll_freq = in_osc0_f * mul / (div * (1 << div2_en)); + + // Update real CPU Frequency + param->cpu_f = pll_freq / (1 << div2_cpu); + mul--; + + scif_pll_opt_t opt; + + opt.osc = SCIF_OSC0, // Sel Osc0 or Osc1 + opt.lockcount = 16, // lockcount in main clock for the PLL wait lock + opt.div = div, // DIV=1 in the formula + opt.mul = mul, // MUL=7 in the formula + opt.pll_div2 = div2_en, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value) + opt.pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. + opt.pll_freq = (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. + + + scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock + + /* Enable PLL0 */ + scif_pll_enable(SCIF_PLL0); + + /* Wait for PLL0 locked */ + scif_wait_for_pll_locked(SCIF_PLL0) ; + + rest = pll_freq; + while (rest > AVR32_PM_PBA_MAX_FREQ || + rest != param->pba_f) + { + div2_pba++; + rest = pll_freq / (1 << div2_pba); + if (rest < param->pba_f) + break; + } + + // Update real PBA Frequency + param->pba_f = pll_freq / (1 << div2_pba); + + + if (div2_cpu) + { + b_div2_cpu = true; + div2_cpu--; + } + else + b_div2_cpu = false; + + if (div2_pba) + { + b_div2_pba = true; + div2_pba--; + } + else + b_div2_pba = false; + + if (b_div2_cpu == true ) + { + pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) div2_cpu); // CPU + pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) div2_cpu); // HSB + pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) div2_cpu); // PBB + } + if (b_div2_pba == true ) + { + pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) div2_pba); // PBA + pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) div2_pba); // PBC + } + + // Set Flashc Wait State + flashc_set_flash_waitstate_and_readmode(param->cpu_f); + + // Set the main clock source as being PLL0. + pm_set_mclk_source(PM_CLK_SRC_PLL0); + + return PASS; +} +#endif // UC3C device-specific implementation + +long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup) +{ +#ifndef AVR32_PM_VERSION_RESETVALUE +// Implementation for UC3A, UC3A3, UC3B parts. + if(PCL_OSC0 == osc) + { + // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency, + // enable the OSC0, set the main clock source as being OSC0. + pm_switch_to_osc0(&AVR32_PM, fcrystal, startup); + } + else + { + return PCL_NOT_SUPPORTED; + } +#else +// Implementation for UC3C, UC3L parts. + #if AVR32_PM_VERSION_RESETVALUE < 0x400 + return PCL_NOT_SUPPORTED; + #else + if(PCL_OSC0 == osc) + { + // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency. + scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal); + // Enable the OSC0 + scif_enable_osc(SCIF_OSC0, startup, true); + // Set the Flash wait state and the speed read mode (depending on the target CPU frequency). +#if UC3L + flashcdw_set_flash_waitstate_and_readmode(fcrystal); +#elif UC3C + flashc_set_flash_waitstate_and_readmode(fcrystal); +#endif + // Set the main clock source as being OSC0. + pm_set_mclk_source(PM_CLK_SRC_OSC0); + } + else + { + return PCL_NOT_SUPPORTED; + } + #endif +#endif + return PASS; +} + +long int pcl_configure_usb_clock(void) +{ +#ifndef AVR32_PM_VERSION_RESETVALUE +// Implementation for UC3A, UC3A3, UC3B parts. + pm_configure_usb_clock(); + return PASS; +#else + #if UC3C + const scif_pll_opt_t opt = { + .osc = SCIF_OSC0, // Sel Osc0 or Osc1 + .lockcount = 16, // lockcount in main clock for the PLL wait lock + .div = 1, // DIV=1 in the formula + .mul = 5, // MUL=7 in the formula + .pll_div2 = 1, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value) + .pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. + .pll_freq = 1, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. + }; + + /* Setup PLL1 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 16Mhzx6 = 96MHz output */ + scif_pll_setup(SCIF_PLL1, opt); // lockcount in main clock for the PLL wait lock + + /* Enable PLL1 */ + scif_pll_enable(SCIF_PLL1); + + /* Wait for PLL1 locked */ + scif_wait_for_pll_locked(SCIF_PLL1) ; + + // Implementation for UC3C parts. + // Setup the generic clock for USB + scif_gc_setup( +#if (defined AVR32_USBB) + AVR32_SCIF_GCLK_USB, +#else + AVR32_SCIF_GCLK_USBC, +#endif + SCIF_GCCTRL_PLL1, + AVR32_SCIF_GC_NO_DIV_CLOCK, + 0); + // Now enable the generic clock + scif_gc_enable( +#if (defined AVR32_USBB) + AVR32_SCIF_GCLK_USB +#else + AVR32_SCIF_GCLK_USBC +#endif + ); + return PASS; + #else + return PCL_NOT_SUPPORTED; + #endif +#endif +} + + +#if UC3L +#else +void pcl_write_gplp(unsigned long gplp, unsigned long value) +{ +#ifndef AVR32_PM_VERSION_RESETVALUE +// Implementation for UC3A, UC3A3, UC3B parts. + pm_write_gplp(&AVR32_PM,gplp,value); +#else + scif_write_gplp(gplp,value); +#endif +} + +unsigned long pcl_read_gplp(unsigned long gplp) +{ +#ifndef AVR32_PM_VERSION_RESETVALUE +// Implementation for UC3A, UC3A3, UC3B parts. + return pm_read_gplp(&AVR32_PM,gplp); +#else + return scif_read_gplp(gplp); +#endif +} +#endif diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/power_clocks_lib.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/power_clocks_lib.h new file mode 100644 index 0000000..f661873 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/power_clocks_lib.h @@ -0,0 +1,381 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief High-level library abstracting features such as oscillators/pll/dfll + * configuration, clock configuration, System-sensible parameters + * configuration, buses clocks configuration, sleep mode, reset. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _POWER_CLOCKS_LIB_H_ +#define _POWER_CLOCKS_LIB_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "compiler.h" + +#ifndef AVR32_PM_VERSION_RESETVALUE +// Support for UC3A, UC3A3, UC3B parts. + #include "pm.h" +#else +//! Device-specific data +#if UC3L + #include "pm_uc3l.h" + #include "scif_uc3l.h" + #include "flashcdw.h" +#elif UC3C + #include "pm_uc3c.h" + #include "scif_uc3c.h" + #include "flashc.h" +#elif UC3D + #include "pm_uc3d.h" + #include "scif_uc3d.h" + #include "flashcdw.h" +#endif + #endif + +/*! \name Clocks Management + */ +//! @{ + +//! The different oscillators +typedef enum +{ + PCL_OSC0 = 0, + PCL_OSC1 = 1 +} pcl_osc_t; + +//! The different DFLLs +typedef enum +{ + PCL_DFLL0 = 0, + PCL_DFLL1 = 1 +} pcl_dfll_t; + +//! Possible Main Clock Sources +typedef enum +{ + PCL_MC_RCSYS, // Default main clock source, supported by all (aka Slow Clock) + PCL_MC_OSC0, // Supported by all + PCL_MC_OSC1, // Supported by UC3C only + PCL_MC_OSC0_PLL0, // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC0 as reference) + PCL_MC_OSC1_PLL0, // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC1 as reference) + PCL_MC_OSC0_PLL1, // Supported by UC3C (the main clock source is PLL1 with OSC0 as reference) + PCL_MC_OSC1_PLL1, // Supported by UC3C (the main clock source is PLL1 with OSC1 as reference) + PCL_MC_DFLL0, // Supported by UC3L + PCL_MC_DFLL1, // Not supported yet + PCL_MC_RC120M, // Supported by UC3L, UC3C + PCL_MC_RC8M, // Supported by UC3C + PCL_MC_CRIPOSC // Supported by UC3C +} pcl_mainclk_t; + +//! Input and output parameters to configure clocks with pcl_configure_clocks(). +// NOTE: regarding the frequency settings, always abide by the datasheet rules and min & max supported frequencies. +#ifndef AVR32_PM_VERSION_RESETVALUE +// Support for UC3A, UC3A3, UC3B parts. +#define pcl_freq_param_t pm_freq_param_t // See pm.h +#else +// Support for UC3C, UC3L parts. +typedef struct +{ + //! Main clock source selection (input argument). + pcl_mainclk_t main_clk_src; + + //! Target CPU frequency (input/output argument). + unsigned long cpu_f; + + //! Target PBA frequency (input/output argument). + unsigned long pba_f; + + //! Target PBB frequency (input/output argument). + unsigned long pbb_f; + + //! Target PBC frequency (input/output argument). + unsigned long pbc_f; + + //! Oscillator 0's external crystal(or external clock) frequency (board dependant) (input argument). + unsigned long osc0_f; + + //! Oscillator 0's external crystal(or external clock) startup time: AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC (input argument). + unsigned long osc0_startup; + + //! DFLL target frequency (input/output argument) (NOTE: the bigger, the most stable the frequency) + unsigned long dfll_f; + + //! Other parameters that might be necessary depending on the device (implementation-dependent). + // For the UC3L DFLL setup, this parameter should be pointing to a structure of + // type (scif_gclk_opt_t *). + void *pextra_params; +} pcl_freq_param_t; +#endif + +//! Define "not supported" for the lib. +#define PCL_NOT_SUPPORTED (-10000) + +/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks + * + * This function needs some parameters stored in a pcl_freq_param_t structure: + * - main_clk_src is the id of the main clock source to use, + * - cpu_f and pba_f and pbb_f are the wanted frequencies, + * - osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0), + * - osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP). + * - dfll_f is the target DFLL frequency to set-up if main_clk_src is the dfll. + * + * The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f. + * + * \note: since it is dynamically computing the appropriate field values of the + * configuration registers from the parameters structure, this function is not + * optimal in terms of code size. For a code size optimal solution, it is better + * to create a new function from pcl_configure_clocks() and modify it to use + * preprocessor computation from pre-defined target frequencies. + * + * \param param pointer on the configuration structure. + * + * \retval 0 Success. + * \retval <0 The configuration cannot be performed. + */ +extern long int pcl_configure_clocks(pcl_freq_param_t *param); + +/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the RCSYS osc as main source clock. + * + * This function needs some parameters stored in a pcl_freq_param_t structure: + * - cpu_f and pba_f and pbb_f are the wanted frequencies + * + * Supported main clock sources: PCL_MC_RCSYS + * + * Supported synchronous clocks frequencies: + * 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz. + * + * \note: by default, this implementation doesn't perform thorough checks on the + * input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + * + * \note: since it is dynamically computing the appropriate field values of the + * configuration registers from the parameters structure, this function is not + * optimal in terms of code size. For a code size optimal solution, it is better + * to create a new function from pcl_configure_clocks_rcsys() and modify it to use + * preprocessor computation from pre-defined target frequencies. + * + * \param param pointer on the configuration structure. + * + * \retval 0 Success. + * \retval <0 The configuration cannot be performed. + */ +extern long int pcl_configure_clocks_rcsys(pcl_freq_param_t *param); + +/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the RC120M osc as main source clock. + * + * This function needs some parameters stored in a pcl_freq_param_t structure: + * - cpu_f and pba_f and pbb_f are the wanted frequencies + * + * Supported main clock sources: PCL_MC_RC120M + * + * Supported synchronous clocks frequencies: + * 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz. + * + * \note: by default, this implementation doesn't perform thorough checks on the + * input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + * + * \note: since it is dynamically computing the appropriate field values of the + * configuration registers from the parameters structure, this function is not + * optimal in terms of code size. For a code size optimal solution, it is better + * to create a new function from pcl_configure_clocks_rc120m() and modify it to + * use preprocessor computation from pre-defined target frequencies. + * + * \param param pointer on the configuration structure. + * + * \retval 0 Success. + * \retval <0 The configuration cannot be performed. + */ +extern long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param); + +/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the OSC0 osc as main source clock + * + * This function needs some parameters stored in a pcl_freq_param_t structure: + * - cpu_f and pba_f and pbb_f are the wanted frequencies, + * - osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0), + * - osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP). + * + * Supported main clock sources: PCL_MC_OSC0 + * + * Supported synchronous clocks frequencies: + * (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example) + * 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz. + * + * \note: by default, this implementation doesn't perform thorough checks on the + * input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + * + * \note: since it is dynamically computing the appropriate field values of the + * configuration registers from the parameters structure, this function is not + * optimal in terms of code size. For a code size optimal solution, it is better + * to create a new function from pcl_configure_clocks_osc0() and modify it to use + * preprocessor computation from pre-defined target frequencies. + * + * \param param pointer on the configuration structure. + * + * \retval 0 Success. + * \retval <0 The configuration cannot be performed. + */ +extern long int pcl_configure_clocks_osc0(pcl_freq_param_t *param); + +/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the DFLL0 as main source clock + * + * This function needs some parameters stored in a pcl_freq_param_t structure: + * - cpu_f and pba_f and pbb_f are the wanted frequencies, + * - dfll_f is the target DFLL frequency to set-up + * + * \note: when the DFLL0 is to be used as main source clock for the synchronous clocks, + * the target frequency of the DFLL should be chosen to be as high as possible + * within the specification range (for stability reasons); the target cpu and pbx + * frequencies will then be reached by appropriate division ratio. + * + * Supported main clock sources: PCL_MC_DFLL0 + * + * Supported synchronous clocks frequencies: + * (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example) + * 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz. + * + * \note: by default, this implementation doesn't perform thorough checks on the + * input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. + * + * \note: since it is dynamically computing the appropriate field values of the + * configuration registers from the parameters structure, this function is not + * optimal in terms of code size. For a code size optimal solution, it is better + * to create a new function from pcl_configure_clocks_dfll0() and modify it to + * use preprocessor computation from pre-defined target frequencies. + * + * \param param pointer on the configuration structure. + * + * \retval 0 Success. + * \retval <0 The configuration cannot be performed. + */ +extern long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param); + +/*! \brief Switch the main clock source to Osc0 configured in crystal mode + * + * \param osc The oscillator to enable and switch to. + * \param fcrystal Oscillator external crystal frequency (Hz) + * \param startup Oscillator startup time. + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured. + */ +extern long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup); + +/*! \brief Enable the clock of a module. + * + * \param module The module to clock (use one of the defines in the part-specific + * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the + * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks" + * or look in the module section). + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured. + */ +#ifndef AVR32_PM_VERSION_RESETVALUE +// Implementation for UC3A, UC3A3, UC3B parts. +#define pcl_enable_module(module) pm_enable_module(&AVR32_PM, module) +#else +// Implementation for UC3C, UC3L parts. +#define pcl_enable_module(module) pm_enable_module(module) +#endif + +/*! \brief Disable the clock of a module. + * + * \param module The module to shut down (use one of the defines in the part-specific + * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the + * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks" + * or look in the module section). + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured. + */ +#ifndef AVR32_PM_VERSION_RESETVALUE +// Implementation for UC3A, UC3A3, UC3B parts. +#define pcl_disable_module(module) pm_disable_module(&AVR32_PM, module) +#else +// Implementation for UC3C, UC3L parts. +#define pcl_disable_module(module) pm_disable_module(module) +#endif + +/*! \brief Configure the USB Clock + * + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured. + */ +extern long int pcl_configure_usb_clock(void); + +//! @} + +/*! \name Power Management + */ +//! @{ +/*! + * \brief Read the content of the GPLP registers + * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part) + * + * \return The content of the chosen GPLP register. + */ +extern unsigned long pcl_read_gplp(unsigned long gplp); + + +/*! + * \brief Write into the GPLP registers + * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part) + * \param value Value to write + */ +extern void pcl_write_gplp(unsigned long gplp, unsigned long value); + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif // _POWER_CLOCKS_LIB_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/sleep.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/sleep.h new file mode 100644 index 0000000..7be961c --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/pm/sleep.h @@ -0,0 +1,149 @@ +/** + * \file + * + * \brief Sleep mode access + * + * Copyright (C) 2010 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#ifndef SLEEP_H +#define SLEEP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifndef AVR32_PM_SMODE_GMCLEAR_MASK +#define AVR32_PM_SMODE_GMCLEAR_MASK 0x80 +#else +#warning Define already present in the system toolchain header files! +#endif + +/** + * \defgroup sleep_group Power Manager (PM) + * + * This is a stub on the AVR UC3 Power Manager(PM) for the sleepmgr service. + * + * \note To minimize the code overhead, these functions do not feature + * interrupt-protected access since they are likely to be called inside + * interrupt handlers or in applications where such protection is not + * necessary. If such protection is needed, it must be ensured by the calling + * code. + * + * @{ + */ + +#if defined(__DOXYGEN__) +/** + * \brief Sets the MCU in the specified sleep mode + * \param sleep_mode Sleep mode to set. + */ +#endif + +#if (UC3A || UC3B) // For AVR UC3 A0/A1, UC3 B, UC3 A3 series + +# ifndef AVR32_PM_SMODE_DEEPSTOP +# define AVR32_PM_SMODE_DEEPSTOP 0x00000004 +# endif +# include "pm.h" +#elif UC3C // For AVR UC3 C series +# include "pm_uc3c.h" +#elif UC3D // For AVR UC3 D series +# include "pm_uc3d.h" +#elif UC3L // For AVR UC3 L series +# include "pm_uc3l.h" +#else +# error Unsupported AVR UC3 series. +#endif + +static inline void pm_sleep(int sleep_mode) +{ + switch (sleep_mode) { + case AVR32_PM_SMODE_IDLE: + SLEEP(AVR32_PM_SMODE_IDLE); + break; + case AVR32_PM_SMODE_GMCLEAR_MASK | AVR32_PM_SMODE_IDLE: + SLEEP(AVR32_PM_SMODE_GMCLEAR_MASK | AVR32_PM_SMODE_IDLE); + break; + case AVR32_PM_SMODE_FROZEN: + SLEEP(AVR32_PM_SMODE_FROZEN); + break; + case AVR32_PM_SMODE_GMCLEAR_MASK | AVR32_PM_SMODE_FROZEN: + SLEEP(AVR32_PM_SMODE_GMCLEAR_MASK | AVR32_PM_SMODE_FROZEN); + break; + case AVR32_PM_SMODE_STANDBY: + SLEEP(AVR32_PM_SMODE_STANDBY); + break; + case AVR32_PM_SMODE_GMCLEAR_MASK | AVR32_PM_SMODE_STANDBY: + SLEEP(AVR32_PM_SMODE_GMCLEAR_MASK | AVR32_PM_SMODE_STANDBY); + break; + case AVR32_PM_SMODE_STOP: + SLEEP(AVR32_PM_SMODE_STOP); + break; + case AVR32_PM_SMODE_GMCLEAR_MASK | AVR32_PM_SMODE_STOP: + SLEEP(AVR32_PM_SMODE_GMCLEAR_MASK | AVR32_PM_SMODE_STOP); + break; + case AVR32_PM_SMODE_DEEPSTOP: + SLEEP(AVR32_PM_SMODE_DEEPSTOP); + break; + case AVR32_PM_SMODE_GMCLEAR_MASK | AVR32_PM_SMODE_DEEPSTOP: + SLEEP(AVR32_PM_SMODE_GMCLEAR_MASK | AVR32_PM_SMODE_DEEPSTOP); + break; + case AVR32_PM_SMODE_STATIC: + SLEEP(AVR32_PM_SMODE_STATIC); + break; + case AVR32_PM_SMODE_GMCLEAR_MASK | AVR32_PM_SMODE_STATIC: + SLEEP(AVR32_PM_SMODE_GMCLEAR_MASK | AVR32_PM_SMODE_STATIC); + break; +#if UC3L + case AVR32_PM_SMODE_SHUTDOWN: + SLEEP(AVR32_PM_SMODE_SHUTDOWN); + break; + case AVR32_PM_SMODE_GMCLEAR_MASK | AVR32_PM_SMODE_SHUTDOWN: + SLEEP(AVR32_PM_SMODE_GMCLEAR_MASK | AVR32_PM_SMODE_SHUTDOWN); + break; +#endif + default: + break; + } +} + + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif /* SLEEP_H */ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/scif/scif_uc3c.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/scif/scif_uc3c.c new file mode 100644 index 0000000..d43719d --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/scif/scif_uc3c.c @@ -0,0 +1,784 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief System Control InterFace(SCIF) driver. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 UC3C devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include "compiler.h" +#include "scif_uc3c.h" + + +/*! \name SCIF Writable Bit-Field Registers + */ +//! @{ + +typedef union +{ + unsigned long oscctrl[2]; + avr32_scif_oscctrl_t OSCCTRL[2]; +} u_avr32_scif_oscctrl_t; + +typedef union +{ + unsigned long pll[2]; + avr32_scif_pll_t PLL[2]; +} u_avr32_scif_pll_t; + +typedef union +{ + unsigned long oscctrl32; + avr32_scif_oscctrl32_t OSCCTRL32; +} u_avr32_scif_oscctrl32_t; + + + +//! @} + + +//----- PRIVATE FUNCTIONS + +/*! \brief Wait for a status high in the Power and Clocks status register. + * + * \param statusMask Mask field of the status to poll [INPUT] + * + * \return Status. + * \retval 0 Status is high. + * \retval <0 SCIF_POLL_TIMEOUT Timeout expired before the status was high. + */ +static long int scif_pclksr_statushigh_wait(unsigned long statusMask) +{ + unsigned int timeout = SCIF_POLL_TIMEOUT; + + while(!(AVR32_SCIF.pclksr & statusMask)) + { + if(--timeout == 0) + return -1; + } + return PASS; +} + +unsigned long scif_read_gplp(unsigned long gplp) +{ + return AVR32_SCIF.gplp[gplp]; +} + + +void scif_write_gplp(int gplp, unsigned long value) +{ + SCIF_UNLOCK(AVR32_SCIF_GPLP + 4*gplp); + AVR32_SCIF.gplp[gplp] = value; +} + +/** + ** Interrupt Functions + **/ +// Implemented as inline in scif_uc3x.h + + +/** + ** Power and Clocks Status Functions + **/ +// Implemented as inline in scif_uc3x.h + + +/** + ** OSC0/OSC1 Functions + **/ + +long int scif_start_osc(scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready) +{ + u_avr32_scif_oscctrl_t u_avr32_scif_oscctrl; + +#ifdef AVR32SFW_INPUT_CHECK + // Check that the input frequency is in the supported frequency range. + if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ) + || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ)) + { + return -1; + } + // Check : for OSC0/OSC1, only 2 modes are supported + if( (opt->mode != SCIF_OSC_MODE_EXT_CLK) + && (opt->mode != SCIF_OSC_MODE_2PIN_CRYSTAL)) + { + return -1; + } + + if (osc == SCIF_OSC0) + { + // Check that the startup value is in the supported range. + if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC) + { + return -1; + } + // Check that the gain value is in the supported range. + if(opt->gain > AVR32_SCIF_OSCCTRL0_GAIN_G3) + { + return -1; + } + } + else + { + // Check that the startup value is in the supported range. + if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL1_STARTUP_16384_RCOSC) + { + return -1; + } + // Check that the gain value is in the supported range. + if(opt->gain > AVR32_SCIF_OSCCTRL1_GAIN_G3) + { + return -1; + } + } +#endif // AVR32SFW_INPUT_CHECK + // Read Register + u_avr32_scif_oscctrl.OSCCTRL[osc] = AVR32_SCIF.OSCCTRL[osc] ; + // Modify: Configure & start OSC0. + u_avr32_scif_oscctrl.OSCCTRL[osc].mode = opt->mode; + u_avr32_scif_oscctrl.OSCCTRL[osc].gain = opt->gain; + u_avr32_scif_oscctrl.OSCCTRL[osc].startup = opt->startup; + u_avr32_scif_oscctrl.OSCCTRL[osc].oscen = ENABLE; + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected OSCCTRL0 register + SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc); + // Write Back + AVR32_SCIF.OSCCTRL[osc] = u_avr32_scif_oscctrl.OSCCTRL[osc]; + AVR32_LEAVE_CRITICAL_REGION( ); + + if(true == wait_for_ready) + { + // Wait until OSC0 is stable and ready to be used. + if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK)) + return -1; + } + return PASS; +} + + +bool scif_is_osc_ready(scif_osc_t osc) +{ + if (osc == SCIF_OSC0) + { + return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC0RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC0RDY_OFFSET); + } + else + { + return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC1RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC1RDY_OFFSET); + } +} + + +long int scif_stop_osc(scif_osc_t osc) +{ + + unsigned long temp; + + temp = AVR32_SCIF.oscctrl[osc]; + temp &= ~AVR32_SCIF_OSCCTRL_OSCEN_MASK; + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected OSCCTRL0 register + SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc); + // Stop OSC0. + AVR32_SCIF.oscctrl[osc] = temp; + AVR32_LEAVE_CRITICAL_REGION( ); + + return PASS; +} + + +long int scif_configure_osc_crystalmode(scif_osc_t osc, unsigned int fcrystal) +{ + u_avr32_scif_oscctrl_t u_avr32_scif_oscctrl; + + if (osc == SCIF_OSC0) + { + // Read Register + u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0] = AVR32_SCIF.OSCCTRL[SCIF_OSC0] ; + // Modify : Configure the oscillator mode to crystal and set the gain according to the + // cyrstal frequency. + u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].mode = SCIF_OSC_MODE_2PIN_CRYSTAL; + u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].gain = (fcrystal < 900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 : + (fcrystal < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 : + (fcrystal < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 : + AVR32_SCIF_OSCCTRL0_GAIN_G3; + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected OSCCTRL0 register + SCIF_UNLOCK(AVR32_SCIF_OSCCTRL); + // Write Back + AVR32_SCIF.OSCCTRL[SCIF_OSC0] = u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0]; + AVR32_LEAVE_CRITICAL_REGION( ); + } + else + { + // Read Register + u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1] = AVR32_SCIF.OSCCTRL[SCIF_OSC1] ; + // Modify : Configure the oscillator mode to crystal and set the gain according to the + // cyrstal frequency. + u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1].mode = SCIF_OSC_MODE_2PIN_CRYSTAL; + u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1].gain = (fcrystal < 900000) ? AVR32_SCIF_OSCCTRL1_GAIN_G0 : + (fcrystal < 3000000) ? AVR32_SCIF_OSCCTRL1_GAIN_G1 : + (fcrystal < 8000000) ? AVR32_SCIF_OSCCTRL1_GAIN_G2 : + AVR32_SCIF_OSCCTRL1_GAIN_G3; + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected OSCCTRL1 register + SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4); + // Write Back + AVR32_SCIF.OSCCTRL[SCIF_OSC1] = u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1]; + AVR32_LEAVE_CRITICAL_REGION( ); + } + + return PASS; +} + +long int scif_configure_osc_extmode(scif_osc_t osc) +{ + u_avr32_scif_oscctrl_t u_avr32_scif_oscctrl; + + // Read Register + u_avr32_scif_oscctrl.OSCCTRL[osc] = AVR32_SCIF.OSCCTRL[osc] ; + // Modify : Configure the oscillator mode to crystal and set the gain according to the + // cyrstal frequency. + u_avr32_scif_oscctrl.OSCCTRL[osc].mode = SCIF_OSC_MODE_EXT_CLK; + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected OSCCTRL0 register + SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc); + // Write Back + AVR32_SCIF.OSCCTRL[osc] = u_avr32_scif_oscctrl.OSCCTRL[osc]; + AVR32_LEAVE_CRITICAL_REGION( ); + + return PASS; +} + +long int scif_enable_osc(scif_osc_t osc, unsigned int startup, bool wait_for_ready) +{ + + u_avr32_scif_oscctrl_t u_avr32_scif_oscctrl; + + // Read Register + u_avr32_scif_oscctrl.OSCCTRL[osc] = AVR32_SCIF.OSCCTRL[osc] ; + // Modify: Configure the oscillator startup and enable the osc. + u_avr32_scif_oscctrl.OSCCTRL[osc].startup = startup; + u_avr32_scif_oscctrl.OSCCTRL[osc].oscen = ENABLE; + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected OSCCTRL0 register + SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc); + // Write Back + AVR32_SCIF.OSCCTRL[osc] = u_avr32_scif_oscctrl.OSCCTRL[osc]; + AVR32_LEAVE_CRITICAL_REGION( ); + + if(true == wait_for_ready) + { + // Wait until OSC0 is stable and ready to be used. + if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK)) + return -1; + } + + return PASS; +} + +long int scif_enable_extosc(scif_osc_t osc) +{ + + u_avr32_scif_oscctrl_t u_avr32_scif_oscctrl; + + // Read Register + u_avr32_scif_oscctrl.OSCCTRL[osc] = AVR32_SCIF.OSCCTRL[osc] ; + // Modify : Enable the osc. + u_avr32_scif_oscctrl.OSCCTRL[osc].oscen = ENABLE; + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected OSCCTRL0 register + SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc); + // Write Back + AVR32_SCIF.OSCCTRL[osc] = u_avr32_scif_oscctrl.OSCCTRL[osc]; + AVR32_LEAVE_CRITICAL_REGION( ); + + return PASS; +} + +/** + ** PLL0/PLL1 Functions + **/ +long int scif_pll_setup(scif_pll_t pll, const scif_pll_opt_t opt) +{ + + u_avr32_scif_pll_t u_avr32_scif_pll; + + // Read Register + u_avr32_scif_pll.PLL[pll] = AVR32_SCIF.PLL[pll] ; + // Modify Configuration + u_avr32_scif_pll.PLL[pll].pllosc = opt.osc; + u_avr32_scif_pll.PLL[pll].pllopt = opt.pll_freq | (opt.pll_div2 << 1) | (opt.pll_wbwdisable << 2); + u_avr32_scif_pll.PLL[pll].plldiv = opt.div; + u_avr32_scif_pll.PLL[pll].pllmul = opt.mul; + u_avr32_scif_pll.PLL[pll].pllcount= opt.lockcount; + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected PLL0 register + SCIF_UNLOCK(AVR32_SCIF_PLL + 4*pll); + // Write Back + AVR32_SCIF.PLL[pll] = u_avr32_scif_pll.PLL[pll]; + AVR32_LEAVE_CRITICAL_REGION( ); + + return PASS; +} + +long int scif_pll_enable(scif_pll_t pll) +{ + + u_avr32_scif_pll_t u_avr32_scif_pll; + + // Read Register + u_avr32_scif_pll.PLL[pll] = AVR32_SCIF.PLL[pll] ; + // Modify Configuration + u_avr32_scif_pll.PLL[pll].pllen = ENABLE; + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected PLL0 register + SCIF_UNLOCK(AVR32_SCIF_PLL + 4*pll); + // Write Back + AVR32_SCIF.PLL[pll] = u_avr32_scif_pll.PLL[pll]; + AVR32_LEAVE_CRITICAL_REGION( ); + + return PASS; +} + +long int scif_pll_disable(scif_pll_t pll) +{ + + u_avr32_scif_pll_t u_avr32_scif_pll; + + // Read Register + u_avr32_scif_pll.PLL[pll] = AVR32_SCIF.PLL[pll] ; + // Modify Configuration + u_avr32_scif_pll.PLL[pll].pllen = DISABLE; + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected PLL0 register + SCIF_UNLOCK(AVR32_SCIF_PLL + 4*pll); + // Write Back + AVR32_SCIF.PLL[pll] = u_avr32_scif_pll.PLL[pll]; + AVR32_LEAVE_CRITICAL_REGION( ); + + return PASS; +} + +long int scif_wait_for_pll_locked(scif_pll_t pll) +{ + + if (pll == SCIF_PLL0) + { + // Wait until PLL0 is stable and ready to be used. + while(!(AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_PLL0_LOCK_MASK)); + } + else + { + // Wait until PLL1 is stable and ready to be used. + while(!(AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_PLL1_LOCK_MASK)); + } + + return PASS; +} + +/** + ** OSC32 Functions + **/ + +long int scif_start_osc32(const scif_osc32_opt_t *opt, bool wait_for_ready) +{ + u_avr32_scif_oscctrl32_t u_avr32_scif_oscctrl32; + + +#ifdef AVR32SFW_INPUT_CHECK + // Check that the input frequency is in the supported frequency range. + if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ) + || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ)) + { + return -1; + } + // Check : for OSC0/OSC1, only 2 modes are supported + if( (opt->mode < SCIF_OSC_MODE_EXT_CLK) + || (opt->mode > SCIF_OSC_MODE_2PIN_CRYSTAL) + || (opt->mode == SCIF_OSC_MODE_NOT_SUPPORTED_1) + || (opt->mode == SCIF_OSC_MODE_NOT_SUPPORTED_2) ) + { + return -1; + } + // Check that the startup value is in the supported range. + if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL32_STARTUP_524288_RCOSC) + { + return -1; + } +#endif // AVR32SFW_INPUT_CHECK + + // Read Register + u_avr32_scif_oscctrl32.oscctrl32 = AVR32_SCIF.oscctrl32 ; + + // Modify : Configure & start OSC32. + u_avr32_scif_oscctrl32.OSCCTRL32.mode = opt->mode; + u_avr32_scif_oscctrl32.OSCCTRL32.startup = opt->startup; + u_avr32_scif_oscctrl32.OSCCTRL32.osc32en = ENABLE; + + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected OSCCTRL32 register + SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32); + + // Write Back + AVR32_SCIF.oscctrl32 = u_avr32_scif_oscctrl32.oscctrl32; + AVR32_LEAVE_CRITICAL_REGION( ); + + if(true == wait_for_ready) + { + // Wait until OSC32 is stable and ready to be used. + if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC32RDY_MASK)) + return -1; + } + + return PASS; +} + + +long scif_stop_osc32() +{ + unsigned long temp = AVR32_SCIF.oscctrl32; + temp &= ~AVR32_SCIF_OSCCTRL32_OSC32EN_MASK; + + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected OSCCTRL32 register + SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32); + + // Stop OSC32. + AVR32_SCIF.oscctrl32 = temp; + AVR32_LEAVE_CRITICAL_REGION( ); + + return PASS; +} + + +/** + ** Calibration Functions + **/ + + +/** + ** Critical Path Oscillator Functions + **/ + +/** + ** 8MHz RCosc Functions + **/ + +void scif_start_rc8M(void) +{ + unsigned int* calibration_bits = (unsigned int*)0x80800200; + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected RC8MCR register + SCIF_UNLOCK(AVR32_SCIF_RCCR8); + AVR32_SCIF.rccr8 = AVR32_SCIF_RCCR8_RCOSC8_EN_MASK | ((*calibration_bits)&AVR32_SCIF_RCCR8_CALIB_MASK); + AVR32_LEAVE_CRITICAL_REGION( ); +} + +void scif_stop_rc8M(void) +{ + unsigned long temp = AVR32_SCIF.rccr8; + + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected RC8MCR register + SCIF_UNLOCK(AVR32_SCIF_RCCR8); + temp &= ~AVR32_SCIF_RCCR8_RCOSC8_EN_MASK; + AVR32_SCIF.rccr8 = temp; + AVR32_LEAVE_CRITICAL_REGION( ); +} + +/** + ** 120MHz RCosc Functions + **/ + +void scif_start_rc120M(void) +{ + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected RC120MCR register + SCIF_UNLOCK(AVR32_SCIF_RC120MCR); + AVR32_SCIF.rc120mcr = AVR32_SCIF_RC120MCR_EN_MASK; + AVR32_LEAVE_CRITICAL_REGION( ); +} + +void scif_stop_rc120M(void) +{ + unsigned long temp = AVR32_SCIF.rc120mcr; + + AVR32_ENTER_CRITICAL_REGION( ); + // Unlock the write-protected RC120MCR register + SCIF_UNLOCK(AVR32_SCIF_RC120MCR); + temp &= ~AVR32_SCIF_RC120MCR_EN_MASK; + AVR32_SCIF.rc120mcr = temp; + AVR32_LEAVE_CRITICAL_REGION( ); +} + + + +/** + ** Generic Clock Functions + **/ + +long int scif_start_gclk(unsigned int gclk, const scif_gclk_opt_t *opt) +{ +#ifdef AVR32SFW_INPUT_CHECK + // Check that the generic clock number is correct + if( gclk > AVR32_SCIF_GCLK_NUM ) + { + return -1; + } + // Check that the clock source for the generic clock is correct. + if(( opt->clock_source >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( opt->clock_source < 0 )) + { + return -1; + } +#endif // AVR32SFW_INPUT_CHECK + + // If the generic clock is already enabled, return an error. + if(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK) + return -1; + + // Configure & start the generic clock. + AVR32_SCIF.gcctrl[gclk] = ((opt->divider << AVR32_SCIF_GCCTRL_DIV_OFFSET)&AVR32_SCIF_GCCTRL_DIV_MASK) + |((opt->diven << AVR32_SCIF_GCCTRL_DIVEN_OFFSET)&AVR32_SCIF_GCCTRL_DIVEN_MASK) + |((opt->clock_source << AVR32_SCIF_GCCTRL_OSCSEL_OFFSET)&AVR32_SCIF_GCCTRL_OSCSEL_MASK) + |(AVR32_SCIF_GCCTRL_CEN_MASK); + + return PASS; +} + + +long int scif_stop_gclk(unsigned int gclk) +{ + unsigned int timeout = SCIF_POLL_TIMEOUT; + +#ifdef AVR32SFW_INPUT_CHECK + // Check that the generic clock number is correct + if( gclk > AVR32_SCIF_GCLK_NUM ) + { + return -1; + } +#endif // AVR32SFW_INPUT_CHECK + + // Stop the generic clock. + AVR32_SCIF.gcctrl[gclk] &= ~AVR32_SCIF_GCCTRL_CEN_MASK; + + // Wait until the generic clock is actually stopped. + while(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK) + { + if(--timeout == 0) + return -1; + } + + return PASS; +} + + +long int scif_gc_setup(unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor) +{ + int restart_gc = false; + + + // Change the division factor to conform to the equation: fgclk = fsrc/divfactor = fsrc/(2*(div+1)) + divfactor = (divfactor>>1) -1; + +#ifdef AVR32SFW_INPUT_CHECK + // Check that the generic clock number is correct + if( gclk > AVR32_SCIF_GCLK_NUM ) + { + return -1; + } + // Check that the clock source for the generic clock is correct. + if(( clk_src >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( clk_src < 0 )) + { + return -1; + } + // Check that the required division factor is correct. + if(diven) + { + if(divfactor >= (1< AVR32_SCIF_GCLK_NUM ) + { + return -1; + } +#endif // AVR32SFW_INPUT_CHECK + + // If the generic clock is already enabled, do nothing. + if(!(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)) + AVR32_SCIF.gcctrl[gclk] |= AVR32_SCIF_GCCTRL_CEN_MASK; + + return PASS; + +} + +void scif_bod18_enable_irq(void) +{ + AVR32_SCIF.ier = AVR32_SCIF_IER_BODDET_MASK ; +} + +void scif_bod18_disable_irq(void) +{ + bool global_interrupt_enabled = Is_global_interrupt_enabled(); + + if (global_interrupt_enabled) Disable_global_interrupt(); + AVR32_SCIF.idr = AVR32_SCIF_IDR_BODDET_MASK; + AVR32_SCIF.isr; + if (global_interrupt_enabled) Enable_global_interrupt(); +} + +void scif_bod18_clear_irq(void) +{ + AVR32_SCIF.icr = AVR32_SCIF_ICR_BODDET_MASK; +} + +unsigned long scif_bod18_get_irq_status(void) +{ + return ((AVR32_SCIF.isr & AVR32_SCIF_ISR_BODDET_MASK) != 0); +} + +unsigned long scif_bod18_get_irq_enable_bit(void) +{ + return ((AVR32_SCIF.imr & AVR32_SCIF_IMR_BODDET_MASK) != 0); +} + +unsigned long scif_bod18_get_level(void) +{ + return (AVR32_SCIF.bod & AVR32_SCIF_BOD_LEVEL_MASK) >> AVR32_SCIF_BOD_LEVEL_OFFSET; +} + +void scif_bod33_enable_irq(void) +{ + AVR32_SCIF.ier = AVR32_SCIF_IER_BOD33DET_MASK ; +} + +void scif_bod33_disable_irq(void) +{ + bool global_interrupt_enabled = Is_global_interrupt_enabled(); + + if (global_interrupt_enabled) Disable_global_interrupt(); + AVR32_SCIF.idr = AVR32_SCIF_IDR_BOD33DET_MASK; + AVR32_SCIF.isr; + if (global_interrupt_enabled) Enable_global_interrupt(); +} + +void scif_bod33_clear_irq(void) +{ + AVR32_SCIF.icr = AVR32_SCIF_ICR_BOD33DET_MASK; +} + +unsigned long scif_bod33_get_irq_status(void) +{ + return ((AVR32_SCIF.isr & AVR32_SCIF_ISR_BOD33DET_MASK) != 0); +} + +unsigned long scif_bod33_get_irq_enable_bit(void) +{ + return ((AVR32_SCIF.imr & AVR32_SCIF_IMR_BOD33DET_MASK) != 0); +} + +unsigned long scif_bod33_get_level(void) +{ + return (AVR32_SCIF.bod33 & AVR32_SCIF_BOD33_LEVEL_MASK) >> AVR32_SCIF_BOD33_LEVEL_OFFSET; +} + +void scif_bod50_enable_irq(void) +{ + AVR32_SCIF.ier = AVR32_SCIF_IER_BOD50DET_MASK ; +} + +void scif_bod50_disable_irq(void) +{ + bool global_interrupt_enabled = Is_global_interrupt_enabled(); + + if (global_interrupt_enabled) Disable_global_interrupt(); + AVR32_SCIF.idr = AVR32_SCIF_IDR_BOD50DET_MASK; + AVR32_SCIF.isr; + if (global_interrupt_enabled) Enable_global_interrupt(); +} + +void scif_bod50_clear_irq(void) +{ + AVR32_SCIF.icr = AVR32_SCIF_ICR_BOD50DET_MASK; +} + +unsigned long scif_bod50_get_irq_status(void) +{ + return ((AVR32_SCIF.isr & AVR32_SCIF_ISR_BOD50DET_MASK) != 0); +} + +unsigned long scif_bod50_get_irq_enable_bit(void) +{ + return ((AVR32_SCIF.imr & AVR32_SCIF_IMR_BOD50DET_MASK) != 0); +} + +unsigned long scif_bod50_get_level(void) +{ + return (AVR32_SCIF.bod50 & AVR32_SCIF_BOD50_LEVEL_MASK) >> AVR32_SCIF_BOD50_LEVEL_OFFSET; +} + diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/scif/scif_uc3c.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/scif/scif_uc3c.h new file mode 100644 index 0000000..74c3a2c --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/scif/scif_uc3c.h @@ -0,0 +1,761 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief System Control InterFace(SCIF) driver interface. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 UC3C devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ +#ifndef _SCIF_UC3C_H_ +#define _SCIF_UC3C_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "compiler.h" + + +// These defines are missing from or wrong in the toolchain header file ip_xxx.h or part.h +#ifdef AVR32_SCIF_101_H_INCLUDED +#define AVR32_SCIF_OSCCTRL0_STARTUP_0_RCOSC 0x00000000 +#define AVR32_SCIF_OSCCTRL0_STARTUP_128_RCOSC 0x00000002 +#define AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC 0x00000006 +#define AVR32_SCIF_OSCCTRL0_STARTUP_2048_RCOSC 0x00000003 +#define AVR32_SCIF_OSCCTRL0_STARTUP_4096_RCOSC 0x00000004 +#define AVR32_SCIF_OSCCTRL0_STARTUP_64_RCOSC 0x00000001 +#define AVR32_SCIF_OSCCTRL0_STARTUP_8192_RCOSC 0x00000005 +#define AVR32_SCIF_OSCCTRL1_STARTUP_0_RCOSC 0x00000000 +#define AVR32_SCIF_OSCCTRL1_STARTUP_128_RCOSC 0x00000002 +#define AVR32_SCIF_OSCCTRL1_STARTUP_16384_RCOSC 0x00000006 +#define AVR32_SCIF_OSCCTRL1_STARTUP_2048_RCOSC 0x00000003 +#define AVR32_SCIF_OSCCTRL1_STARTUP_4096_RCOSC 0x00000004 +#define AVR32_SCIF_OSCCTRL1_STARTUP_64_RCOSC 0x00000001 +#define AVR32_SCIF_OSCCTRL1_STARTUP_8192_RCOSC 0x00000005 +#define AVR32_SCIF_OSCCTRL32_STARTUP_0_RCOSC 0x00000000 +#define AVR32_SCIF_OSCCTRL32_STARTUP_128_RCOSC 0x00000001 +#define AVR32_SCIF_OSCCTRL32_STARTUP_131072_RCOSC 0x00000005 +#define AVR32_SCIF_OSCCTRL32_STARTUP_16384_RCOSC 0x00000003 +#define AVR32_SCIF_OSCCTRL32_STARTUP_262144_RCOSC 0x00000006 +#define AVR32_SCIF_OSCCTRL32_STARTUP_524288_RCOSC 0x00000007 +#define AVR32_SCIF_OSCCTRL32_STARTUP_65536_RCOSC 0x00000004 +#define AVR32_SCIF_OSCCTRL32_STARTUP_8192_RCOSC 0x00000002 +#define AVR32_SCIF_OSCCTRL0_MODE_CRYSTAL 0x00000001 +#define AVR32_SCIF_OSCCTRL0_MODE_EXTCLK 0x00000000 +#define AVR32_SCIF_OSCCTRL0_GAIN_G0 0x00000000 +#define AVR32_SCIF_OSCCTRL0_GAIN_G1 0x00000001 +#define AVR32_SCIF_OSCCTRL0_GAIN_G2 0x00000002 +#define AVR32_SCIF_OSCCTRL0_GAIN_G3 0x00000003 +#define AVR32_SCIF_OSCCTRL1_GAIN_G0 0x00000000 +#define AVR32_SCIF_OSCCTRL1_GAIN_G1 0x00000001 +#define AVR32_SCIF_OSCCTRL1_GAIN_G2 0x00000002 +#define AVR32_SCIF_OSCCTRL1_GAIN_G3 0x00000003 +#define AVR32_SCIF_UNLOCK_KEY_VALUE 0x000000AA +#define AVR32_SCIF_OSCCTRL_OSCEN_ENABLE 0x00000001 +#define AVR32_SCIF_OSCCTRL_OSCEN_DISABLE 0x00000000 +#define AVR32_SCIF_OSCCTRL32_OSC32EN_ENABLE 0x00000001 +#define AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE 0x00000000 +#endif + + +//! Device-specific data + +//!< External crystal/clock min frequency (in Herz) +#define SCIF_EXT_CRYSTAL_MIN_FREQ_HZ 4000000 +//!< External crystal/clock max frequency (in Herz) +#define SCIF_EXT_CRYSTAL_MAX_FREQ_HZ 20000000 + +//! The different clock source for the generic clocks +typedef enum +{ + SCIF_GCCTRL_SLOWCLOCK = AVR32_SCIF_GC_USES_CLK_SLOW, + SCIF_GCCTRL_OSC32K = AVR32_SCIF_GC_USES_CLK_32, + SCIF_GCCTRL_OSC0 = AVR32_SCIF_GC_USES_OSC0, + SCIF_GCCTRL_OSC1 = AVR32_SCIF_GC_USES_OSC1, + SCIF_GCCTRL_PLL0 = AVR32_SCIF_GC_USES_PLL0, + SCIF_GCCTRL_PLL1 = AVR32_SCIF_GC_USES_PLL1, + SCIF_GCCTRL_RC8M = AVR32_SCIF_GC_USES_RCOSC8, + SCIF_GCCTRL_CPUCLOCK = AVR32_SCIF_GC_USES_CLK_CPU, + SCIF_GCCTRL_HSBCLOCK = AVR32_SCIF_GC_USES_CLK_HSB, + SCIF_GCCTRL_PBACLOCK = AVR32_SCIF_GC_USES_CLK_PBA, + SCIF_GCCTRL_PBBCLOCK = AVR32_SCIF_GC_USES_CLK_PBB, + SCIF_GCCTRL_OSCSEL_INVALID +} scif_gcctrl_oscsel_t; + + + +//! The timeguard used for polling in ticks. +#define SCIF_POLL_TIMEOUT 100000 + +//! Define "not supported" for the chosen implementation. +#define SCIF_NOT_SUPPORTED (-10000) + + +//! The different oscillators +typedef enum +{ + SCIF_OSC0 = 0, + SCIF_OSC1 = 1 +} scif_osc_t; + +//! The different plls +typedef enum +{ + SCIF_PLL0 = 0, + SCIF_PLL1 = 1 +} scif_pll_t; + +//! The different oscillator modes +typedef enum +{ + SCIF_OSC_MODE_EXT_CLK = 0, // For both OSC0 & OSC32 + SCIF_OSC_MODE_2PIN_CRYSTAL = 1, // For both OSC0 & OSC32 + SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR = 2, // For OSC32 only +} scif_osc_mode_t; + +//! OSC0/OSC1 startup options. +typedef struct +{ + //! The input frequency (from the external clock or the crystal). + unsigned long freq_hz; + //! Set the oscillator mode. + scif_osc_mode_t mode; + //! Specify the oscillator startup time. + unsigned char startup; + //! Gain for the oscillator + unsigned char gain; +} scif_osc_opt_t; + +//! PLL0/PLL1 startup options. +typedef struct +{ + //! Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. + unsigned char pll_freq; + //! 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. + unsigned char pll_wbwdisable; + //! Divide the PLL output frequency by 2. (this settings does not change the FVCO value) + unsigned char pll_div2; + //! PLL MUL in the PLL formula + unsigned int mul; + //! PLL DIV in the PLL formula + unsigned int div; + //! PLL lockount + unsigned int lockcount; + //! Specify the scillator input. + unsigned char osc; +} scif_pll_opt_t; + +//! OSC32 startup options. +typedef struct +{ + //! The input frequency (from the external clock or the crystal). + unsigned long freq_hz; + //! Set the oscillator mode. + scif_osc_mode_t mode; + //! Specify the oscillator startup time. + unsigned char startup; +} scif_osc32_opt_t; + + +//! Generic clock generation settings. +typedef struct +{ + //! The input clock source to use for the generic clock + scif_gcctrl_oscsel_t clock_source; + //! The division factor to apply to the clock src. + unsigned int divider; + //! Enable/disable the generic clock divisor + unsigned int diven; +} scif_gclk_opt_t; + + +//! Unlock SCIF register macro +#define SCIF_UNLOCK(reg) (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)|(reg)) + +/*! \name Interrupt Functions + */ +//! @{ + +/*! \brief Enable SCIF interrupts. + * + * \param mask the interrupts to enable. + */ + #if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void scif_enable_interrupts(unsigned long mask) +{ + AVR32_SCIF.ier = mask; +} + +/*! \brief Disable SCIF interrupts. + * + * \param mask the interrupts to disable. + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void scif_disable_interrupts(unsigned long mask) +{ + AVR32_SCIF.idr = mask; +} + +/*! \brief Read the SCIF currently enabled interrupts. + * + * \return The enabled interrupts. + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline unsigned long scif_get_enabled_interrupts(void) +{ + return(AVR32_SCIF.imr); +} + +/*! \brief Read the interrupt status of the SCIF. + * + * \return The interrupts which have been triggered. + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline unsigned long scif_get_interrupts_status(void) +{ + return(AVR32_SCIF.isr); +} + +/*! \brief Clear raised interrupts from the SCIF. + * + * \param mask The interrupts to clear. + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void scif_clear_interrupts_status(unsigned long mask) +{ + AVR32_SCIF.icr = mask; +} + +//! @} + + +/*! \name Power and Clocks Status Functions + */ +//! @{ + +/*! \brief Read the Power and Clocks Status of the SCIF. + * + * \return The content of the PCLKSR register + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline unsigned long scif_get_pclk_status(void) +{ + return(AVR32_SCIF.pclksr); +} + +//! @} + + +/*! \name OSC0/OSC1 Functions + */ +//! @{ + +/*! \brief Configure and start an OSC0/OSC1 oscillator. + * + * \param osc The oscillator to start [INPUT] + * \param opt The configuration of the oscillator [INPUT] + * \param wait_for_ready Wait for the oscillator to be stable before return [INPUT] + * + * \note To avoid an infinite loop, this function checks the osc0 ready flag + * SCIF_POLL_TIMEOUT times. + * + * \return Status. + * \retval 0 Oscillator start successfull. + * \retval <0 Error starting the oscillator. + */ +extern long int scif_start_osc(scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready); + +/*! \brief Is an oscillator stable and ready to be used as clock source? + * + * \param osc The oscillator [INPUT] + * + * \return Status. + * \retval true oscillator stable and ready + * \retval false oscillator not enabled or not ready. + */ +extern bool scif_is_osc_ready(scif_osc_t osc); + +/*! \brief Stop an oscillator. + * + * \param osc The oscillator to stop + * + * \return Status. + * \retval 0 Oscillator successfully stopped. + * \retval <0 An error occured when stopping the oscillator. + */ +extern long int scif_stop_osc(scif_osc_t osc); + +/*! \brief Configure an oscillator in crystal mode + * + * \param osc The oscillator to configure [INPUT] + * \param fcrystal Crystal frequency (Hz) [INPUT] + * + * \return Status. + * \retval 0 Oscillator successfully configured. + * \retval <0 Error configuring the oscillator. + */ +extern long int scif_configure_osc_crystalmode(scif_osc_t osc, unsigned int fcrystal); + +/*! \brief Configure an external clock as input clock + * + * \param osc The external clock to configure [INPUT] + * + * \return Status. + * \retval 0 External clock successfully configured. + * \retval <0 Error configuring the external clock. + */ +extern long int scif_configure_osc_extmode(scif_osc_t osc); + +/*! \brief Enable an oscillator with a given startup time. + * + * \param osc The oscillator to configure [INPUT] + * \param startup Oscillator startup time (one of AVR32_SCIF_OSCCTRLx_STARTUP_x_RCOSC) [INPUT] + * \param wait_for_ready Wait for the oscillator to be stable before return [INPUT] + * + * \return Status. + * \retval 0 Oscillator successfully started + * \retval <0 Error starting the oscillator. + */ +extern long int scif_enable_osc(scif_osc_t osc, unsigned int startup, bool wait_for_ready); + +/*! \brief Enable external clock. + * + * \param osc The oscillator to configure [INPUT] + * + * \return Status. + * \retval 0 Oscillator successfully started + * \retval <0 Error starting the oscillator. + */ +extern long int scif_enable_extosc(scif_osc_t osc); + +//! @} + + +/*! \name PLL0/PLL1 Functions + */ +//! @{ + +/*! + * \brief This function will setup a PLL. + * \param pll The PLL to configure [INPUT] + * \param opt The configuration of the PLL [INPUT] + * \return Status. + * \retval 0 PLL successfully started + * \retval <0 Error starting the PLL. + */ +extern long int scif_pll_setup(scif_pll_t pll, const scif_pll_opt_t opt); + +/*! + * \brief This function will enable a PLL. + * \param pll The PLL to configure [INPUT] + * \return Status. + * \retval 0 PLL successfully started + * \retval <0 Error starting the PLL. + */ +extern long int scif_pll_enable(scif_pll_t pll); + + +/*! + * \brief This function will disable a PLL. + * \param pll The PLL to configure [INPUT] + * \return Status. + * \retval 0 PLL successfully started + * \retval <0 Error starting the PLL. + */ +extern long int scif_pll_disable(scif_pll_t pll); + + +/*! + * \brief This function will wait for PLL locked + * \param pll The PLL to configure [INPUT] + * \return Status. + * \retval 0 PLL successfully started + * \retval <0 Error starting the PLL. + */ +extern long int scif_wait_for_pll_locked(scif_pll_t pll); + +//! @} + +/*! \name OSC32 Functions + */ +//! @{ + +/*! \brief Configure and start the OSC32 oscillator. + * + * \param opt The configuration of the oscillator [INPUT] + * \param wait_for_ready Wait for the oscillator to be stable before return [INPUT] + * + * \note To avoid an infinite loop, this function checks the osc32 ready flag + * SCIF_POLL_TIMEOUT times. + * + * \return Status. + * \retval 0 Oscillator start successfull. + * \retval <0 Error starting the oscillator. + */ +extern long int scif_start_osc32(const scif_osc32_opt_t *opt, bool wait_for_ready); + +/*! \brief Is OSC32 stable and ready to be used as clock source? + * + * \return Status. + * \retval true oscillator stable and ready + * \retval false oscillator not enabled or not ready. + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline bool scif_is_osc32_ready(void) +{ + return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC32RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC32RDY_OFFSET); +} + + +/*! \brief Stop the OSC32 oscillator. + * + * \return Status. + * \retval 0 Oscillator successfully stopped. + * \retval <0 An error occured when stopping the oscillator. + */ +extern long int scif_stop_osc32(void); + +//! @} + + +/*! \name Calibration Functions + */ +//! @{ + +/*! \brief Enables the 1.8V Brown-Out Detector interrupt. + * + */ +extern void scif_bod18_enable_irq(void); + + +/*! \brief Disables the 1.8V Brown-Out Detector interrupt. + * + */ +extern void scif_bod18_disable_irq(void); + + +/*! \brief Clears the 1.8V Brown-Out Detector interrupt flag. + * + */ +extern void scif_bod18_clear_irq(void); + + +/*! \brief Gets the 1.8V Brown-Out Detector interrupt flag. + * + * + * \retval 0 No BOD interrupt. + * \retval 1 BOD interrupt pending. + */ +extern unsigned long scif_bod18_get_irq_status(void); + + +/*! \brief Gets the 1.8V Brown-Out Detector interrupt enable status. + * + * + * \retval 0 BOD interrupt disabled. + * \retval 1 BOD interrupt enabled. + */ +extern unsigned long scif_bod18_get_irq_enable_bit(void); + + +/*! \brief Gets the triggering threshold of the 1.8V Brown-Out Detector. + * + */ +extern unsigned long scif_bod18_get_level(void); + + +/*! \brief Enables the 3.3V Brown-Out Detector interrupt. + * + */ +extern void scif_bod33_enable_irq(void); + + +/*! \brief Disables the 3.3V Brown-Out Detector interrupt. + * + */ +extern void scif_bod33_disable_irq(void); + + +/*! \brief Clears the 3.3V Brown-Out Detector interrupt flag. + * + */ +extern void scif_bod33_clear_irq(void); + + +/*! \brief Gets the 3.3V Brown-Out Detector interrupt flag. + * + * + * \retval 0 No BOD interrupt. + * \retval 1 BOD interrupt pending. + */ +extern unsigned long scif_bod33_get_irq_status(void); + + +/*! \brief Gets the 3.3V Brown-Out Detector interrupt enable status. + * + * + * \retval 0 BOD interrupt disabled. + * \retval 1 BOD interrupt enabled. + */ +extern unsigned long scif_bod33_get_irq_enable_bit(void); + + +/*! \brief Gets the triggering threshold of the 3.3V Brown-Out Detector. + * + */ +extern unsigned long scif_bod33_get_level(void); + +/*! \brief Enables the 5.0V Brown-Out Detector interrupt. + * + */ +extern void scif_bod50_enable_irq(void); + + +/*! \brief Disables the 5.0V Brown-Out Detector interrupt. + * + */ +extern void scif_bod50_disable_irq(void); + + +/*! \brief Clears the 5.0V Brown-Out Detector interrupt flag. + * + */ +extern void scif_bod50_clear_irq(void); + + +/*! \brief Gets the 5.0V Brown-Out Detector interrupt flag. + * + * + * \retval 0 No BOD interrupt. + * \retval 1 BOD interrupt pending. + */ +extern unsigned long scif_bod50_get_irq_status(void); + + +/*! \brief Gets the 5.0V Brown-Out Detector interrupt enable status. + * + * + * \retval 0 BOD interrupt disabled. + * \retval 1 BOD interrupt enabled. + */ +extern unsigned long scif_bod50_get_irq_enable_bit(void); + + +/*! \brief Gets the triggering threshold of the 5.0V Brown-Out Detector. + * + */ +extern unsigned long scif_bod50_get_level(void); + +//! @} + + +/*! \name Critical Path Oscillator Functions + */ +//! @{ + + +//! @} + +/*! \name 8MHz RCosc Functions + */ +//! @{ + +/*! \brief Start the 8MHz internal RCosc (RC8M) clock + */ +extern void scif_start_rc8M(void); + +/*! \brief Stop the 8MHz internal RCosc (RC8M) clock + */ +extern void scif_stop_rc8M(void); + + +/*! \name 120MHz RCosc Functions + */ +//! @{ + +/*! \brief Start the 120MHz internal RCosc (RC120M) clock + */ +extern void scif_start_rc120M(void); + +/*! \brief Stop the 120MHz internal RCosc (RC120M) clock + */ +extern void scif_stop_rc120M(void); + +//! @} + + +/*! \name Generic Clock Functions + */ +//! @{ + +/*! \brief Setup and start a generic clock. + * + * \param gclk The generic clock number to setup and start (cf. datasheet) + * \param opt The settings for the generic clock. + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured. + */ +extern long int scif_start_gclk(unsigned int gclk, const scif_gclk_opt_t *opt); + +/*! \brief Stop a generic clock. + * + * \param gclk The generic clock number to stop. + * + * \note To avoid an infinite loop, this function checks the Clock enable flag + * SCIF_POLL_TIMEOUT times. + * + * \return Status. + * \retval 0 Success. + * \retval <0 Unable to stop generic clock. + */ +extern long int scif_stop_gclk(unsigned int gclk); + +/*! \brief Setup a generic clock. + * + * \param gclk generic clock number (0 for gc0...) + * \param clk_src The input clock source to use for the generic clock + * \param diven Generic clock divisor enable + * \param divfactor Generic clock divisor + * + * \note If the generic clock is already enabled, this function will disable it, + * apply the configuration then restart the generic clock. + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured. + */ +extern long int scif_gc_setup(unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor); + +/*! \brief Enable a generic clock. + * + * \param gclk generic clock number (0 for gc0...) + * + * \return Status. + * \retval 0 Success. + * \retval <0 An error occured. + */ +extern long int scif_gc_enable(unsigned int gclk); + +//! @} + + +/*! \name Backup Registers Functions + */ +//! @{ +/*! + * \brief Read the content of the SCIF GPLP registers + * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part) + * + * \return The content of the chosen GPLP register. + */ +extern unsigned long scif_read_gplp(unsigned long gplp); + + +/*! + * \brief Write into the SCIF GPLP registers + * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part) + * \param value Value to write + */ +extern void scif_write_gplp(int gplp, unsigned long value); + +//! @} + + +/*! \name Temperature Sensor Management Functions + */ +//! @{ + + +/*! \brief Enable the temperature sensor + * + * \note Due to register unlock process, this function needs to be atomic. So if + * there's risk that call is split by any interrupts, disable them first. + * + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void scif_temperature_sensor_enable(void) +{ + // Unlock the write-protected TSENS register + SCIF_UNLOCK(AVR32_SCIF_TSENS); + AVR32_SCIF.tsens = AVR32_SCIF_TSENS_EN_MASK; +} + +/*! \brief Disable the temperature sensor. + * + * \note Due to register unlock process, this function needs to be atomic so if + * there's risk that call is split by an interrupt, disable them first. + * + */ +#if defined (__GNUC__) +__attribute__((__always_inline__)) +#endif +static inline void scif_temperature_sensor_disable(void) +{ + // Unlock the write-protected TSENS register + SCIF_UNLOCK(AVR32_SCIF_TSENS); + AVR32_SCIF.tsens = ~AVR32_SCIF_TSENS_EN_MASK; +} + +//! @} + + +#ifdef __cplusplus +} +#endif + +#endif // _SCIF_UC3C_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/tc/tc.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/tc/tc.c new file mode 100644 index 0000000..0be1e77 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/tc/tc.c @@ -0,0 +1,312 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief TC driver for AVR32 UC3. + * + * AVR32 Timer/Counter driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a TC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include +#include "compiler.h" +#include "tc.h" + + +int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return tc->channel[channel].imr; +} + + +int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield) +{ + bool global_interrupt_enabled = Is_global_interrupt_enabled(); + + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Enable the appropriate interrupts. + tc->channel[channel].ier = bitfield->etrgs << AVR32_TC_ETRGS_OFFSET | + bitfield->ldrbs << AVR32_TC_LDRBS_OFFSET | + bitfield->ldras << AVR32_TC_LDRAS_OFFSET | + bitfield->cpcs << AVR32_TC_CPCS_OFFSET | + bitfield->cpbs << AVR32_TC_CPBS_OFFSET | + bitfield->cpas << AVR32_TC_CPAS_OFFSET | + bitfield->lovrs << AVR32_TC_LOVRS_OFFSET | + bitfield->covfs << AVR32_TC_COVFS_OFFSET; + + // Disable the appropriate interrupts. + if (global_interrupt_enabled) Disable_global_interrupt(); + tc->channel[channel].idr = (~bitfield->etrgs & 1) << AVR32_TC_ETRGS_OFFSET | + (~bitfield->ldrbs & 1) << AVR32_TC_LDRBS_OFFSET | + (~bitfield->ldras & 1) << AVR32_TC_LDRAS_OFFSET | + (~bitfield->cpcs & 1) << AVR32_TC_CPCS_OFFSET | + (~bitfield->cpbs & 1) << AVR32_TC_CPBS_OFFSET | + (~bitfield->cpas & 1) << AVR32_TC_CPAS_OFFSET | + (~bitfield->lovrs & 1) << AVR32_TC_LOVRS_OFFSET | + (~bitfield->covfs & 1) << AVR32_TC_COVFS_OFFSET; + tc->channel[channel].sr; + if (global_interrupt_enabled) Enable_global_interrupt(); + + return 0; +} + + +int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS || ext_clk_sig_src >= 1 << AVR32_TC_BMR_TC0XC0S_SIZE) + return TC_INVALID_ARGUMENT; + + // Clear bit-field and set the correct behavior. + tc->bmr = (tc->bmr & ~(AVR32_TC_BMR_TC0XC0S_MASK << (channel * AVR32_TC_BMR_TC0XC0S_SIZE))) | + (ext_clk_sig_src << (channel * AVR32_TC_BMR_TC0XC0S_SIZE)); + + return 0; +} + + +int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt) +{ + // Check for valid input. + if (opt->channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // MEASURE SIGNALS: Capture operating mode. + tc->channel[opt->channel].cmr = opt->ldrb << AVR32_TC_LDRB_OFFSET | + opt->ldra << AVR32_TC_LDRA_OFFSET | + 0 << AVR32_TC_WAVE_OFFSET | + opt->cpctrg << AVR32_TC_CPCTRG_OFFSET | + opt->abetrg << AVR32_TC_ABETRG_OFFSET | + opt->etrgedg << AVR32_TC_ETRGEDG_OFFSET| + opt->ldbdis << AVR32_TC_LDBDIS_OFFSET | + opt->ldbstop << AVR32_TC_LDBSTOP_OFFSET | + opt->burst << AVR32_TC_BURST_OFFSET | + opt->clki << AVR32_TC_CLKI_OFFSET | + opt->tcclks << AVR32_TC_TCCLKS_OFFSET; + + return 0; +} + + +int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt) +{ + // Check for valid input. + if (opt->channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // GENERATE SIGNALS: Waveform operating mode. + tc->channel[opt->channel].cmr = opt->bswtrg << AVR32_TC_BSWTRG_OFFSET | + opt->beevt << AVR32_TC_BEEVT_OFFSET | + opt->bcpc << AVR32_TC_BCPC_OFFSET | + opt->bcpb << AVR32_TC_BCPB_OFFSET | + opt->aswtrg << AVR32_TC_ASWTRG_OFFSET | + opt->aeevt << AVR32_TC_AEEVT_OFFSET | + opt->acpc << AVR32_TC_ACPC_OFFSET | + opt->acpa << AVR32_TC_ACPA_OFFSET | + 1 << AVR32_TC_WAVE_OFFSET | + opt->wavsel << AVR32_TC_WAVSEL_OFFSET | + opt->enetrg << AVR32_TC_ENETRG_OFFSET | + opt->eevt << AVR32_TC_EEVT_OFFSET | + opt->eevtedg << AVR32_TC_EEVTEDG_OFFSET | + opt->cpcdis << AVR32_TC_CPCDIS_OFFSET | + opt->cpcstop << AVR32_TC_CPCSTOP_OFFSET | + opt->burst << AVR32_TC_BURST_OFFSET | + opt->clki << AVR32_TC_CLKI_OFFSET | + opt->tcclks << AVR32_TC_TCCLKS_OFFSET; + + return 0; +} + + +int tc_start(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Enable, reset and start the selected timer/counter channel. + tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK | AVR32_TC_CLKEN_MASK; + + return 0; +} + + +int tc_stop(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Disable the selected timer/counter channel. + tc->channel[channel].ccr = AVR32_TC_CLKDIS_MASK; + + return 0; +} + + +int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Reset the selected timer/counter channel. + tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK; + + return 0; +} + + +void tc_sync_trigger(volatile avr32_tc_t *tc) +{ + // Reset all channels of the selected timer/counter. + tc->bcr = AVR32_TC_BCR_SYNC_MASK; +} + + +void tc_sync_start(volatile avr32_tc_t *tc) +{ + unsigned int i; + // Enable the clock for each channel. + for(i=0; ichannel[i].ccr = AVR32_TC_CLKEN_MASK; + + // Reset all channels of the selected timer/counter. + tc->bcr = AVR32_TC_BCR_SYNC_MASK; +} + + +int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return tc->channel[channel].sr; +} + + +int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].cv, AVR32_TC_CV_MASK); +} + + +int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK); +} + + +int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK); +} + + +int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK); +} + + +int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // This function is only available in WAVEFORM mode. + if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK)) + Wr_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK, value); + + return value; +} + + +int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // This function is only available in WAVEFORM mode. + if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK)) + Wr_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK, value); + + return value; +} + + +int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // This function is only available in WAVEFORM mode. + if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK)) + Wr_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK, value); + + return value; +} diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/tc/tc.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/tc/tc.h new file mode 100644 index 0000000..0b4027d --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/tc/tc.h @@ -0,0 +1,589 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Timer/Counter driver for AVR32 UC3. + * + * AVR32 Timer/Counter driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a TC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _TC_H_ +#define _TC_H_ + +#include + + +//! TC driver functions return value in case of invalid argument(s). +#define TC_INVALID_ARGUMENT (-1) + +//! Number of timer/counter channels. +#define TC_NUMBER_OF_CHANNELS (sizeof(((avr32_tc_t *)0)->channel) / sizeof(avr32_tc_channel_t)) + +/*! \name External Clock Signal 0 Selection + */ +//! @{ +#define TC_CH0_EXT_CLK0_SRC_TCLK0 AVR32_TC_TC0XC0S_TCLK0 +#define TC_CH0_EXT_CLK0_SRC_NO_CLK AVR32_TC_TC0XC0S_NO_CLK +#define TC_CH0_EXT_CLK0_SRC_TIOA1 AVR32_TC_TC0XC0S_TIOA1 +#define TC_CH0_EXT_CLK0_SRC_TIOA2 AVR32_TC_TC0XC0S_TIOA2 +//! @} + +/*! \name External Clock Signal 1 Selection + */ +//! @{ +#define TC_CH1_EXT_CLK1_SRC_TCLK1 AVR32_TC_TC1XC1S_TCLK1 +#define TC_CH1_EXT_CLK1_SRC_NO_CLK AVR32_TC_TC1XC1S_NO_CLK +#define TC_CH1_EXT_CLK1_SRC_TIOA0 AVR32_TC_TC1XC1S_TIOA0 +#define TC_CH1_EXT_CLK1_SRC_TIOA2 AVR32_TC_TC1XC1S_TIOA2 +//! @} + +/*! \name External Clock Signal 2 Selection + */ +//! @{ +#define TC_CH2_EXT_CLK2_SRC_TCLK2 AVR32_TC_TC2XC2S_TCLK2 +#define TC_CH2_EXT_CLK2_SRC_NO_CLK AVR32_TC_TC2XC2S_NO_CLK +#define TC_CH2_EXT_CLK2_SRC_TIOA0 AVR32_TC_TC2XC2S_TIOA0 +#define TC_CH2_EXT_CLK2_SRC_TIOA1 AVR32_TC_TC2XC2S_TIOA1 +//! @} + +/*! \name Event/Trigger Actions on Output + */ +//! @{ +#define TC_EVT_EFFECT_NOOP AVR32_TC_NONE +#define TC_EVT_EFFECT_SET AVR32_TC_SET +#define TC_EVT_EFFECT_CLEAR AVR32_TC_CLEAR +#define TC_EVT_EFFECT_TOGGLE AVR32_TC_TOGGLE +//! @} + +/*! \name RC Compare Trigger Enable + */ +//! @{ +#define TC_NO_TRIGGER_COMPARE_RC 0 +#define TC_TRIGGER_COMPARE_RC 1 +//! @} + +/*! \name Waveform Selection + */ +//! @{ +#define TC_WAVEFORM_SEL_UP_MODE AVR32_TC_WAVSEL_UP_NO_AUTO +#define TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER AVR32_TC_WAVSEL_UP_AUTO +#define TC_WAVEFORM_SEL_UPDOWN_MODE AVR32_TC_WAVSEL_UPDOWN_NO_AUTO +#define TC_WAVEFORM_SEL_UPDOWN_MODE_RC_TRIGGER AVR32_TC_WAVSEL_UPDOWN_AUTO +//! @} + +/*! \name TIOA or TIOB External Trigger Selection + */ +//! @{ +#define TC_EXT_TRIG_SEL_TIOA 1 +#define TC_EXT_TRIG_SEL_TIOB 0 +//! @} + +/*! \name External Event Selection + */ +//! @{ +#define TC_EXT_EVENT_SEL_TIOB_INPUT AVR32_TC_EEVT_TIOB_INPUT +#define TC_EXT_EVENT_SEL_XC0_OUTPUT AVR32_TC_EEVT_XC0_OUTPUT +#define TC_EXT_EVENT_SEL_XC1_OUTPUT AVR32_TC_EEVT_XC1_OUTPUT +#define TC_EXT_EVENT_SEL_XC2_OUTPUT AVR32_TC_EEVT_XC2_OUTPUT +//! @} + +/*! \name Edge Selection + */ +//! @{ +#define TC_SEL_NO_EDGE AVR32_TC_EEVTEDG_NO_EDGE +#define TC_SEL_RISING_EDGE AVR32_TC_EEVTEDG_POS_EDGE +#define TC_SEL_FALLING_EDGE AVR32_TC_EEVTEDG_NEG_EDGE +#define TC_SEL_EACH_EDGE AVR32_TC_EEVTEDG_BOTH_EDGES +//! @} + +/*! \name Burst Signal Selection + */ +//! @{ +#define TC_BURST_NOT_GATED AVR32_TC_BURST_NOT_GATED +#define TC_BURST_CLK_AND_XC0 AVR32_TC_BURST_CLK_AND_XC0 +#define TC_BURST_CLK_AND_XC1 AVR32_TC_BURST_CLK_AND_XC1 +#define TC_BURST_CLK_AND_XC2 AVR32_TC_BURST_CLK_AND_XC2 +//! @} + +/*! \name Clock Invert + */ +//! @{ +#define TC_CLOCK_RISING_EDGE 0 +#define TC_CLOCK_FALLING_EDGE 1 +//! @} + +/*! \name Clock Selection + */ +//! @{ +#define TC_CLOCK_SOURCE_TC1 AVR32_TC_TCCLKS_TIMER_CLOCK1 +#define TC_CLOCK_SOURCE_TC2 AVR32_TC_TCCLKS_TIMER_CLOCK2 +#define TC_CLOCK_SOURCE_TC3 AVR32_TC_TCCLKS_TIMER_CLOCK3 +#define TC_CLOCK_SOURCE_TC4 AVR32_TC_TCCLKS_TIMER_CLOCK4 +#define TC_CLOCK_SOURCE_TC5 AVR32_TC_TCCLKS_TIMER_CLOCK5 +#define TC_CLOCK_SOURCE_XC0 AVR32_TC_TCCLKS_XC0 +#define TC_CLOCK_SOURCE_XC1 AVR32_TC_TCCLKS_XC1 +#define TC_CLOCK_SOURCE_XC2 AVR32_TC_TCCLKS_XC2 +//! @} + + +//! Timer/counter interrupts. +typedef struct +{ + unsigned int :24; + + //! External trigger interrupt. + unsigned int etrgs : 1; + + //! RB load interrupt. + unsigned int ldrbs : 1; + + //! RA load interrupt. + unsigned int ldras : 1; + + //! RC compare interrupt. + unsigned int cpcs : 1; + + //! RB compare interrupt. + unsigned int cpbs : 1; + + //! RA compare interrupt. + unsigned int cpas : 1; + + //! Load overrun interrupt. + unsigned int lovrs : 1; + + //! Counter overflow interrupt. + unsigned int covfs : 1; +} tc_interrupt_t; + +//! Parameters when initializing a timer/counter in capture mode. +typedef struct +{ + //! Channel to initialize. + unsigned int channel ; + + unsigned int :12; + + //! RB loading selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int ldrb : 2; + + //! RA loading selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int ldra : 2; + + unsigned int : 1; + + //! RC compare trigger enable:\n + //! - \ref TC_NO_TRIGGER_COMPARE_RC;\n + //! - \ref TC_TRIGGER_COMPARE_RC. + unsigned int cpctrg : 1; + + unsigned int : 3; + + //! TIOA or TIOB external trigger selection:\n + //! - \ref TC_EXT_TRIG_SEL_TIOA;\n + //! - \ref TC_EXT_TRIG_SEL_TIOB. + unsigned int abetrg : 1; + + //! External trigger edge selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int etrgedg : 2; + + //! Counter clock disable with RB loading:\n + //! - \c false;\n + //! - \c true. + unsigned int ldbdis : 1; + + //! Counter clock stopped with RB loading:\n + //! - \c false;\n + //! - \c true. + unsigned int ldbstop : 1; + + //! Burst signal selection:\n + //! - \ref TC_BURST_NOT_GATED;\n + //! - \ref TC_BURST_CLK_AND_XC0;\n + //! - \ref TC_BURST_CLK_AND_XC1;\n + //! - \ref TC_BURST_CLK_AND_XC2. + unsigned int burst : 2; + + //! Clock invert:\n + //! - \ref TC_CLOCK_RISING_EDGE;\n + //! - \ref TC_CLOCK_FALLING_EDGE. + unsigned int clki : 1; + + //! Clock selection:\n + //! - \ref TC_CLOCK_SOURCE_TC1;\n + //! - \ref TC_CLOCK_SOURCE_TC2;\n + //! - \ref TC_CLOCK_SOURCE_TC3;\n + //! - \ref TC_CLOCK_SOURCE_TC4;\n + //! - \ref TC_CLOCK_SOURCE_TC5;\n + //! - \ref TC_CLOCK_SOURCE_XC0;\n + //! - \ref TC_CLOCK_SOURCE_XC1;\n + //! - \ref TC_CLOCK_SOURCE_XC2. + unsigned int tcclks : 3; +} tc_capture_opt_t; + +//! Parameters when initializing a timer/counter in waveform mode. +typedef struct +{ + //! Channel to initialize. + unsigned int channel ; + + //! Software trigger effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int bswtrg : 2; + + //! External event effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int beevt : 2; + + //! RC compare effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int bcpc : 2; + + //! RB compare effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int bcpb : 2; + + //! Software trigger effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int aswtrg : 2; + + //! External event effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int aeevt : 2; + + //! RC compare effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int acpc : 2; + + //! RA compare effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int acpa : 2; + + unsigned int : 1; + + //! Waveform selection:\n + //! - \ref TC_WAVEFORM_SEL_UP_MODE;\n + //! - \ref TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER;\n + //! - \ref TC_WAVEFORM_SEL_UPDOWN_MODE;\n + //! - \ref TC_WAVEFORM_SEL_UPDOWN_MODE_RC_TRIGGER. + unsigned int wavsel : 2; + + //! External event trigger enable:\n + //! - \c false;\n + //! - \c true. + unsigned int enetrg : 1; + + //! External event selection:\n + //! - \ref TC_EXT_EVENT_SEL_TIOB_INPUT;\n + //! - \ref TC_EXT_EVENT_SEL_XC0_OUTPUT;\n + //! - \ref TC_EXT_EVENT_SEL_XC1_OUTPUT;\n + //! - \ref TC_EXT_EVENT_SEL_XC2_OUTPUT. + unsigned int eevt : 2; + + //! External event edge selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int eevtedg : 2; + + //! Counter clock disable with RC compare:\n + //! - \c false;\n + //! - \c true. + unsigned int cpcdis : 1; + + //! Counter clock stopped with RC compare:\n + //! - \c false;\n + //! - \c true. + unsigned int cpcstop : 1; + + //! Burst signal selection:\n + //! - \ref TC_BURST_NOT_GATED;\n + //! - \ref TC_BURST_CLK_AND_XC0;\n + //! - \ref TC_BURST_CLK_AND_XC1;\n + //! - \ref TC_BURST_CLK_AND_XC2. + unsigned int burst : 2; + + //! Clock invert:\n + //! - \ref TC_CLOCK_RISING_EDGE;\n + //! - \ref TC_CLOCK_FALLING_EDGE. + unsigned int clki : 1; + + //! Clock selection:\n + //! - \ref TC_CLOCK_SOURCE_TC1;\n + //! - \ref TC_CLOCK_SOURCE_TC2;\n + //! - \ref TC_CLOCK_SOURCE_TC3;\n + //! - \ref TC_CLOCK_SOURCE_TC4;\n + //! - \ref TC_CLOCK_SOURCE_TC5;\n + //! - \ref TC_CLOCK_SOURCE_XC0;\n + //! - \ref TC_CLOCK_SOURCE_XC1;\n + //! - \ref TC_CLOCK_SOURCE_XC2. + unsigned int tcclks : 3; +} tc_waveform_opt_t; + + +/*! \brief Reads timer/counter interrupt settings. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 The interrupt enable configuration organized according to \ref tc_interrupt_t. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Enables various timer/counter interrupts. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param bitfield The interrupt enable configuration. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield); + +/*! \brief Selects which external clock to use and how to configure it. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param ext_clk_sig_src External clock signal selection: + * \arg \c TC_CH0_EXT_CLK0_SRC_TCLK0; + * \arg \c TC_CH0_EXT_CLK0_SRC_NO_CLK; + * \arg \c TC_CH0_EXT_CLK0_SRC_TIOA1; + * \arg \c TC_CH0_EXT_CLK0_SRC_TIOA2; + * \arg \c TC_CH1_EXT_CLK1_SRC_TCLK1; + * \arg \c TC_CH1_EXT_CLK1_SRC_NO_CLK; + * \arg \c TC_CH1_EXT_CLK1_SRC_TIOA0; + * \arg \c TC_CH1_EXT_CLK1_SRC_TIOA2; + * \arg \c TC_CH2_EXT_CLK2_SRC_TCLK2; + * \arg \c TC_CH2_EXT_CLK2_SRC_NO_CLK; + * \arg \c TC_CH2_EXT_CLK2_SRC_TIOA0; + * \arg \c TC_CH2_EXT_CLK2_SRC_TIOA1. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src); + +/*! \brief Sets options for timer/counter capture initialization. + * + * \param tc Pointer to the TC instance to access. + * \param opt Options for capture mode. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt); + +/*! \brief Sets options for timer/counter waveform initialization. + * + * \param tc Pointer to the TC instance to access. + * \param opt Options for waveform generation. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt); + +/*! \brief Starts a timer/counter. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_start(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Stops a timer/counter. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_stop(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Performs a software trigger: the counter is reset and the clock is started. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Asserts a SYNC signal to generate a software trigger and reset all channels. + * + * \param tc Pointer to the TC instance to access. + */ +extern void tc_sync_trigger(volatile avr32_tc_t *tc); + +/*! \brief Start all TC channels simultaneously. + * + * \param tc Pointer to the TC instance to access. + */ +extern void tc_sync_start(volatile avr32_tc_t *tc); + +/*! \brief Reads the status register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 Status register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's TC counter and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 TC counter value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's RA register and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 RA register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's RB register and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 RB register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's RC register and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 RC register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Writes a value to the channel's RA register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param value Value to write to the RA register. + * + * \retval >=0 Written value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value); + +/*! \brief Writes a value to the channel's RB register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param value Value to write to the RB register. + * + * \retval >=0 Written value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value); + +/*! \brief Writes a value to the channel's RC register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param value Value to write to the RC register. + * + * \retval >=0 Written value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value); + + +#endif // _TC_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/wdt/wdt.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/wdt/wdt.h new file mode 100644 index 0000000..06e0334 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/wdt/wdt.h @@ -0,0 +1,140 @@ + /** + * \file + * + * \brief WDT driver for WDT module from revision 4.0.0 for AVR32 UC3. + * + * Copyright (C) 2010 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#ifndef _WDT_H_ +#define _WDT_H_ + +// These defines are missing from or wrong in the toolchain header file ip_xxx.h or part.h +#if !defined(AVR32_SCIF_OSC32_FREQUENCY) +#define AVR32_SCIF_OSC32_FREQUENCY 32768 +#else +#warning "Duplicate define(s) to remove from the ASF" +#endif +// These defines are missing from or wrong in the toolchain header file ip_xxx.h or part.h +#if (defined AVR32_WDT_401_H_INCLUDED ) || (defined AVR32_WDT_410_H_INCLUDED ) +#define AVR32_WDT_KEY_VALUE 0x00000055 +#endif + +//! WDT Clock Source Select RCOSC +#define WDT_CLOCK_SOURCE_SELECT_RCSYS 0x0 + +//! WDT Clock Source Select 32K Oscillator +#define WDT_CLOCK_SOURCE_SELECT_OSC32K 0x1 + +//! WDT Basic Mode +#define WDT_BASIC_MODE 0x0 + +//! WDT Window Mode +#define WDT_WINDOW_MODE 0x1 + +//! WDT startup options. +typedef struct +{ + //! Prescaler value for the timeout. + uint64_t us_timeout_period; +#if AVR32_WDT_H_VERSION >= 400 + //! Prescaler value for the timeban. + uint64_t us_timeban_period; + //! Clock Source Select. + uint8_t cssel; + //! Flash Calibration Done. + uint8_t fcd; + //! Store final Value. + uint8_t sfv; + //! Mode selection for the WDT + uint8_t mode; + //! Disable WDT after reset + uint8_t dar; +#endif +} wdt_opt_t; + +/** + * \brief Gets the time-out period of the WatchDog Timer in microseconds. + * + * \param opt Structure for settings of WDT. + * + * \retval <0 The WatchDog Timer is disabled. + * \retval >=0 Active time-out period of the WatchDog Timer in microseconds. + */ +int64_t wdt_get_us_timeout_period(wdt_opt_t *opt); + +// Only available for WDT versions above 400 +#if AVR32_WDT_H_VERSION >= 400 +/** + * \brief Gets the timeban period of the WatchDog Timer in microseconds. + * + * \param opt Structure for settings of WDT. + * + * \retval <0 The WatchDog Timer is disabled. + * \retval >=0 Active timeban period of the WatchDog Timer in microseconds. + */ +int64_t wdt_get_us_timeban_period(wdt_opt_t *opt); +#endif + +/** + * \brief Disables the WatchDog Timer. + */ +void wdt_disable(void); + +/** + * \brief Enables the WatchDog Timer with the \a us_timeout_period time-out + * period saturated to the supported range and rounded up to the nearest + * supported greater time-out period. + * + * \param opt Structure for settings of WDT. + * + * \return Actually configured time-out period in microseconds. + */ +uint64_t wdt_enable(wdt_opt_t *opt); + +/** + * \brief Re-enables the WatchDog Timer with the last time-out period + * configured. + */ +void wdt_reenable(void); + +/** + * \brief Clears the WatchDog Timer. + */ +void wdt_clear(void); + +/** + * \brief Resets the MCU with the WatchDog Timer as fast as possible. + */ +void wdt_reset_mcu(void); + +#endif // _WDT_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/wdt/wdt4.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/wdt/wdt4.c new file mode 100644 index 0000000..fcd6ce4 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/drivers/wdt/wdt4.c @@ -0,0 +1,165 @@ +/** + * \file + * + * \brief WDT driver for WDT module from revision 4.0.0 for AVR32 UC3. + * + * Copyright (C) 2010 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#include +#include "compiler.h" +#include "board.h" +#include "wdt.h" + +#define MIN_US_TIMEOUT_PERIOD_RCSYS (((1ULL << 1 ) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) +#define MAX_US_TIMEOUT_PERIOD_RCSYS (((1ULL << (1 << AVR32_WDT_CTRL_PSEL_SIZE)) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) +#define MIN_US_TIMEOUT_PERIOD_OSC32K (((1ULL << 1 ) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) +#define MAX_US_TIMEOUT_PERIOD_OSC32K (((1ULL << (1 << AVR32_WDT_CTRL_PSEL_SIZE)) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) + +#define MIN_US_TIMEBAN_PERIOD_RCSYS (((1ULL << 1 ) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) +#define MAX_US_TIMEBAN_PERIOD_RCSYS (((1ULL << (1 << AVR32_WDT_CTRL_TBAN_SIZE)) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) +#define MIN_US_TIMEBAN_PERIOD_OSC32K (((1ULL << 1 ) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) +#define MAX_US_TIMEBAN_PERIOD_OSC32K (((1ULL << (1 << AVR32_WDT_CTRL_TBAN_SIZE)) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) + +/** + * \brief Sets the WatchDog Timer Control register to the \a ctrl value thanks + * to the WatchDog Timer key. + * + * \param ctrl Value to set the WatchDog Timer Control register to. + * + * \note The KEY bit-field of \a ctrl is assumed to be zero. + */ +static void wdt_set_ctrl(uint32_t ctrl) +{ + AVR32_WDT.ctrl = ctrl | (AVR32_WDT_KEY_VALUE << AVR32_WDT_CTRL_KEY_OFFSET); + AVR32_WDT.ctrl = ctrl | ((uint32_t) (~AVR32_WDT_KEY_VALUE << AVR32_WDT_CTRL_KEY_OFFSET) & AVR32_WDT_CTRL_KEY_MASK); +} + +int64_t wdt_get_us_timeout_period(wdt_opt_t *opt) +{ + // RCOSC + if (opt->cssel == WDT_CLOCK_SOURCE_SELECT_RCSYS) { + // Read CTRL.PSEL and translate it into us. + return (AVR32_WDT.ctrl & AVR32_WDT_CTRL_EN_MASK) ? + ((1ULL << (((AVR32_WDT.ctrl & AVR32_WDT_CTRL_PSEL_MASK) >> AVR32_WDT_CTRL_PSEL_OFFSET) + 1)) * + 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY : + -1ULL; + } else { + // Read CTRL.PSEL and translate it into us. + return (AVR32_WDT.ctrl & AVR32_WDT_CTRL_EN_MASK) ? + ((1ULL << (((AVR32_WDT.ctrl & AVR32_WDT_CTRL_PSEL_MASK) >> AVR32_WDT_CTRL_PSEL_OFFSET) + 1)) * + 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY : + -1ULL; + } +} + +int64_t wdt_get_us_timeban_period(wdt_opt_t *opt) +{ + // RCOSC + if (opt->cssel == WDT_CLOCK_SOURCE_SELECT_RCSYS) { + // Read CTRL.PSEL and translate it into us. + return (AVR32_WDT.ctrl & AVR32_WDT_CTRL_EN_MASK) ? + ((1ULL << (((AVR32_WDT.ctrl & AVR32_WDT_CTRL_TBAN_MASK) >> AVR32_WDT_CTRL_TBAN_OFFSET) + 1)) * + 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY : + -1ULL; + } else { + // Read CTRL.PSEL and translate it into us. + return (AVR32_WDT.ctrl & AVR32_WDT_CTRL_EN_MASK) ? + ((1ULL << (((AVR32_WDT.ctrl & AVR32_WDT_CTRL_TBAN_MASK) >> AVR32_WDT_CTRL_TBAN_OFFSET) + 1)) * + 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY : + -1ULL; + } +} + +void wdt_disable(void) +{ + wdt_set_ctrl(AVR32_WDT.ctrl & ~AVR32_WDT_CTRL_EN_MASK); +} + +uint64_t wdt_enable(wdt_opt_t *opt) +{ + // RCOSC + if (opt->cssel == WDT_CLOCK_SOURCE_SELECT_RCSYS) { + // Set the CTRL.EN bit + // Translate the us timeout to fit in CTRL.PSEL using the formula Twdt = 2pow(PSEL+1) / fRCosc + // Translate the us timeban to fit in CTRL.PSEL using the formula Twdt = 2pow(PSEL+1) / fRCosc + wdt_set_ctrl(AVR32_WDT_CTRL_EN_MASK | AVR32_WDT_CTRL_CEN_MASK | + (opt->dar << AVR32_WDT_CTRL_DAR_OFFSET) | + (opt->mode << AVR32_WDT_CTRL_MODE_OFFSET) | + (opt->sfv << AVR32_WDT_CTRL_SFV_OFFSET) | + (opt->fcd << AVR32_WDT_CTRL_FCD_OFFSET) | + (opt->cssel << AVR32_WDT_CTRL_CSSEL_OFFSET) | + ((32 - clz(((((Min(Max(opt->us_timeout_period, MIN_US_TIMEOUT_PERIOD_RCSYS), MAX_US_TIMEOUT_PERIOD_RCSYS) * + AVR32_SCIF_RCOSC_FREQUENCY + 500000) / 1000000) << 1) - 1) >> 1) - 1) << AVR32_WDT_CTRL_PSEL_OFFSET) | + ((32 - clz(((((Min(Max(opt->us_timeban_period, MIN_US_TIMEBAN_PERIOD_RCSYS), MAX_US_TIMEBAN_PERIOD_RCSYS) * + AVR32_SCIF_RCOSC_FREQUENCY + 500000) / 1000000) << 1) - 1) >> 1) - 1) << AVR32_WDT_CTRL_TBAN_OFFSET)); + } else { + // Set the CTRL.EN bit + // Translate the us timeout to fit in CTRL.PSEL using the formula Twdt = 2pow(PSEL+1) / fROSC32K + // Translate the us timeban to fit in CTRL.PSEL using the formula Twdt = 2pow(PSEL+1) / fROSC32K + wdt_set_ctrl(AVR32_WDT_CTRL_EN_MASK | AVR32_WDT_CTRL_CEN_MASK | + (opt->dar << AVR32_WDT_CTRL_DAR_OFFSET) | + (opt->mode << AVR32_WDT_CTRL_MODE_OFFSET) | + (opt->sfv << AVR32_WDT_CTRL_SFV_OFFSET) | + (opt->fcd << AVR32_WDT_CTRL_FCD_OFFSET) | + (opt->cssel << AVR32_WDT_CTRL_CSSEL_OFFSET) | + ((32 - clz(((((Min(Max(opt->us_timeout_period, MIN_US_TIMEOUT_PERIOD_OSC32K), MAX_US_TIMEOUT_PERIOD_OSC32K) * + AVR32_SCIF_OSC32_FREQUENCY + 500000) / 1000000) << 1) - 1) >> 1) - 1) << AVR32_WDT_CTRL_PSEL_OFFSET) | + ((32 - clz(((((Min(Max(opt->us_timeout_period, MIN_US_TIMEBAN_PERIOD_OSC32K), MAX_US_TIMEBAN_PERIOD_OSC32K) * + AVR32_SCIF_OSC32_FREQUENCY + 500000) / 1000000) << 1) - 1) >> 1) - 1) << AVR32_WDT_CTRL_TBAN_OFFSET)); + } + // Return the actual wdt period in us. + return wdt_get_us_timeout_period(opt); +} + +void wdt_reenable(void) +{ + wdt_set_ctrl(AVR32_WDT.ctrl | AVR32_WDT_CTRL_EN_MASK | AVR32_WDT_CTRL_CEN_MASK ); +} + +void wdt_clear(void) +{ + while (!(AVR32_WDT.sr & AVR32_WDT_CLR_WDTCLR_MASK)); + AVR32_WDT.clr = ( (AVR32_WDT_KEY_VALUE << AVR32_WDT_KEY_OFFSET) | AVR32_WDT_CLR_WDTCLR_MASK ); + AVR32_WDT.clr = ( (~AVR32_WDT_KEY_VALUE << AVR32_WDT_KEY_OFFSET) | AVR32_WDT_CLR_WDTCLR_MASK ); +} + +void wdt_reset_mcu(void) +{ + Disable_global_interrupt(); + // Enable the WDT with a 0s period (fastest way to get a Watchdog reset). + wdt_opt_t opt = { + .us_timeout_period = 0 + }; + wdt_enable(&opt); + while (1); +} diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/services/network/can/can.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/services/network/can/can.c new file mode 100644 index 0000000..0e014da --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/services/network/can/can.c @@ -0,0 +1,464 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief CAN Software Stack for AVR32 UC3. + * + * This file contains basic functions for the AVR32 CAN, with support for all + * modes, settings and clock speeds. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a CANIF module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ +//_____ I N C L U D E S ________________________________________________________ +#include "avr32/io.h" +#include "can.h" +#include "compiler.h" +#include "preprocessor.h" +#include "intc.h" +#include "canif.h" +#include "CAN1c1.h" +//_____ D E F I N I T I O N S __________________________________________________ + +//_____ F U N C T I O N S ______________________________________________________ + +//! Dynamic Mob Allocation State Vector for Channel 0 +U32 can_mob_alloc_vector0 = 0; + +//! Dynamic Mob Allocation State Vector for Channel 1 +U32 can_mob_alloc_vector1 = 0; + +//! Output parameters. +static struct +{ + void (*can_msg_callback_channel0) (U8,U8,U8); + void (*can_msg_callback_channel1) (U8,U8,U8); +} can_lib_params = +{ + .can_msg_callback_channel0 = NULL, + .can_msg_callback_channel1 = NULL +}; + +#if defined (__GNUC__) +__attribute__((__interrupt__)) +#elif defined (__ICCAVR32__) +__interrupt +#endif +static void can0_int_tx_handler(void) +{ + U8 handle; + handle = CANIF_mob_get_mob_txok(0); + if (handle != 0x20) + { + CANIF_mob_clear_txok_status(0,handle); + CANIF_mob_clear_status(0,handle); // and reset MOb status + } + can_lib_params.can_msg_callback_channel0(handle,CAN_STATUS_COMPLETED,CAN__nenMbMode_Tx); +} + +#if defined (__GNUC__) +__attribute__((__interrupt__)) +#elif defined (__ICCAVR32__) +__interrupt +#endif +static void can0_int_rx_handler(void) +{ + U8 handle; + handle = CANIF_mob_get_mob_rxok(0) ; + if (handle != 0x20) + { + CANIF_mob_clear_rxok_status(0,handle); + CANIF_mob_clear_status(0,handle); // and reset MOb status + } + can_lib_params.can_msg_callback_channel0(handle,CAN_STATUS_COMPLETED,CAN__nenMbMode_Rx); +} + +#if defined (__GNUC__) +__attribute__((__interrupt__)) +#elif defined (__ICCAVR32__) +__interrupt +#endif +static void can0_int_busoff_handler(void) +{ + CANIF_clr_interrupt_status(0); + can_lib_params.can_msg_callback_channel0(0xFF,CAN_STATUS_BUSOFF,CAN_STATUS_BUSOFF); +} + +#if defined (__GNUC__) +__attribute__((__interrupt__)) +#elif defined (__ICCAVR32__) +__interrupt +#endif +static void can0_int_cerr_handler(void) +{ + CANIF_clr_interrupt_status(0); + can_lib_params.can_msg_callback_channel0(0xFF,CAN_STATUS_ERROR,CAN_STATUS_ERROR); +} + +#if defined (__GNUC__) +__attribute__((__interrupt__)) +#elif defined (__ICCAVR32__) +__interrupt +#endif +static void can0_int_wakeup_handler(void) +{ + CANIF_clr_interrupt_status(0); + can_lib_params.can_msg_callback_channel0(0xFF,CAN_STATUS_WAKEUP,CAN_STATUS_WAKEUP); +} + +#if defined (__GNUC__) +__attribute__((__interrupt__)) +#elif defined (__ICCAVR32__) +__interrupt +#endif +static void can1_int_tx_handler(void) +{ + U8 handle; + handle = CANIF_mob_get_mob_txok(1) ; + if (handle != 0x20) + { + CANIF_mob_clear_txok_status(1,handle); + CANIF_mob_clear_status(1,handle); // and reset MOb status + } + can_lib_params.can_msg_callback_channel1(handle,CAN_STATUS_COMPLETED,CAN__nenMbMode_Tx); +} + +#if defined (__GNUC__) +__attribute__((__interrupt__)) +#elif defined (__ICCAVR32__) +__interrupt +#endif +static void can1_int_rx_handler(void) +{ + U8 handle; + handle = CANIF_mob_get_mob_rxok(1) ; + if (handle != 0x20) + { + CANIF_mob_clear_rxok_status(1,handle); + CANIF_mob_clear_status(1,handle); // and reset MOb status + } + can_lib_params.can_msg_callback_channel1(handle,CAN_STATUS_COMPLETED,CAN__nenMbMode_Rx); +} + +#if defined (__GNUC__) +__attribute__((__interrupt__)) +#elif defined (__ICCAVR32__) +__interrupt +#endif +static void can1_int_busoff_handler(void) +{ + CANIF_clr_interrupt_status(1); + can_lib_params.can_msg_callback_channel1(0xFF,CAN_STATUS_BUSOFF,CAN_STATUS_BUSOFF); +} + +#if defined (__GNUC__) +__attribute__((__interrupt__)) +#elif defined (__ICCAVR32__) +__interrupt +#endif +static void can1_int_cerr_handler(void) +{ + CANIF_clr_interrupt_status(1); + can_lib_params.can_msg_callback_channel1(0xFF,CAN_STATUS_ERROR,CAN_STATUS_ERROR); +} + +#if defined (__GNUC__) +__attribute__((__interrupt__)) +#elif defined (__ICCAVR32__) +__interrupt +#endif +static void can1_int_wakeup_handler(void) +{ + CANIF_clr_interrupt_status(1); + can_lib_params.can_msg_callback_channel1(0xFF,CAN_STATUS_WAKEUP,CAN_STATUS_WAKEUP); +} + +U8 can_enable_interrupt(U8 ch) +{ + if ((ch > 1)) + return CAN_CMD_REFUSED; + + if (ch==0) + { + INTC_register_interrupt(&can0_int_tx_handler, AVR32_CANIF_TXOK_IRQ_0, CAN0_INT_TX_LEVEL); + INTC_register_interrupt(&can0_int_rx_handler, AVR32_CANIF_RXOK_IRQ_0, CAN0_INT_RX_LEVEL); + INTC_register_interrupt(&can0_int_busoff_handler, AVR32_CANIF_BUS_OFF_IRQ_0, CAN0_INT_BOFF_LEVEL); + INTC_register_interrupt(&can0_int_cerr_handler, AVR32_CANIF_ERROR_IRQ_0, CAN0_INT_ERR_LEVEL); + INTC_register_interrupt(&can0_int_wakeup_handler, AVR32_CANIF_WAKE_UP_IRQ_0, CAN0_INT_WAKE_UP_LEVEL); + CANIF_enable_interrupt(ch); + } + else if (ch == 1) + { + INTC_register_interrupt(&can1_int_tx_handler, AVR32_CANIF_TXOK_IRQ_1, CAN1_INT_TX_LEVEL); + INTC_register_interrupt(&can1_int_rx_handler, AVR32_CANIF_RXOK_IRQ_1, CAN1_INT_RX_LEVEL); + INTC_register_interrupt(&can1_int_busoff_handler, AVR32_CANIF_BUS_OFF_IRQ_1, CAN1_INT_BOFF_LEVEL); + INTC_register_interrupt(&can1_int_cerr_handler, AVR32_CANIF_ERROR_IRQ_1, CAN1_INT_ERR_LEVEL); + INTC_register_interrupt(&can1_int_wakeup_handler, AVR32_CANIF_WAKE_UP_IRQ_1, CAN1_INT_WAKE_UP_LEVEL); + CANIF_enable_interrupt(ch); + } + + return CAN_CMD_ACCEPTED; +} + +U8 can_init(U8 ch, + U32 can_msg_ram_add, + U8 operating_mode, + void (*can_msg_callback_channel) (U8 handle, U8 event, U8 dir)) +{ + if ( ch > 1) + return CAN_CMD_REFUSED; + + // Initialize CAN channel + CANIF_set_reset(ch); + while(CANIF_channel_enable_status(ch)); + CANIF_clr_reset(ch); + + CANIF_set_ram_add(ch,(unsigned long) can_msg_ram_add); + if ((CANIF_bit_timing(ch))==0) return (0); + switch(operating_mode) + { + case CANIF_CHANNEL_MODE_NORMAL: + CANIF_set_channel_mode(ch,0); + CANIF_clr_overrun_mode(ch); + break; + case CANIF_CHANNEL_MODE_LISTENING: + CANIF_set_channel_mode(ch,1); + CANIF_set_overrun_mode(ch); + break; + case CANIF_CHANNEL_MODE_LOOPBACK: + CANIF_set_channel_mode(ch,2); + CANIF_clr_overrun_mode(ch); + break; + } + canif_clear_all_mob(ch,NB_MOB_CHANNEL); + //CANIF_enable(ch); + //while(!CANIF_channel_enable_status(ch)); + +#ifdef CAN_LIB_UNDER_INTERRUPT + switch(ch) + { + case 0: + can_lib_params.can_msg_callback_channel0 = can_msg_callback_channel; + break; + case 1: + can_lib_params.can_msg_callback_channel1 = can_msg_callback_channel; + break; + } + can_enable_interrupt(ch); +#endif + + return CAN_CMD_ACCEPTED; +} + + +U8 can_mob_alloc(U8 ch) +{ + if ((ch > 1)) + return CAN_CMD_REFUSED; + + if(ch==0) + { + int i; + for (i=0;i>i)&0x01)) + { + can_mob_alloc_vector0|=(1<>i)&0x01)) + { + can_mob_alloc_vector1|=(1< 1)|| + (handle > (NB_MOB_CHANNEL-1))) + return CAN_CMD_REFUSED; + switch(ch) + { + case 0: + can_mob_alloc_vector0 &= (~(1< 1) || + (handle > (NB_MOB_CHANNEL-1)) || + (dlc > 8)) + return CAN_CMD_REFUSED; + + if (can_msg->ide_bit){ + CANIF_set_ext_id(ch, + handle, + can_msg->id); + + CANIF_set_ext_idmask(ch, + handle, + can_msg->id_mask); + } + else { + CANIF_set_std_id(ch, + handle, + can_msg->id); + CANIF_set_std_idmask(ch, + handle, + can_msg->id_mask); + } + CANIF_mob_set_dlc(ch,handle,dlc); + if (req_type == CAN_REMOTE_FRAME){ + CANIF_set_rtr(ch,handle); + CANIF_set_rtrmask(ch,handle); + CANIF_mob_set_automode(ch,handle); + } + CANIF_set_data(ch,handle,((can_msg_t *)can_msg)->data.u64); + CANIF_config_tx(ch,handle); + CANIF_mob_enable(ch,handle); +#ifdef CAN_LIB_UNDER_INTERRUPT + CANIF_mob_enable_interrupt(ch,handle); +#endif + return CAN_CMD_ACCEPTED; +} + +U8 can_rx( U8 ch, + U8 handle, + U8 req_type, + const can_msg_t *can_msg) +{ + if ((ch > 1) || + (handle > (NB_MOB_CHANNEL-1))) + return CAN_CMD_REFUSED; + if (can_msg->ide_bit){ + CANIF_set_ext_id(ch, + handle, + can_msg->id); + CANIF_set_ext_idmask(ch, + handle, + can_msg->id_mask); + } + else { + CANIF_set_std_id(ch, + handle, + can_msg->id); + CANIF_set_std_idmask(ch, + handle, + can_msg->id_mask); + } + if (req_type == CAN_REMOTE_FRAME){ + CANIF_set_rtr(ch,handle); + CANIF_set_rtrmask(ch,handle); + CANIF_mob_set_automode(ch,handle); + CANIF_set_data(ch,handle,((can_msg_t *)can_msg)->data.u64); + } + CANIF_config_rx(ch,handle); + CANIF_mob_enable(ch,handle); +#ifdef CAN_LIB_UNDER_INTERRUPT + CANIF_mob_enable_interrupt(ch,handle); +#endif + return CAN_CMD_ACCEPTED; +} + +Union64 can_get_mob_data( U8 ch , + U8 handle) +{ + return ((CANIF_mob_get_ptr_data(ch,handle)->data)); +} + +U8 can_get_mob_dlc( U8 ch , + U8 handle) +{ + return (CANIF_mob_get_dlc(ch,handle)); +} + +U32 can_get_mob_id( U8 ch , + U8 handle) +{ + return (CANIF_get_ext_id(ch,handle)); +} + +U8 can_mob_get_status( U8 ch, + U8 handle) +{ + U8 status; + if ((ch > 1)|| + (handle > (NB_MOB_CHANNEL-1)) ) + return CAN_CMD_REFUSED; + + status = CANIF_get_interrupt_error_status(ch); + if (status!=0) + return CAN_STATUS_ERROR; + + status = CANIF_mob_get_status(ch,handle); + if ( (status & MOB_RX_COMPLETED) || + (status & MOB_TX_COMPLETED) || + (status & MOB_RX_COMPLETED_DLCW) ) + return CAN_STATUS_COMPLETED; + + return CAN_STATUS_NOT_COMPLETED; +} + +void can_clear_status (U8 ch, + U8 mob) +{ + CANIF_mob_clear_status(ch,mob); +} diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/services/network/can/can.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/services/network/can/can.h new file mode 100644 index 0000000..f160a5f --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/services/network/can/can.h @@ -0,0 +1,183 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief CAN Software Stack for AVR32 UC3. + * + * This file contains basic functions for the AVR32 CAN, with support for all + * modes, settings and clock speeds. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a CANIF module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ +#ifndef _CAN_H_ +#define _CAN_H_ + +//_____ I N C L U D E S ________________________________________________________ +#include "conf_can.h" +#include "canif.h" +#include "compiler.h" +#include "preprocessor.h" +//_____ D E F I N I T I O N S __________________________________________________ + +// ---------- +//! This constant is used as return value for "can_cmd" function. +#define CAN_CMD_REFUSED 0xFF +// ---------- +//!This constant is used as return value for "can_cmd" function. +#define CAN_CMD_ACCEPTED 0x00 +// ---------- +//! This constant is used as return value for "can_get_status" function. +#define CAN_STATUS_COMPLETED 0x00 +// ---------- +//! This constant is used as return value for "can_get_status" function. +#define CAN_STATUS_NOT_COMPLETED 0x01 +// ---------- +//! This constant is used as return value for "can_get_status" function. +#define CAN_STATUS_ERROR 0x02 +// ---------- +//! This constant is used as return value for "can_get_status" function. +#define CAN_STATUS_WAKEUP 0x03 +// ---------- +//! This constant is used as return value for "can_get_status" function. +#define CAN_STATUS_BUSOFF 0x04 +// ---------- +//! This constant is used for MOB Allocation status +#define CAN_MOB_NOT_ALLOCATED 0xFF +// ---------- +//! This constant is used for MOB Initialization request +#define CAN_DATA_FRAME 0 +//! This constant is used for MOB Initialization request +#define CAN_REMOTE_FRAME 1 + +typedef struct{ + U8 handle; + can_msg_t *can_msg; + U8 dlc; + U8 req_type; + U8 status; +}can_mob_t; +//_____ D E C L A R A T I O N S ________________________________________________ + + +/*! \brief Initialize CAN channel + * \param ch CAN channel selected 0 (CAN Channel 0) 1 (CAN Channel 1) + * \param can_msg_ram_add Adress of the location of MOB Ram Buffer + * \param operating_mode Selection between CAN_CHANNEL_MODE_NORMAL or CAN_CHANNEL_MODE_LISTENING or CAN_CHANNEL_MODE_LOOPBACK + * \param can_msg_callback Callback for hardware interrupt + * \return U8 CAN_CMD_REFUSED or CAN_CMD_ACCEPTED + */ +extern U8 can_init( U8 ch, + U32 can_msg_ram_add, + U8 operating_mode, + void (*can_msg_callback) (U8,U8,U8)); + +/*! \brief Allocate one MOB in a specific CAN Channel + * \param ch CAN channel selected 0 (CAN Channel 0) 1 (CAN Channel 1) + * \return U8 CAN_CMD_REFUSED or the number of the MOB selected + */ +extern U8 can_mob_alloc(U8 ch); + +/*! \brief Free one specific MOB in a specific CAN Channel + * \param ch CAN channel selected 0 (CAN Channel 0) 1 (CAN Channel 1) + * \param handle CAN MOB number + * \return U8 CAN_CMD_REFUSED or CAN_CMD_ACCEPTED + */ +extern U8 can_mob_free(U8 ch,U8 handle); + +/*! \brief Start Transmission + * \param ch CAN channel selected 0 (CAN Channel 0) 1 (CAN Channel 1) + * \param handle CAN MOB number + * \param dlc Datalength + * \param req_type CAN_DATA_FRAME or CAN_REMOTE_FRAME + * \param can_msg CAN Message + * \return U8 CAN_CMD_REFUSED or CAN_CMD_ACCEPTED + */ +extern U8 can_tx( U8 ch, + U8 handle, + U8 dlc, + U8 req_type, + const can_msg_t *can_msg); + +/*! \brief Start Reception + * \param ch CAN channel selected 0 (CAN Channel 0) 1 (CAN Channel 1) + * \param handle CAN MOB number + * \param req_type CAN_DATA_FRAME or CAN_REMOTE_FRAME + * \param can_msg CAN Message + * \return U8 CAN_CMD_REFUSED or CAN_CMD_ACCEPTED + */ +extern U8 can_rx( U8 ch, + U8 handle, + U8 req_type, + const can_msg_t *can_msg); + + +/*! \brief Get Mob data from a selected MOB + * \param ch CAN channel selected 0 (CAN Channel 0) 1 (CAN Channel 1) + * \param handle CAN MOB number + * \return Union64 See compiler.h file for type return definition + */ +extern Union64 can_get_mob_data( U8 ch , + U8 handle); + +/*! \brief Get Mob dlc from a selected MOB + * \param ch CAN channel selected 0 (CAN Channel 0) 1 (CAN Channel 1) + * \param handle CAN MOB number + * \return U8 Return the DLC + */ +extern U8 can_get_mob_dlc( U8 ch , + U8 handle); + +/*! \brief Get Mob ID from a selected MOB + * \param ch CAN channel selected 0 (CAN Channel 0) 1 (CAN Channel 1) + * \param handle CAN MOB number + * \return U32 Return the ID + */ +extern U32 can_get_mob_id( U8 ch , + U8 handle); + +/*! \brief Get Mob status from a selected MOB + * \param ch CAN channel selected 0 (CAN Channel 0) 1 (CAN Channel 1) + * \param handle CAN MOB number + * \return U8 CAN_CMD_REFUSED or CAN_STATUS_ERROR or CAN_STATUS_COMPLETED or CAN_STATUS_NOT_COMPLETED + */ +extern U8 can_mob_get_status( U8 ch, + U8 handle); +//______________________________________________________________________________ + +#endif // _CAN_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/compiler.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/compiler.h new file mode 100644 index 0000000..2639c7a --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/compiler.h @@ -0,0 +1,1233 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Compiler file for AVR32. + * + * This file defines commonly used types and macros. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _COMPILER_AVR32_H_ +#define _COMPILER_AVR32_H_ + +#if (defined __ICCAVR32__) +# include +#endif +#include "preprocessor.h" + +#include "parts.h" + + +//_____ D E C L A R A T I O N S ____________________________________________ + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +#include +#include +#include +#include + + +#if (defined __ICCAVR32__) + +/*! \name Compiler Keywords + * + * Port of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32. + */ +//! @{ +#define __asm__ asm +#define __inline__ inline +#define __volatile__ +//! @} + +#endif + +/** + * \def barrier + * \brief Memory barrier + */ +#if defined(__GNUC__) +# define barrier() asm volatile("" ::: "memory") +#elif defined(__ICCAVR32__) +# define barrier() __asm__ __volatile__ ("") +#endif + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union + * definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union + * definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + + +/** + * \brief Set aligned boundary. + */ +#if (defined __GNUC__) +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif (defined __ICCAVR32__) +#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#endif + +/** + * \brief Set word-aligned boundary. + */ +#if (defined __GNUC__) +#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) +#elif (defined __ICCAVR32__) +#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4) +#endif + +/** + * \name System Register Access + * @{ + */ +#if defined(__GNUC__) || defined(__DOXYGEN__) +/** + * \brief Get value of system register + * + * \param reg Address of the system register of which to get the value. + * + * \return Value of system register \a reg. + */ +# define sysreg_read(reg) __builtin_mfsr(reg) + +/** + * \name Tag functions as deprecated + * + * Tagging a function as deprecated will produce a warning when and only + * when the function is called. + * + * Usage is to add the __DEPRECATED__ symbol before the function definition. + * E.g.: + * __DEPRECATED__ uint8_t some_deprecated_function (void) + * { + * ... + * } + * + * \note Only supported by GCC 3.1 and above, no IAR support + * @{ + */ +#if ((defined __GNUC__) && (__GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >=1))) +#define __DEPRECATED__ __attribute__((__deprecated__)) +#else +#define __DEPRECATED__ +#endif +//! @} + +/** + * \brief Set value of system register + * + * \param reg Address of the system register of which to set the value. + * \param val Value to set the system register \a reg to. + */ +# define sysreg_write(reg, val) __builtin_mtsr(reg, val) + +#elif defined(__ICCAVR32__) +# define sysreg_read(reg) __get_system_register(reg) +# define sysreg_write(reg, val) __set_system_register(reg, val) +#endif + +// Deprecated definitions +#define Get_system_register(reg) sysreg_read(reg) +#define Set_system_register(reg, val) sysreg_write(reg, val) +//! @} + +#include "interrupt.h" + +/*! \name Usual Types + */ +//! @{ +typedef unsigned char Bool; //!< Boolean. +#ifndef __cplusplus +#if !defined(__bool_true_false_are_defined) +typedef unsigned char bool; //!< Boolean. +#endif +#endif +typedef int8_t S8 ; //!< 8-bit signed integer. +typedef uint8_t U8 ; //!< 8-bit unsigned integer. +typedef int16_t S16; //!< 16-bit signed integer. +typedef uint16_t U16; //!< 16-bit unsigned integer. +typedef uint16_t le16_t; +typedef uint16_t be16_t; +typedef int32_t S32; //!< 32-bit signed integer. +typedef uint32_t U32; //!< 32-bit unsigned integer. +typedef uint32_t le32_t; +typedef uint32_t be32_t; +typedef signed long long int S64; //!< 64-bit signed integer. +typedef unsigned long long int U64; //!< 64-bit unsigned integer. +typedef float F32; //!< 32-bit floating-point number. +typedef double F64; //!< 64-bit floating-point number. +typedef uint32_t iram_size_t; +//! @} + + +/*! \name Status Types + */ +//! @{ +typedef bool Status_bool_t; //!< Boolean status. +typedef U8 Status_t; //!< 8-bit-coded status. +//! @} + + +/*! \name Aliasing Aggregate Types + */ +//! @{ + +//! 16-bit union. +typedef union +{ + S16 s16 ; + U16 u16 ; + S8 s8 [2]; + U8 u8 [2]; +} Union16; + +//! 32-bit union. +typedef union +{ + S32 s32 ; + U32 u32 ; + S16 s16[2]; + U16 u16[2]; + S8 s8 [4]; + U8 u8 [4]; +} Union32; + +//! 64-bit union. +typedef union +{ + S64 s64 ; + U64 u64 ; + S32 s32[2]; + U32 u32[2]; + S16 s16[4]; + U16 u16[4]; + S8 s8 [8]; + U8 u8 [8]; +} Union64; + +//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + S64 *s64ptr; + U64 *u64ptr; + S32 *s32ptr; + U32 *u32ptr; + S16 *s16ptr; + U16 *u16ptr; + S8 *s8ptr ; + U8 *u8ptr ; +} UnionPtr; + +//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + volatile S64 *s64ptr; + volatile U64 *u64ptr; + volatile S32 *s32ptr; + volatile U32 *u32ptr; + volatile S16 *s16ptr; + volatile U16 *u16ptr; + volatile S8 *s8ptr ; + volatile U8 *u8ptr ; +} UnionVPtr; + +//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + const S64 *s64ptr; + const U64 *u64ptr; + const S32 *s32ptr; + const U32 *u32ptr; + const S16 *s16ptr; + const U16 *u16ptr; + const S8 *s8ptr ; + const U8 *u8ptr ; +} UnionCPtr; + +//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + const volatile S64 *s64ptr; + const volatile U64 *u64ptr; + const volatile S32 *s32ptr; + const volatile U32 *u32ptr; + const volatile S16 *s16ptr; + const volatile U16 *u16ptr; + const volatile S8 *s8ptr ; + const volatile U8 *u8ptr ; +} UnionCVPtr; + +//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + S64 *s64ptr; + U64 *u64ptr; + S32 *s32ptr; + U32 *u32ptr; + S16 *s16ptr; + U16 *u16ptr; + S8 *s8ptr ; + U8 *u8ptr ; +} StructPtr; + +//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + volatile S64 *s64ptr; + volatile U64 *u64ptr; + volatile S32 *s32ptr; + volatile U32 *u32ptr; + volatile S16 *s16ptr; + volatile U16 *u16ptr; + volatile S8 *s8ptr ; + volatile U8 *u8ptr ; +} StructVPtr; + +//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + const S64 *s64ptr; + const U64 *u64ptr; + const S32 *s32ptr; + const U32 *u32ptr; + const S16 *s16ptr; + const U16 *u16ptr; + const S8 *s8ptr ; + const U8 *u8ptr ; +} StructCPtr; + +//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + const volatile S64 *s64ptr; + const volatile U64 *u64ptr; + const volatile S32 *s32ptr; + const volatile U32 *u32ptr; + const volatile S16 *s16ptr; + const volatile U16 *u16ptr; + const volatile S8 *s8ptr ; + const volatile U8 *u8ptr ; +} StructCVPtr; + +//! @} + +#endif // __AVR32_ABI_COMPILER__ + + +//_____ M A C R O S ________________________________________________________ + +/*! \name Usual Constants + */ +//! @{ +#define DISABLE 0 +#define ENABLE 1 +#ifndef __cplusplus +#if !defined(__bool_true_false_are_defined) +#define false 0 +#define true 1 +#endif +#endif +#define PASS 0 +#define FAIL 1 +#define LOW 0 +#define HIGH 1 +//! @} + + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +//! \name Optimization Control +//@{ + +/** + * \def likely(exp) + * \brief The expression \a exp is likely to be true + */ +#ifndef likely +# define likely(exp) (exp) +#endif + +/** + * \def unlikely(exp) + * \brief The expression \a exp is unlikely to be true + */ +#ifndef unlikely +# define unlikely(exp) (exp) +#endif + +/** + * \def is_constant(exp) + * \brief Determine if an expression evaluates to a constant value. + * + * \param exp Any expression + * + * \return true if \a exp is constant, false otherwise. + */ +#ifdef __GNUC__ +# define is_constant(exp) __builtin_constant_p(exp) +#else +# define is_constant(exp) (0) +#endif + +//! @} + +/*! \name Bit-Field Handling + */ +//! @{ + +/*! \brief Reads the bits of a value specified by a given bit-mask. + * + * \param value Value to read bits from. + * \param mask Bit-mask indicating bits to read. + * + * \return Read bits. + */ +#define Rd_bits( value, mask) ((value) & (mask)) + +/*! \brief Writes the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue to write bits to. + * \param mask Bit-mask indicating bits to write. + * \param bits Bits to write. + * + * \return Resulting value with written bits. + */ +#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\ + ((bits ) & (mask))) + +/*! \brief Tests the bits of a value specified by a given bit-mask. + * + * \param value Value of which to test bits. + * \param mask Bit-mask indicating bits to test. + * + * \return \c 1 if at least one of the tested bits is set, else \c 0. + */ +#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0) + +/*! \brief Clears the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to clear bits. + * \param mask Bit-mask indicating bits to clear. + * + * \return Resulting value with cleared bits. + */ +#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask)) + +/*! \brief Sets the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to set bits. + * \param mask Bit-mask indicating bits to set. + * + * \return Resulting value with set bits. + */ +#define Set_bits(lvalue, mask) ((lvalue) |= (mask)) + +/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to toggle bits. + * \param mask Bit-mask indicating bits to toggle. + * + * \return Resulting value with toggled bits. + */ +#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask)) + +/*! \brief Reads the bit-field of a value specified by a given bit-mask. + * + * \param value Value to read a bit-field from. + * \param mask Bit-mask indicating the bit-field to read. + * + * \return Read bit-field. + */ +#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask)) + +/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue to write a bit-field to. + * \param mask Bit-mask indicating the bit-field to write. + * \param bitfield Bit-field to write. + * + * \return Resulting value with written bit-field. + */ +#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask))) + +//! @} + + +/*! \brief This macro makes the CPU take a small break for a few cycles. This should + * be used when waiting for an event. It will reduce the internal bus load. + * + * "sub pc, pc, -4" (or "sub pc, -2") forces the IF stage to wait until the result + * of the calculation before it can fetch the next instruction. This makes sure + * there are nothing stuck in the LS pipe when you start a new iteration and guarante + * to flush the pipeline without having any other effect. + * (A nop doesn't have any effect on the IF stage.) + */ +#if (defined __GNUC__) +# define cpu_relax() __asm__ __volatile__("sub pc, pc, -4" ::: "memory", "cc") +#elif (defined __ICCAVR32__) +# define cpu_relax() __asm__ __volatile__("sub pc, pc, -4") +#endif + + +/*! \brief This macro is used to test fatal errors. + * + * The macro tests if the expression is false. If it is, a fatal error is + * detected and the application hangs up. + * + * \param expr Expression to evaluate and supposed to be nonzero. + */ +#ifdef _ASSERT_ENABLE_ + #define Assert(expr) \ + {\ + if (!(expr)) while (true);\ + } +#else + #define Assert(expr) ((void) 0) +#endif + + +/*! \name Zero-Bit Counting + * + * Under AVR32-GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + */ +//! @{ + +/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) + #define clz(u) __builtin_clz(u) +#elif (defined __ICCAVR32__) + #if (__VER__ == 330) && (__SUBVERSION__ <= 1) + // __count_leading_zeros is broken and returns a value which is offset by + // -32 when called with a constant parameter. + #define clz(v) (0 == v ? 32 : (31 & __count_leading_zeros(v))) + #else + #define clz(v) __count_leading_zeros(v) + #endif +#endif + +/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) + #define ctz(u) __builtin_ctz(u) +#elif (defined __ICCAVR32__) + #define ctz(u) __count_trailing_zeros(u) +#endif + +//! @} + +//! \name Logarithmic functions +//! @{ + +/** + * \internal + * Undefined function. Will cause a link failure if ilog2() is called + * with an invalid constant value. + */ +int_fast8_t ilog2_undefined(void); + +/** + * \brief Calculate the base-2 logarithm of a number rounded down to + * the nearest integer. + * + * \param x A 32-bit value + * \return The base-2 logarithm of \a x, or -1 if \a x is 0. + */ +static inline int_fast8_t ilog2(uint32_t x) +{ + if (is_constant(x)) + return ((x) & (1ULL << 31) ? 31 : + (x) & (1ULL << 30) ? 30 : + (x) & (1ULL << 29) ? 29 : + (x) & (1ULL << 28) ? 28 : + (x) & (1ULL << 27) ? 27 : + (x) & (1ULL << 26) ? 26 : + (x) & (1ULL << 25) ? 25 : + (x) & (1ULL << 24) ? 24 : + (x) & (1ULL << 23) ? 23 : + (x) & (1ULL << 22) ? 22 : + (x) & (1ULL << 21) ? 21 : + (x) & (1ULL << 20) ? 20 : + (x) & (1ULL << 19) ? 19 : + (x) & (1ULL << 18) ? 18 : + (x) & (1ULL << 17) ? 17 : + (x) & (1ULL << 16) ? 16 : + (x) & (1ULL << 15) ? 15 : + (x) & (1ULL << 14) ? 14 : + (x) & (1ULL << 13) ? 13 : + (x) & (1ULL << 12) ? 12 : + (x) & (1ULL << 11) ? 11 : + (x) & (1ULL << 10) ? 10 : + (x) & (1ULL << 9) ? 9 : + (x) & (1ULL << 8) ? 8 : + (x) & (1ULL << 7) ? 7 : + (x) & (1ULL << 6) ? 6 : + (x) & (1ULL << 5) ? 5 : + (x) & (1ULL << 4) ? 4 : + (x) & (1ULL << 3) ? 3 : + (x) & (1ULL << 2) ? 2 : + (x) & (1ULL << 1) ? 1 : + (x) & (1ULL << 0) ? 0 : + ilog2_undefined()); + + return 31 - clz(x); +} + +//! @} + +/*! \name Bit Reversing + */ +//! @{ + +/*! \brief Reverses the bits of \a u8. + * + * \param u8 U8 of which to reverse the bits. + * + * \return Value resulting from \a u8 with reversed bits. + */ +#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24)) + +/*! \brief Reverses the bits of \a u16. + * + * \param u16 U16 of which to reverse the bits. + * + * \return Value resulting from \a u16 with reversed bits. + */ +#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16)) + +/*! \brief Reverses the bits of \a u32. + * + * \param u32 U32 of which to reverse the bits. + * + * \return Value resulting from \a u32 with reversed bits. + */ +#if (defined __GNUC__) + #define bit_reverse32(u32) \ + (\ + {\ + unsigned int __value = (U32)(u32);\ + __asm__ ("brev\t%0" : "+r" (__value) : : "cc");\ + (U32)__value;\ + }\ + ) +#elif (defined __ICCAVR32__) + #define bit_reverse32(u32) ((U32)__bit_reverse((U32)(u32))) +#endif + +/*! \brief Reverses the bits of \a u64. + * + * \param u64 U64 of which to reverse the bits. + * + * \return Value resulting from \a u64 with reversed bits. + */ +#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\ + ((U64)bit_reverse32((U64)(u64)) << 32))) + +//! @} + + +/*! \name Alignment + */ +//! @{ + +/*! \brief Tests alignment of the number \a val with the \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0. + */ +#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) ) + +/*! \brief Gets alignment of the number \a val with respect to the \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Alignment of the number \a val with respect to the \a n boundary. + */ +#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) ) + +/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary. + * + * \param lval Input/output lvalue. + * \param n Boundary. + * \param alg Alignment. + * + * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary. + */ +#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) ) + +/*! \brief Aligns the number \a val with the upper \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Value resulting from the number \a val aligned with the upper \a n boundary. + */ +#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1)) + +/*! \brief Aligns the number \a val with the lower \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Value resulting from the number \a val aligned with the lower \a n boundary. + */ +#define Align_down(val, n ) ( (val) & ~((n) - 1)) + +//! @} + + +/*! \name Mathematics + * + * The same considerations as for clz and ctz apply here but AVR32-GCC does not + * provide built-in functions to access the assembly instructions abs, min and + * max and it does not produce them by itself in most cases, so two sets of + * macros are defined here: + * - Abs, Min and Max to apply to constant expressions (values known at + * compile time); + * - abs, min and max to apply to non-constant expressions (values unknown at + * compile time). + */ +//! @{ + +/*! \brief Takes the absolute value of \a a. + * + * \param a Input value. + * + * \return Absolute value of \a a. + * + * \note More optimized if only used with values known at compile time. + */ +#define Abs(a) (((a) < 0 ) ? -(a) : (a)) + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Min(a, b) (((a) < (b)) ? (a) : (b)) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Max(a, b) (((a) > (b)) ? (a) : (b)) + +/*! \brief Takes the absolute value of \a a. + * + * \param a Input value. + * + * \return Absolute value of \a a. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) + #define abs(a) \ + (\ + {\ + int __value = (a);\ + __asm__ ("abs\t%0" : "+r" (__value) : : "cc");\ + __value;\ + }\ + ) +#elif (defined __ICCAVR32__) + #define abs(a) Abs(a) +#endif + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) + #define min(a, b) \ + (\ + {\ + int __value, __arg_a = (a), __arg_b = (b);\ + __asm__ ("min\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\ + __value;\ + }\ + ) +#elif (defined __ICCAVR32__) + #define min(a, b) __min(a, b) +#endif + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) + #define max(a, b) \ + (\ + {\ + int __value, __arg_a = (a), __arg_b = (b);\ + __asm__ ("max\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\ + __value;\ + }\ + ) +#elif (defined __ICCAVR32__) + #define max(a, b) __max(a, b) +#endif + +//! @} + + +/*! \brief Calls the routine at address \a addr. + * + * It generates a long call opcode. + * + * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if + * it is invoked from the CPU supervisor mode. + * + * \param addr Address of the routine to call. + * + * \note It may be used as a long jump opcode in some special cases. + */ +#define Long_call(addr) ((*(void (*)(void))(addr))()) + +/*! \brief Resets the CPU by software. + * + * \warning It shall not be called from the CPU application mode. + */ +#if (defined __GNUC__) + #define Reset_CPU() \ + (\ + {\ + __asm__ __volatile__ (\ + "lddpc r9, 3f\n\t"\ + "mfsr r8, %[SR]\n\t"\ + "bfextu r8, r8, %[SR_M_OFFSET], %[SR_M_SIZE]\n\t"\ + "cp.w r8, 0b001\n\t"\ + "breq 0f\n\t"\ + "sub r8, pc, $ - 1f\n\t"\ + "pushm r8-r9\n\t"\ + "rete\n"\ + "0:\n\t"\ + "mtsr %[SR], r9\n"\ + "1:\n\t"\ + "mov r0, 0\n\t"\ + "mov r1, 0\n\t"\ + "mov r2, 0\n\t"\ + "mov r3, 0\n\t"\ + "mov r4, 0\n\t"\ + "mov r5, 0\n\t"\ + "mov r6, 0\n\t"\ + "mov r7, 0\n\t"\ + "mov r8, 0\n\t"\ + "mov r9, 0\n\t"\ + "mov r10, 0\n\t"\ + "mov r11, 0\n\t"\ + "mov r12, 0\n\t"\ + "mov sp, 0\n\t"\ + "stdsp sp[0], sp\n\t"\ + "ldmts sp, sp\n\t"\ + "mov lr, 0\n\t"\ + "lddpc pc, 2f\n\t"\ + ".balign 4\n"\ + "2:\n\t"\ + ".word _start\n"\ + "3:\n\t"\ + ".word %[RESET_SR]"\ + :\ + : [SR] "i" (AVR32_SR),\ + [SR_M_OFFSET] "i" (AVR32_SR_M_OFFSET),\ + [SR_M_SIZE] "i" (AVR32_SR_M_SIZE),\ + [RESET_SR] "i" (AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))\ + );\ + }\ + ) +#elif (defined __ICCAVR32__) + #define Reset_CPU() \ + {\ + extern void *volatile __program_start;\ + __asm__ __volatile__ (\ + "mov r7, LWRD(__program_start)\n\t"\ + "orh r7, HWRD(__program_start)\n\t"\ + "mov r9, LWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))")\n\t"\ + "orh r9, HWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))")\n\t"\ + "mfsr r8, "ASTRINGZ(AVR32_SR)"\n\t"\ + "bfextu r8, r8, "ASTRINGZ(AVR32_SR_M_OFFSET)", "ASTRINGZ(AVR32_SR_M_SIZE)"\n\t"\ + "cp.w r8, 001b\n\t"\ + "breq $ + 10\n\t"\ + "sub r8, pc, -12\n\t"\ + "pushm r8-r9\n\t"\ + "rete\n\t"\ + "mtsr "ASTRINGZ(AVR32_SR)", r9\n\t"\ + "mov r0, 0\n\t"\ + "mov r1, 0\n\t"\ + "mov r2, 0\n\t"\ + "mov r3, 0\n\t"\ + "mov r4, 0\n\t"\ + "mov r5, 0\n\t"\ + "mov r6, 0\n\t"\ + "st.w r0[4], r7\n\t"\ + "mov r7, 0\n\t"\ + "mov r8, 0\n\t"\ + "mov r9, 0\n\t"\ + "mov r10, 0\n\t"\ + "mov r11, 0\n\t"\ + "mov r12, 0\n\t"\ + "mov sp, 0\n\t"\ + "stdsp sp[0], sp\n\t"\ + "ldmts sp, sp\n\t"\ + "mov lr, 0\n\t"\ + "ld.w pc, lr[4]"\ + );\ + __program_start;\ + } +#endif + + + +/*! \name CPU Status Register Access + */ +//! @{ + +/*! \brief Tells whether exceptions are globally enabled. + * + * \return \c 1 if exceptions are globally enabled, else \c 0. + */ +#define Is_global_exception_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_EM_MASK)) + +/*! \brief Disables exceptions globally. + */ +#if (defined __GNUC__) + #define Disable_global_exception() ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));}) +#elif (defined __ICCAVR32__) + #define Disable_global_exception() (__set_status_flag(AVR32_SR_EM_OFFSET)) +#endif + +/*! \brief Enables exceptions globally. + */ +#if (defined __GNUC__) + #define Enable_global_exception() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));}) +#elif (defined __ICCAVR32__) + #define Enable_global_exception() (__clear_status_flag(AVR32_SR_EM_OFFSET)) +#endif + +//! @} + + +/*! \name Debug Register Access + */ +//! @{ + +/*! \brief Gets the value of the \a dbgreg debug register. + * + * \param dbgreg Address of the debug register of which to get the value. + * + * \return Value of the \a dbgreg debug register. + */ +#if (defined __GNUC__) + #define Get_debug_register(dbgreg) __builtin_mfdr(dbgreg) +#elif (defined __ICCAVR32__) + #define Get_debug_register(dbgreg) __get_debug_register(dbgreg) +#endif + +/*! \brief Sets the value of the \a dbgreg debug register to \a value. + * + * \param dbgreg Address of the debug register of which to set the value. + * \param value Value to set the \a dbgreg debug register to. + */ +#if (defined __GNUC__) + #define Set_debug_register(dbgreg, value) __builtin_mtdr(dbgreg, value) +#elif (defined __ICCAVR32__) + #define Set_debug_register(dbgreg, value) __set_debug_register(dbgreg, value) +#endif + +//! @} + + +/*! \name Force Assembly Inline Code Section + */ +//! @{ +#if (defined __GNUC__) +#define __always_inline __attribute__((__always_inline__)) +#elif (defined __ICCAVR32__) +#define __always_inline _Pragma("inline=forced") +#endif +//! @} + +/*! \name MCU Endianism Handling + * AVR32 is MCU big endianism. + */ +//! @{ +#define MSB(u16) (((U8 *)&(u16))[0]) //!< Most significant byte of \a u16. +#define LSB(u16) (((U8 *)&(u16))[1]) //!< Least significant byte of \a u16. + +#define MSH(u32) (((U16 *)&(u32))[0]) //!< Most significant half-word of \a u32. +#define LSH(u32) (((U16 *)&(u32))[1]) //!< Least significant half-word of \a u32. +#define MSB0W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 1st rank of \a u32. +#define MSB1W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 2nd rank of \a u32. +#define MSB2W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 3rd rank of \a u32. +#define MSB3W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 4th rank of \a u32. +#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32. +#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32. +#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32. +#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32. + +#define MSW(u64) (((U32 *)&(u64))[0]) //!< Most significant word of \a u64. +#define LSW(u64) (((U32 *)&(u64))[1]) //!< Least significant word of \a u64. +#define MSH0(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 1st rank of \a u64. +#define MSH1(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 2nd rank of \a u64. +#define MSH2(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 3rd rank of \a u64. +#define MSH3(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 4th rank of \a u64. +#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64. +#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64. +#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64. +#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64. +#define MSB0D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 1st rank of \a u64. +#define MSB1D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 2nd rank of \a u64. +#define MSB2D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 3rd rank of \a u64. +#define MSB3D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 4th rank of \a u64. +#define MSB4D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 5th rank of \a u64. +#define MSB5D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 6th rank of \a u64. +#define MSB6D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 7th rank of \a u64. +#define MSB7D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 8th rank of \a u64. +#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64. +#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64. +#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64. +#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64. +#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64. +#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64. +#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64. +#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64. + +#define LE16(x) Swap16(x) +#define le16_to_cpu(x) swap16(x) +#define cpu_to_le16(x) swap16(x) +#define LE16_TO_CPU(x) Swap16(x) +#define CPU_TO_LE16(x) Swap16(x) + +#define be16_to_cpu(x) (x) +#define cpu_to_be16(x) (x) +#define BE16_TO_CPU(x) (x) +#define CPU_TO_BE16(x) (x) + +#define le32_to_cpu(x) swap32(x) +#define cpu_to_le32(x) swap32(x) +#define LE32_TO_CPU(x) Swap32(x) +#define CPU_TO_LE32(x) Swap32(x) + +#define be32_to_cpu(x) (x) +#define cpu_to_be32(x) (x) +#define BE32_TO_CPU(x) (x) +#define CPU_TO_BE32(x) (x) +//! @} + + +/*! \name Endianism Conversion + * + * The same considerations as for clz and ctz apply here but AVR32-GCC's + * __builtin_bswap_16 and __builtin_bswap_32 do not behave like macros when + * applied to constant expressions, so two sets of macros are defined here: + * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known + * at compile time); + * - swap16, swap32 and swap64 to apply to non-constant expressions (values + * unknown at compile time). + */ +//! @{ + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\ + ((U16)(u16) << 8))) + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\ + ((U32)Swap16((U32)(u32)) << 16))) + +/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). + * + * \param u64 U64 of which to toggle the endianism. + * + * \return Value resulting from \a u64 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\ + ((U64)Swap32((U64)(u64)) << 32))) + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) +# if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ + #define swap16(u16) ((U16)__builtin_bswap_16((U16)(u16))) +# else + // swap_16 must be not used when GCC's -Os command option is used + #define swap16(u16) Swap16(u16) +# endif +#elif (defined __ICCAVR32__) + #define swap16(u16) ((U16)__swap_bytes_in_halfwords((U16)(u16))) +#endif + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) + #define swap32(u32) ((U32)__builtin_bswap_32((U32)(u32))) +#elif (defined __ICCAVR32__) + #define swap32(u32) ((U32)__swap_bytes((U32)(u32))) +#endif + +/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). + * + * \param u64 U64 of which to toggle the endianism. + * + * \return Value resulting from \a u64 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\ + ((U64)swap32((U64)(u64)) << 32))) + +//! @} + + +/*! \name Target Abstraction + */ +//! @{ + +#define _GLOBEXT_ extern //!< extern storage-class specifier. +#define _CONST_TYPE_ const //!< const type qualifier. +#define _MEM_TYPE_SLOW_ //!< Slow memory type. +#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type. +#define _MEM_TYPE_FAST_ //!< Fast memory type. + +typedef U8 Byte; //!< 8-bit unsigned integer. + +#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM. +#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM. +#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM. +#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM. + +#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32. +#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32. +#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32. +#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32. +#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32. +#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32. +#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32. +#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32. + +//! @} + +#endif // __AVR32_ABI_COMPILER__ + + +#endif // _COMPILER_AVR32_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/linker_scripts/at32uc3c/0512c/gcc/link_uc3c0512c.lds b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/linker_scripts/at32uc3c/0512c/gcc/link_uc3c0512c.lds new file mode 100644 index 0000000..a3c3cc8 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/linker_scripts/at32uc3c/0512c/gcc/link_uc3c0512c.lds @@ -0,0 +1,288 @@ +/****************************************************************************** + * AVR32 AT32UC3C0512C GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3C0512C + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00080000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC + HRAM0 (wxa!ri) : ORIGIN = 0xA0000000, LENGTH = 0x00001000 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM_ALIGN PT_NULL; + INTRAM_AT_FLASH PT_LOAD; + INTRAM PT_NULL; + HRAM0_AT_FLASH PT_LOAD; + HRAM0 PT_NULL; + USERPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM_ALIGN + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .ramtext : { *(.ramtext .ramtext.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .ddalign : { . = ALIGN(8); } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :INTRAM_AT_FLASH + .balign : { . = ALIGN(8); PROVIDE(_edata = .); } >INTRAM AT>FLASH :INTRAM_AT_FLASH + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + + . = ORIGIN(HRAM0); + .data_hram0 ORIGIN(HRAM0) : AT ( LOADADDR(.balign) + SIZEOF (.balign) ) + { + PROVIDE(_data_hram0 = .); + *(.data_hram0) + . = ALIGN(8); + PROVIDE(_edata_hram0 = .); + } >HRAM0 :HRAM0_AT_FLASH + + PROVIDE(_data_hram0_lma = ABSOLUTE(LOADADDR(.data_hram0))); + + . = ALIGN(8); + .bss_hram0 : + { + PROVIDE(__bss_hram0_start = .); + *(.bss_hram0) + PROVIDE(_bss_hram0_end = .); + } >HRAM0 AT>HRAM0 :HRAM0 + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/parts.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/parts.h new file mode 100644 index 0000000..91994b4 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/parts.h @@ -0,0 +1,253 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Arch file for AVR32. + * + * This file defines common AVR32 UC3 series. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _ARCH_H_ +#define _ARCH_H_ + +// UC3 A Series +#define UC3A0 (( defined (__GNUC__) && \ + ( defined (__AVR32_UC3A0128__) || \ + defined (__AVR32_UC3A0256__) || \ + defined (__AVR32_UC3A0512__) || \ + defined (__AVR32_UC3A0512ES__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3A0128__) || \ + defined (__AT32UC3A0256__) || \ + defined (__AT32UC3A0512__) || \ + defined (__AT32UC3A0512ES__)))) + +#define UC3A1 (( defined (__GNUC__) && \ + ( defined (__AVR32_UC3A1128__) || \ + defined (__AVR32_UC3A1256__) || \ + defined (__AVR32_UC3A1512__) || \ + defined (__AVR32_UC3A1512ES__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3A1128__) || \ + defined (__AT32UC3A1256__) || \ + defined (__AT32UC3A1512__) || \ + defined (__AT32UC3A1512ES__)))) + +#define UC3A3 (( defined (__GNUC__) && \ + ( defined (__AVR32_UC3A364__) || \ + defined (__AVR32_UC3A364S__) || \ + defined (__AVR32_UC3A3128__) || \ + defined (__AVR32_UC3A3128S__) || \ + defined (__AVR32_UC3A3256__) || \ + defined (__AVR32_UC3A3256S__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3A364__) || \ + defined (__AT32UC3A364S__) || \ + defined (__AT32UC3A3128__) || \ + defined (__AT32UC3A3128S__) || \ + defined (__AT32UC3A3256__) || \ + defined (__AT32UC3A3256S__)))) + +#define UC3A4 (( defined (__GNUC__) && \ + ( defined (__AVR32_UC3A464__) || \ + defined (__AVR32_UC3A464S__) || \ + defined (__AVR32_UC3A4128__) || \ + defined (__AVR32_UC3A4128S__) || \ + defined (__AVR32_UC3A4256__) || \ + defined (__AVR32_UC3A4256S__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3A464__) || \ + defined (__AT32UC3A464S__) || \ + defined (__AT32UC3A4128__) || \ + defined (__AT32UC3A4128S__) || \ + defined (__AT32UC3A4256__) || \ + defined (__AT32UC3A4256S__)))) + +#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4) + +// UC3 B Series +#define UC3B0 (( defined (__GNUC__) && \ + ( defined (__AVR32_UC3B064__) || \ + defined (__AVR32_UC3B0128__) || \ + defined (__AVR32_UC3B0256__) || \ + defined (__AVR32_UC3B0256ES__) || \ + defined (__AVR32_UC3B0512__) || \ + defined (__AVR32_UC3B0512REVC_))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3B064__) || \ + defined (__AT32UC3B0128__) || \ + defined (__AT32UC3B0256__) || \ + defined (__AT32UC3B0256ES__) || \ + defined (__AT32UC3B0512__) || \ + defined (__AT32UC3B0512REVC__)))) + +#define UC3B1 (( defined (__GNUC__) && \ + ( defined (__AVR32_UC3B164__) || \ + defined (__AVR32_UC3B1128__) || \ + defined (__AVR32_UC3B1256__) || \ + defined (__AVR32_UC3B1256ES__) || \ + defined (__AVR32_UC3B1512__) || \ + defined (__AVR32_UC3B1512ES__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3B164__) || \ + defined (__AT32UC3B1128__) || \ + defined (__AT32UC3B1256__) || \ + defined (__AT32UC3B1256ES__) || \ + defined (__AT32UC3B1512__) || \ + defined (__AT32UC3B1512REVC__)))) + +#define UC3B (UC3B0 || UC3B1 ) + +// UC3 C Series +#define UC3C0_REVC (( defined (__GNUC__) && \ + ( defined (__AVR32_UC3C064CREVC__) || \ + defined (__AVR32_UC3C0128CREVC__) || \ + defined (__AVR32_UC3C0256CREVC__) || \ + defined (__AVR32_UC3C0512CREVC__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3C064CREVC__) || \ + defined (__AT32UC3C0128CREVC__) || \ + defined (__AT32UC3C0256CREVC__) || \ + defined (__AT32UC3C0512CREVC__)))) + +#define UC3C0 (( defined (__GNUC__) && \ + ( defined (__AVR32_UC3C064C__) || \ + defined (__AVR32_UC3C0128C__) || \ + defined (__AVR32_UC3C0256C__) || \ + defined (__AVR32_UC3C0512C__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3C064C__) || \ + defined (__AT32UC3C0128C__) || \ + defined (__AT32UC3C0256C__) || \ + defined (__AT32UC3C0512C__)))) + +#define UC3C1_REVC (( defined (__GNUC__) && \ + ( defined (__AVR32_UC3C164CREVC__) || \ + defined (__AVR32_UC3C1128CREVC__) || \ + defined (__AVR32_UC3C1256CREVC__) || \ + defined (__AVR32_UC3C1512CREVC__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3C164CREVC__) || \ + defined (__AT32UC3C1128CREVC__) || \ + defined (__AT32UC3C1256CREVC__) || \ + defined (__AT32UC3C1512CREVC__)))) + +#define UC3C1 (( defined (__GNUC__) && \ + ( defined (__AVR32_UC3C164C__) || \ + defined (__AVR32_UC3C1128C__) || \ + defined (__AVR32_UC3C1256C__) || \ + defined (__AVR32_UC3C1512C__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3C164C__) || \ + defined (__AT32UC3C1128C__) || \ + defined (__AT32UC3C1256C__) || \ + defined (__AT32UC3C1512C__)))) + +#define UC3C2_REVC (( defined (__GNUC__) && \ + ( defined (__AVR32_UC3C264CREVC__) || \ + defined (__AVR32_UC3C2128CREVC__) || \ + defined (__AVR32_UC3C2256CREVC__) || \ + defined (__AVR32_UC3C2512CREVC__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3C264CREVC__) || \ + defined (__AT32UC3C2128CREVC__) || \ + defined (__AT32UC3C2256CREVC__) || \ + defined (__AT32UC3C2512CREVC__)))) + +#define UC3C2 (( defined (__GNUC__) && \ + ( defined (__AVR32_UC3C264C__) || \ + defined (__AVR32_UC3C2128C__) || \ + defined (__AVR32_UC3C2256C__) || \ + defined (__AVR32_UC3C2512C__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3C264C__) || \ + defined (__AT32UC3C2128C__) || \ + defined (__AT32UC3C2256C__) || \ + defined (__AT32UC3C2512C__)))) + +#define UC3C_REVC (UC3C0_REVC || UC3C1_REVC || UC3C2_REVC) +#define UC3C (UC3C0 || UC3C0_REVC || UC3C1 || UC3C1_REVC || UC3C2 || UC3C2_REVC) + +// UC3 L Device series +#define UC3L0 (( defined (__GNUC__) && \ + ( defined (__AVR32_UC3L016__) || \ + defined (__AVR32_UC3L032__) || \ + defined (__AVR32_UC3L064__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3L016__) || \ + defined (__AT32UC3L032__) || \ + defined (__AT32UC3L064__)))) + +#define UC3L0128 (( defined (__GNUC__) && \ + ( defined (__AVR32_UC3L0128__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3L0128__)))) + +#define UC3L0256 (( defined (__GNUC__) && \ + ( defined (__AVR32_UC3L0256__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__AT32UC3L0256__)))) + +#define UC3L ( UC3L0 || UC3L0128 || UC3L0256 ) + +// UC3 D Device series +#define UC3D3 (( defined (__GNUC__) && \ + ( defined (__AVR32_UC128D3__) || \ + defined (__AVR32_UC64D3__))) \ + ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \ + ( defined (__ATUC128D3__) || \ + defined (__ATUC64D3__) ))) + +#define UC3D (UC3D3) + +#if (UC3D) +#include "header_files/uc3d_defines_fix.h" +#endif + +#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L) + +#if ((defined __GNUC__) && (defined __AVR32__)) || (defined __ICCAVR32__ || defined __AAVR32__) +# if (UC3) +# include +# endif +#endif + +#endif // _ARCH_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/mrepeat.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/mrepeat.h new file mode 100644 index 0000000..92b81ae --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/mrepeat.h @@ -0,0 +1,326 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor macro repeating utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _MREPEAT_H_ +#define _MREPEAT_H_ + +#include "preprocessor.h" + + +//! Maximal number of repetitions supported by MREPEAT. +#define MREPEAT_LIMIT 256 + +/*! \brief Macro repeat. + * + * This macro represents a horizontal repetition construct. + * + * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT. + * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with + * the current repetition number and the auxiliary data argument. + * \param data Auxiliary data passed to macro. + * + * \return macro(0, data) macro(1, data) ... macro(count - 1, data) + */ +#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data) + +#define MREPEAT0( macro, data) +#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data) +#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data) +#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data) +#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data) +#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data) +#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data) +#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data) +#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data) +#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data) +#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data) +#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data) +#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data) +#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data) +#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data) +#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data) +#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data) +#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data) +#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data) +#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data) +#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data) +#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data) +#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data) +#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data) +#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data) +#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data) +#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data) +#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data) +#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data) +#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data) +#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data) +#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data) +#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data) +#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data) +#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data) +#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data) +#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data) +#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data) +#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data) +#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data) +#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data) +#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data) +#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data) +#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data) +#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data) +#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data) +#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data) +#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data) +#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data) +#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data) +#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data) +#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data) +#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data) +#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data) +#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data) +#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data) +#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data) +#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data) +#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data) +#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data) +#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data) +#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data) +#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data) +#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data) +#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data) +#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data) +#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data) +#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data) +#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data) +#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data) +#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data) +#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data) +#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data) +#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data) +#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data) +#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data) +#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data) +#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data) +#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data) +#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data) +#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data) +#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data) +#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data) +#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data) +#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data) +#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data) +#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data) +#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data) +#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data) +#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data) +#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data) +#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data) +#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data) +#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data) +#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data) +#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data) +#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data) +#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data) +#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data) +#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data) +#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data) +#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data) +#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data) +#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data) +#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data) +#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data) +#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data) +#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data) +#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data) +#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data) +#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data) +#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data) +#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data) +#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data) +#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data) +#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data) +#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data) +#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data) +#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data) +#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data) +#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data) +#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data) +#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data) +#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data) +#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data) +#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data) +#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data) +#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data) +#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data) +#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data) +#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data) +#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data) +#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data) +#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data) +#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data) +#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data) +#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data) +#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data) +#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data) +#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data) +#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data) +#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data) +#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data) +#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data) +#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data) +#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data) +#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data) +#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data) +#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data) +#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data) +#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data) +#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data) +#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data) +#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data) +#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data) +#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data) +#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data) +#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data) +#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data) +#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data) +#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data) +#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data) +#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data) +#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data) +#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data) +#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data) +#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data) +#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data) +#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data) +#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data) +#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data) +#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data) +#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data) +#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data) +#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data) +#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data) +#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data) +#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data) +#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data) +#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data) +#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data) +#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data) +#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data) +#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data) +#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data) +#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data) +#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data) +#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data) +#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data) +#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data) +#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data) +#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data) +#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data) +#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data) +#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data) +#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data) +#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data) +#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data) +#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data) +#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data) +#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data) +#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data) +#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data) +#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data) +#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data) +#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data) +#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data) +#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data) +#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data) +#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data) +#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data) +#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data) +#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data) +#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data) +#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data) +#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data) +#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data) +#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data) +#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data) +#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data) +#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data) +#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data) +#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data) +#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data) +#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data) +#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data) +#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data) +#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data) +#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data) +#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data) +#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data) +#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data) +#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data) +#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data) +#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data) +#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data) +#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data) +#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data) +#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data) +#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data) +#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data) +#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data) +#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data) +#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data) +#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data) +#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data) +#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data) +#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data) +#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data) +#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data) +#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data) +#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data) +#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data) +#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data) +#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data) +#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data) +#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data) + + +#endif // _MREPEAT_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/preprocessor.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/preprocessor.h new file mode 100644 index 0000000..32677c9 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/preprocessor.h @@ -0,0 +1,53 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _PREPROCESSOR_H_ +#define _PREPROCESSOR_H_ + +#include "tpaste.h" +#include "stringz.h" +#include "mrepeat.h" + + +#endif // _PREPROCESSOR_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/stringz.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/stringz.h new file mode 100644 index 0000000..4773d07 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/stringz.h @@ -0,0 +1,73 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor stringizing utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _STRINGZ_H_ +#define _STRINGZ_H_ + + +/*! \brief Stringize. + * + * Stringize a preprocessing token, this token being allowed to be \#defined. + * + * May be used only within macros with the token passed as an argument if the token is \#defined. + * + * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN) + * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to + * writing "A0". + */ +#define STRINGZ(x) #x + +/*! \brief Absolute stringize. + * + * Stringize a preprocessing token, this token being allowed to be \#defined. + * + * No restriction of use if the token is \#defined. + * + * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is + * equivalent to writing "A0". + */ +#define ASTRINGZ(x) STRINGZ(x) + + +#endif // _STRINGZ_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/tpaste.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/tpaste.h new file mode 100644 index 0000000..26a7d95 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/preprocessor/tpaste.h @@ -0,0 +1,93 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor token pasting utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _TPASTE_H_ +#define _TPASTE_H_ + + +/*! \name Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * May be used only within macros with the tokens passed as arguments if the tokens are \#defined. + * + * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by + * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is + * equivalent to writing U32. + */ +//! @{ +#define TPASTE2( a, b) a##b +#define TPASTE3( a, b, c) a##b##c +#define TPASTE4( a, b, c, d) a##b##c##d +#define TPASTE5( a, b, c, d, e) a##b##c##d##e +#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f +#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g +#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h +#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i +#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j +//! @} + +/*! \name Absolute Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * No restriction of use if the tokens are \#defined. + * + * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined + * as 32 is equivalent to writing U32. + */ +//! @{ +#define ATPASTE2( a, b) TPASTE2( a, b) +#define ATPASTE3( a, b, c) TPASTE3( a, b, c) +#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d) +#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e) +#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f) +#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g) +#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h) +#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i) +#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j) +//! @} + + +#endif // _TPASTE_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/startup/startup_uc3.S b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/startup/startup_uc3.S new file mode 100644 index 0000000..0b94189 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/startup/startup_uc3.S @@ -0,0 +1,118 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AVR32UC C runtime startup file. + * + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32UC devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include + + +//! @{ +//! \verbatim + + + // This must be linked @ 0x80000000 if it is to be run upon reset. + .section .reset, "ax", @progbits + + + .global _start + .type _start, @function +_start: + // Jump to the C runtime startup routine. + lda.w pc, _stext + + + // _stext is placed outside the .reset section so that the program entry point + // can be changed without affecting the C runtime startup. + .section .text._stext, "ax", @progbits + + + .global _stext + .type _stext, @function +_stext: + // Set initial stack pointer. + lda.w sp, _estack + + // Set up EVBA so interrupts can be enabled. + lda.w r0, _evba + mtsr AVR32_EVBA, r0 + + // Enable the exception processing. + csrf AVR32_SR_EM_OFFSET + + // Load initialized data having a global lifetime from the data LMA. + lda.w r0, _data + lda.w r1, _edata + cp r0, r1 + brhs idata_load_loop_end + lda.w r2, _data_lma +idata_load_loop: + ld.d r4, r2++ + st.d r0++, r4 + cp r0, r1 + brlo idata_load_loop +idata_load_loop_end: + + // Clear uninitialized data having a global lifetime in the blank static storage section. + lda.w r0, __bss_start + lda.w r1, _end + cp r0, r1 + brhs udata_clear_loop_end + mov r2, 0 + mov r3, 0 +udata_clear_loop: + st.d r0++, r2 + cp r0, r1 + brlo udata_clear_loop +udata_clear_loop_end: + +#ifdef CONFIG_FRAME_POINTER + // Safety: Set the default "return" @ to the exit routine address. + lda.w lr, exit +#endif + + // Start the show. + lda.w pc, main + + +//! \endverbatim +//! @} diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/startup/trampoline_uc3.S b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/startup/trampoline_uc3.S new file mode 100644 index 0000000..7ccd36b --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/startup/trampoline_uc3.S @@ -0,0 +1,75 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AVR32 UC3 ISP trampoline. + * + * In order to be able to program a project with both BatchISP and JTAGICE mkII + * without having to take the general-purpose fuses into consideration, add this + * file to the project and change the program entry point to _trampoline. + * + * The pre-programmed ISP will be erased if JTAGICE mkII is used. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32UC devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#include "trampoline_uc3.h" + + +//! @{ +//! \verbatim + + + // This must be linked @ 0x80000000 if it is to be run upon reset. + .section .reset, "ax", @progbits + + + .global _trampoline + .type _trampoline, @function +_trampoline: + // Jump to program start. + rjmp program_start + + .org PROGRAM_START_OFFSET +program_start: + // Jump to the C runtime startup routine. + lda.w pc, _stext + + +//! \endverbatim +//! @} diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/startup/trampoline_uc3.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/startup/trampoline_uc3.h new file mode 100644 index 0000000..575815d --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/startup/trampoline_uc3.h @@ -0,0 +1,52 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ****************************************************************** + * + * \brief UC3 trampoline definitions (default size is 8KB) + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR UC3 devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ***************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _TRAMPOLINE_UC3_H_ +#define _TRAMPOLINE_UC3_H_ + +#define PROGRAM_START_ADDRESS (AVR32_FLASH_ADDRESS + PROGRAM_START_OFFSET) +#define PROGRAM_START_OFFSET 0x00002000 + +#endif // _TRAMPOLINE_UC3_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/status_codes.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/status_codes.h new file mode 100644 index 0000000..b4ddac5 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/avr32/utils/status_codes.h @@ -0,0 +1,81 @@ +/** + * \file + * + * \brief Status code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (C) 2009 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#ifndef STATUS_CODES_H_INCLUDED +#define STATUS_CODES_H_INCLUDED + +/** + * Status code that may be returned by shell commands and protocol + * implementations. + * + * \note Any change to these status codes and the corresponding + * message strings is strictly forbidden. New codes can be added, + * however, but make sure that any message string tables are updated + * at the same time. + */ +enum status_code { + STATUS_OK = 0, //!< Success + ERR_IO_ERROR = -1, //!< I/O error + ERR_FLUSHED = -2, //!< Request flushed from queue + ERR_TIMEOUT = -3, //!< Operation timed out + ERR_BAD_DATA = -4, //!< Data integrity check failed + ERR_PROTOCOL = -5, //!< Protocol error + ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device + ERR_NO_MEMORY = -7, //!< Insufficient memory + ERR_INVALID_ARG = -8, //!< Invalid argument + ERR_BAD_ADDRESS = -9, //!< Bad address + ERR_BUSY = -10, //!< Resource is busy + ERR_BAD_FORMAT = -11, //!< Data format not recognized + + /** + * \brief Operation in progress + * + * This status code is for driver-internal use when an operation + * is currently being performed. + * + * \note Drivers should never return this status code to any + * callers. It is strictly for internal use. + */ + OPERATION_IN_PROGRESS = -128, +}; + +typedef enum status_code status_code_t; + +#endif /* STATUS_CODES_H_INCLUDED */ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/boards/board.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/boards/board.h new file mode 100644 index 0000000..5f80777 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/boards/board.h @@ -0,0 +1,196 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Standard board header file. + * + * This file includes the appropriate board header file according to the + * defined board (parameter BOARD). + * + * - Compiler: IAR EWAVR/IAR EWAVR32 and GNU GCC for AVR or AVR32 + * - Supported devices: All AVR devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/*! \name Base Boards + */ +//! @{ +#define EVK1100 1 //!< AT32UC3A EVK1100 board. +#define EVK1101 2 //!< AT32UC3B EVK1101 board. +#define UC3C_EK 3 //!< AT32UC3C UC3C_EK board. +#define EVK1104 4 //!< AT32UC3A3 EVK1104 board. +#define EVK1105 5 //!< AT32UC3A EVK1105 board. +#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board. +#define UC3L_EK 7 //!< AT32UC3L-EK board. +#define XPLAIN 8 //!< ATxmega128A1 Xplain board. +#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board. +#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board. +#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board. +#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board. +#define STK600_RCUC3D 16 //!< STK600 RCUC3D board. +#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board. +#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board. +#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board +#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board +#define STK600_RC044X 24 //!< STK600 with RC044X routing card board. +#define STK600_RCUC3B 25 //!< STK600 RCUC3B board. +#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board. +#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices +#define AVR_SIMULATOR_UC3 98 //!< AVR SIMULATOR for AVR UC3 device family. +#define USER_BOARD 99 //!< User-reserved board (if any). +#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader) +//! @} + +/*! \name Extension Boards + */ +//! @{ +#define EXT1102 1 //!< AT32UC3B EXT1102 board +#define MC300 2 //!< AT32UC3 MC300 board +#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1 +#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2 +#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board +#define SENSORS_XPLAINED_LIGHT_1 6 //!< Xplained light & proximity sensor board +#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A" + +#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any). +//! @} + +#if BOARD == EVK1100 + #include "evk1100/evk1100.h" +#elif BOARD == EVK1101 + #include "evk1101/evk1101.h" +#elif BOARD == UC3C_EK + #include "uc3c_ek/uc3c_ek.h" +#elif BOARD == EVK1104 + #include "evk1104/evk1104.h" +#elif BOARD == EVK1105 + #include "evk1105/evk1105.h" +#elif BOARD == STK600_RCUC3L0 + #include "stk600/rcuc3l0/stk600_rcuc3l0.h" +#elif BOARD == UC3L_EK + #include "uc3l_ek/uc3l_ek.h" +#elif BOARD == XPLAIN + #include "xplain/xplain.h" +#elif BOARD == STK600_RC044X + #include "stk600/rc044x/stk600_rc044x.h" +#elif BOARD == STK600_RC064X + #include "stk600/rc064x/stk600_rc064x.h" +#elif BOARD == STK600_RC100X + #include "stk600/rc100x/stk600_rc100x.h" +#elif BOARD == UC3_A3_XPLAINED + #include "uc3_a3_xplained/uc3_a3_xplained.h" +#elif BOARD == UC3_L0_XPLAINED + #include "uc3_l0_xplained/uc3_l0_xplained.h" +#elif BOARD == STK600_RCUC3B + #include "stk600/rcuc3b/stk600_rcuc3b.h" +#elif BOARD == STK600_RCUC3D + #include "stk600/rcuc3d/stk600_rcuc3d.h" +#elif BOARD == STK600_RCUC3C0 + #include "stk600/rcuc3c0/stk600_rcuc3c0.h" +#elif BOARD == XMEGA_A1_XPLAINED + #include "xmega_a1_xplained/xmega_a1_xplained.h" +#elif BOARD == UC3_L0_XPLAINED_BC + #include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h" +#elif BOARD == MEGA1284P_XPLAINED_BC + #include "mega1284p_xplained_bc/mega1284p_xplained_bc.h" +#elif BOARD == UC3_L0_QT600 + #include "uc3_l0_qt600/uc3_l0_qt600.h" +#elif BOARD == SIMULATOR_XMEGA_A1 + #include "simulator/xmega_a1/simulator_xmega_a1.h" +#elif BOARD == AVR_SIMULATOR_UC3 + #include "avr_simulator_uc3/avr_simulator_uc3.h" +#elif BOARD == USER_BOARD + // User-reserved area: #include the header file of your board here (if any). + #include "user_board.h" +#elif BOARD == DUMMY_BOARD + #include "dummy/dummy_board.h" +#else + #error No known AVR board defined +#endif + +#if (defined EXT_BOARD) + #if EXT_BOARD == MC300 + #include "mc300/mc300.h" + #elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \ + (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \ + (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \ + (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \ + (EXT_BOARD == SENSORS_XPLAINED_LIGHT_1) + #include "sensors_xplained/sensors_xplained.h" + #elif EXT_BOARD == USER_EXT_BOARD + // User-reserved area: #include the header file of your extension board here + // (if any). + #endif +#endif + + +#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__)) +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +/*! \brief This function initializes the board target resources + * + * This function should be called to ensure proper initialization of the target + * board hardware connected to the part. + */ +extern void board_init(void); + +#endif // #ifdef __AVR32_ABI_COMPILER__ +#else +/*! \brief This function initializes the board target resources + * + * This function should be called to ensure proper initialization of the target + * board hardware connected to the part. + */ +extern void board_init(void); +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // _BOARD_H_ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/genclk.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/genclk.h new file mode 100644 index 0000000..f9b145a --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/genclk.h @@ -0,0 +1,136 @@ +/** + * \file + * + * \brief Generic clock management + * + * Copyright (C) 2010 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#ifndef CLK_GENCLK_H_INCLUDED +#define CLK_GENCLK_H_INCLUDED + +#include + +#if (UC3A0 || UC3A1) +# include "uc3a0_a1/genclk.h" +#elif UC3A3 +# include "uc3a3_a4/genclk.h" +#elif UC3B +# include "uc3b0_b1/genclk.h" +#elif UC3C +# include "uc3c/genclk.h" +#elif UC3D +# include "uc3d/genclk.h" +#elif UC3L +# include "uc3l/genclk.h" +#else +# error Unsupported chip type +#endif + +/** + * \ingroup clk_group + * \defgroup genclk_group Generic Clock Management + * + * Generic clocks are configurable clocks which run outside the system + * clock domain. They are often connected to peripherals which have an + * asynchronous component running independently of the bus clock, e.g. + * USB controllers, low-power timers and RTCs, etc. + * + * Note that not all platforms have support for generic clocks; on such + * platforms, this API will not be available. + * + * @{ + */ + +/** + * \def GENCLK_DIV_MAX + * \brief Maximum divider supported by the generic clock implementation + */ +/** + * \enum genclk_source + * \brief Generic clock source ID + * + * Each generic clock may be generated from a different clock source. + * These are the available alternatives provided by the chip. + */ + +//! \name Generic clock configuration +//@{ +/** + * \struct genclk_config + * \brief Hardware representation of a set of generic clock parameters + */ +/** + * \fn void genclk_config_defaults(struct genclk_config *cfg, + * unsigned int id) + * \brief Initialize \a cfg to the default configuration for the clock + * identified by \a id. + */ +/** + * \fn void genclk_config_read(struct genclk_config *cfg, unsigned int id) + * \brief Read the currently active configuration of the clock + * identified by \a id into \a cfg. + */ +/** + * \fn void genclk_config_write(const struct genclk_config *cfg, + * unsigned int id) + * \brief Activate the configuration \a cfg on the clock identified by + * \a id. + */ +/** + * \fn void genclk_config_set_source(struct genclk_config *cfg, + * enum genclk_source src) + * \brief Select a new source clock \a src in configuration \a cfg. + */ +/** + * \fn void genclk_config_set_divider(struct genclk_config *cfg, + * unsigned int divider) + * \brief Set a new \a divider in configuration \a cfg. + */ +//@} + +//! \name Enabling and disabling Generic Clocks +//@{ +/** + * \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id) + * \brief Activate the configuration \a cfg on the clock identified by + * \a id and enable it. + */ +/** + * \fn void genclk_disable(unsigned int id) + * \brief Disable the generic clock identified by \a id. + */ +//@} + +//! @} + +#endif /* CLK_GENCLK_H_INCLUDED */ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/osc.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/osc.h new file mode 100644 index 0000000..4e96100 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/osc.h @@ -0,0 +1,145 @@ +/** + * \file + * + * \brief Oscillator management + * + * Copyright (C) 2010 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#ifndef OSC_H_INCLUDED +#define OSC_H_INCLUDED + +#include +#include "conf_clock.h" + +#if (UC3A0 || UC3A1) +# include "uc3a0_a1/osc.h" +#elif UC3A3 +# include "uc3a3_a4/osc.h" +#elif UC3B +# include "uc3b0_b1/osc.h" +#elif UC3C +# include "uc3c/osc.h" +#elif UC3D +# include "uc3d/osc.h" +#elif UC3L +# include "uc3l/osc.h" +#elif XMEGA +# include "xmega/osc.h" +#else +# error Unsupported chip type +#endif + +/** + * \ingroup clk_group + * \defgroup osc_group Oscillator Management + * + * This group contains functions and definitions related to configuring + * and enabling/disabling on-chip oscillators. Internal RC-oscillators, + * external crystal oscillators and external clock generators are + * supported by this module. What all of these have in common is that + * they swing at a fixed, nominal frequency which is normally not + * adjustable. + * + * \par Example: Enabling an oscillator + * + * The following example demonstrates how to enable the external + * oscillator on XMEGA A and wait for it to be ready to use. The + * oscillator identifiers are platform-specific, so while the same + * procedure is used on all platforms, the parameter to osc_enable() + * will be different from device to device. + * \code + osc_enable(OSC_ID_XOSC); + osc_wait_ready(OSC_ID_XOSC); \endcode + * + * \section osc_group_board Board-specific Definitions + * If external oscillators are used, the board code must provide the + * following definitions for each of those: + * - \b BOARD__HZ: The nominal frequency of the oscillator. + * - \b BOARD__STARTUP_US: The startup time of the + * oscillator in microseconds. + * - \b BOARD__TYPE: The type of oscillator connected, i.e. + * whether it's a crystal or external clock, and sometimes what kind + * of crystal it is. The meaning of this value is platform-specific. + * + * @{ + */ + +//! \name Oscillator Management +//@{ +/** + * \fn void osc_enable(uint8_t id) + * \brief Enable oscillator \a id + * + * The startup time and mode value is automatically determined based on + * definitions in the board code. + */ +/** + * \fn void osc_disable(uint8_t id) + * \brief Disable oscillator \a id + */ +/** + * \fn osc_is_ready(uint8_t id) + * \brief Determine whether oscillator \a id is ready. + * \retval true Oscillator \a id is running and ready to use as a clock + * source. + * \retval false Oscillator \a id is not running. + */ +/** + * \fn uint32_t osc_get_rate(uint8_t id) + * \brief Return the frequency of oscillator \a id in Hz + */ + +#ifndef __ASSEMBLY__ + +/** + * \brief Wait until the oscillator identified by \a id is ready + * + * This function will busy-wait for the oscillator identified by \a id + * to become stable and ready to use as a clock source. + * + * \param id A number identifying the oscillator to wait for. + */ +static inline void osc_wait_ready(uint8_t id) +{ + while (!osc_is_ready(id)) { + /* Do nothing */ + } +} + +#endif /* __ASSEMBLY__ */ + +//@} + +//! @} + +#endif /* OSC_H_INCLUDED */ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/pll.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/pll.h new file mode 100644 index 0000000..b507264 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/pll.h @@ -0,0 +1,279 @@ +/** + * \file + * + * \brief PLL management + * + * Copyright (C) 2010 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#ifndef CLK_PLL_H_INCLUDED +#define CLK_PLL_H_INCLUDED + +#include +#include "conf_clock.h" + +#if (UC3A0 || UC3A1) +# include "uc3a0_a1/pll.h" +#elif UC3A3 +# include "uc3a3_a4/pll.h" +#elif UC3B +# include "uc3b0_b1/pll.h" +#elif UC3C +# include "uc3c/pll.h" +#elif UC3D +# include "uc3d/pll.h" +#elif (UC3L0128 || UC3L0256) +# include "uc3l/pll.h" +#elif XMEGA +# include "xmega/pll.h" +#else +# error Unsupported chip type +#endif + +/** + * \ingroup clk_group + * \defgroup pll_group PLL Management + * + * This group contains functions and definitions related to configuring + * and enabling/disabling on-chip PLLs. A PLL will take an input signal + * (the \em source), optionally divide the frequency by a configurable + * \em divider, and then multiply the frequency by a configurable \em + * multiplier. + * + * Some devices don't support input dividers; specifying any other + * divisor than 1 on these devices will result in an assertion failure. + * Other devices may have various restrictions to the frequency range of + * the input and output signals. + * + * \par Example: Setting up PLL0 with default parameters + * + * The following example shows how to configure and enable PLL0 using + * the default parameters specified using the configuration symbols + * listed above, and with Wide Bandwidth Mode disabled (a UC3A3-specific + * PLL option.) + * \code + struct pll_config pllcfg; + + pll_config_defaults(&pllcfg, 0); + pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE); + pll_enable(&pllcfg, 0); + pll_wait_for_lock(0); \endcode + * + * When the last function call returns, PLL0 is ready to be used as the + * main system clock source. + * + * \section pll_group_config Configuration Symbols + * + * Each PLL has a set of default parameters determined by the following + * configuration symbols in the application's configuration file: + * - \b CONFIG_PLLn_SOURCE: The default clock source connected to the + * input of PLL \a n. Must be one of the values defined by the + * #pll_source enum. + * - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL + * \a n. + * - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n. + * + * These configuration symbols determine the result of calling + * pll_config_defaults() and pll_get_default_rate(). + * + * @{ + */ + +//! \name Chip-specific PLL characteristics +//@{ +/** + * \def PLL_MAX_STARTUP_CYCLES + * \brief Maximum PLL startup time in number of slow clock cycles + */ +/** + * \def NR_PLLS + * \brief Number of on-chip PLLs + */ + +/** + * \def PLL_MIN_HZ + * \brief Minimum frequency that the PLL can generate + */ +/** + * \def PLL_MAX_HZ + * \brief Maximum frequency that the PLL can generate + */ +/** + * \def PLL_NR_OPTIONS + * \brief Number of PLL option bits + */ +//@} + +/** + * \enum pll_source + * \brief PLL clock source + */ + +//! \name PLL configuration +//@{ + +/** + * \struct pll_config + * \brief Hardware-specific representation of PLL configuration. + * + * This structure contains one or more device-specific values + * representing the current PLL configuration. The contents of this + * structure is typically different from platform to platform, and the + * user should not access any fields except through the PLL + * configuration API. + */ + +/** + * \fn void pll_config_init(struct pll_config *cfg, + * enum pll_source src, unsigned int div, unsigned int mul) + * \brief Initialize PLL configuration from standard parameters. + * + * \note This function may be defined inline because it is assumed to be + * called very few times, and usually with constant parameters. Inlining + * it will in such cases reduce the code size significantly. + * + * \param cfg The PLL configuration to be initialized. + * \param src The oscillator to be used as input to the PLL. + * \param div PLL input divider. + * \param mul PLL loop divider (i.e. multiplier). + * + * \return A configuration which will make the PLL run at + * (\a mul / \a div) times the frequency of \a src + */ +/** + * \def pll_config_defaults(cfg, pll_id) + * \brief Initialize PLL configuration using default parameters. + * + * After this function returns, \a cfg will contain a configuration + * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV) + * times the frequency of CONFIG_PLLx_SOURCE. + * + * \param cfg The PLL configuration to be initialized. + * \param pll_id Use defaults for this PLL. + */ +/** + * \def pll_get_default_rate(pll_id) + * \brief Get the default rate in Hz of \a pll_id + */ +/** + * \fn void pll_config_set_option(struct pll_config *cfg, + * unsigned int option) + * \brief Set the PLL option bit \a option in the configuration \a cfg. + * + * \param cfg The PLL configuration to be changed. + * \param option The PLL option bit to be set. + */ +/** + * \fn void pll_config_clear_option(struct pll_config *cfg, + * unsigned int option) + * \brief Clear the PLL option bit \a option in the configuration \a cfg. + * + * \param cfg The PLL configuration to be changed. + * \param option The PLL option bit to be cleared. + */ +/** + * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id) + * \brief Read the currently active configuration of \a pll_id. + * + * \param cfg The configuration object into which to store the currently + * active configuration. + * \param pll_id The ID of the PLL to be accessed. + */ +/** + * \fn void pll_config_write(const struct pll_config *cfg, + * unsigned int pll_id) + * \brief Activate the configuration \a cfg on \a pll_id + * + * \param cfg The configuration object representing the PLL + * configuration to be activated. + * \param pll_id The ID of the PLL to be updated. + */ + +//@} + +//! \name Interaction with the PLL hardware +//@{ +/** + * \fn void pll_enable(const struct pll_config *cfg, + * unsigned int pll_id) + * \brief Activate the configuration \a cfg and enable PLL \a pll_id. + * + * \param cfg The PLL configuration to be activated. + * \param pll_id The ID of the PLL to be enabled. + */ +/** + * \fn void pll_disable(unsigned int pll_id) + * \brief Disable the PLL identified by \a pll_id. + * + * After this function is called, the PLL identified by \a pll_id will + * be disabled. The PLL configuration stored in hardware may be affected + * by this, so if the caller needs to restore the same configuration + * later, it should either do a pll_config_read() before disabling the + * PLL, or remember the last configuration written to the PLL. + * + * \param pll_id The ID of the PLL to be disabled. + */ +/** + * \fn bool pll_is_locked(unsigned int pll_id) + * \brief Determine whether the PLL is locked or not. + * + * \param pll_id The ID of the PLL to check. + * + * \retval true The PLL is locked and ready to use as a clock source + * \retval false The PLL is not yet locked, or has not been enabled. + */ + +/** + * \brief Wait for PLL \a pll_id to become locked + * + * \todo Use a timeout to avoid waiting forever and hanging the system + * + * \param pll_id The ID of the PLL to wait for. + * + * \retval STATUS_OK The PLL is now locked. + * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked. + */ +static inline int pll_wait_for_lock(unsigned int pll_id) +{ + Assert(pll_id < NR_PLLS); + + while (!pll_is_locked(pll_id)) { + /* Do nothing */ + } + + return 0; +} + +//@} +//! @} + +#endif /* CLK_PLL_H_INCLUDED */ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/sysclk.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/sysclk.h new file mode 100644 index 0000000..fd617f2 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/sysclk.h @@ -0,0 +1,150 @@ +/** + * \file + * + * \brief System clock management + * + * Copyright (C) 2010 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#ifndef SYSCLK_H_INCLUDED +#define SYSCLK_H_INCLUDED + +#include +#include "conf_clock.h" + +#if (UC3A0 || UC3A1) +# include "uc3a0_a1/sysclk.h" +#elif UC3A3 +# include "uc3a3_a4/sysclk.h" +#elif UC3B +# include "uc3b0_b1/sysclk.h" +#elif UC3C +# include "uc3c/sysclk.h" +#elif UC3D +# include "uc3d/sysclk.h" +#elif UC3L +# include "uc3l/sysclk.h" +#elif XMEGA +# include "xmega/sysclk.h" +#else +# error Unsupported chip type +#endif + +/** + * \defgroup clk_group Clock Management + */ + +/** + * \ingroup clk_group + * \defgroup sysclk_group System Clock Management + * + * The sysclk API covers the system clock and all + * clocks derived from it. The system clock is a chip-internal clock on + * which all synchronous clocks, i.e. CPU and bus/peripheral + * clocks, are based. The system clock is typically generated from one + * of a variety of sources, which may include crystal and RC oscillators + * as well as PLLs. The clocks derived from the system clock are + * sometimes also known as synchronous clocks, since they + * always run synchronously with respect to each other, as opposed to + * generic clocks which may run from different oscillators or + * PLLs. + * + * Most applications should simply call sysclk_init() to initialize + * everything related to the system clock and its source (oscillator, + * PLL or DFLL), and leave it at that. More advanced applications, and + * platform-specific drivers, may require additional services from the + * clock system, some of which may be platform-specific. + * + * \section sysclk_group_platform Platform Dependencies + * + * The sysclk API is partially chip- or platform-specific. While all + * platforms provide mostly the same functionality, there are some + * variations around how different bus types and clock tree structures + * are handled. + * + * The following functions are available on all platforms with the same + * parameters and functionality. These functions may be called freely by + * portable applications, drivers and services: + * - sysclk_init() + * - sysclk_set_source() + * - sysclk_get_main_hz() + * - sysclk_get_cpu_hz() + * - sysclk_get_peripheral_bus_hz() + * + * The following functions are available on all platforms, but there may + * be variations in the function signature (i.e. parameters) and + * behaviour. These functions are typically called by platform-specific + * parts of drivers, and applications that aren't intended to be + * portable: + * - sysclk_enable_peripheral_clock() + * - sysclk_disable_peripheral_clock() + * - sysclk_enable_module() + * - sysclk_disable_module() + * - sysclk_module_is_enabled() + * - sysclk_set_prescalers() + * + * All other functions should be considered platform-specific. + * Enabling/disabling clocks to specific peripherals as well as + * determining the speed of these clocks should be done by calling + * functions provided by the driver for that peripheral. + * + * @{ + */ + +//! \name System Clock Initialization +//@{ +/** + * \fn void sysclk_init(void) + * \brief Initialize the synchronous clock system. + * + * This function will initialize the system clock and its source. This + * includes: + * - Mask all synchronous clocks except for any clocks which are + * essential for normal operation (for example internal memory + * clocks). + * - Set up the system clock prescalers as specified by the + * application's configuration file. + * - Enable the clock source specified by the application's + * configuration file (oscillator or PLL) and wait for it to become + * stable. + * - Set the main system clock source to the clock specified by the + * application's configuration file. + * + * Since all non-essential peripheral clocks are initially disabled, it + * is the responsibility of the peripheral driver to re-enable any + * clocks that are needed for normal operation. + */ +//@} + +//! @} + +#endif /* SYSCLK_H_INCLUDED */ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/genclk.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/genclk.h new file mode 100644 index 0000000..9a3b2b8 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/genclk.h @@ -0,0 +1,132 @@ +/** + * \file + * + * \brief Chip-specific generic clock management + * + * Copyright (C) 2010 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#ifndef CHIP_GENCLK_H_INCLUDED +#define CHIP_GENCLK_H_INCLUDED + +/** + * \weakgroup genclk_group + * @{ + */ + +//! \name Chip-specific generic clock definitions +//@{ + +#define GENCLK_DIV_MAX 256 + +#ifndef __ASSEMBLY__ + +#include +#include + +enum genclk_source { + GENCLK_SRC_RCSYS = 0, //!< System RC oscillator + GENCLK_SRC_OSC32K = 1, //!< 32 kHz oscillator + GENCLK_SRC_RC8M = 2, //!< 8 MHz RC oscillator + GENCLK_SRC_OSC0 = 3, //!< Oscillator 0 + GENCLK_SRC_OSC1 = 4, //!< Oscillator 1 + GENCLK_SRC_PLL0 = 5, //!< PLL 0 + GENCLK_SRC_PLL1 = 6, //!< PLL 1 + GENCLK_SRC_CLK_CPU = 7, //!< CPU clock + GENCLK_SRC_CLK_HSB = 8, //!< High Speed Bus clock + GENCLK_SRC_CLK_PBA = 9, //!< Peripheral Bus A clock + GENCLK_SRC_CLK_PBB = 10, //!< Peripheral Bus B clock + GENCLK_SRC_CLK_PBC = 11, //!< Peripheral Bus C clock +}; + +//@} + +struct genclk_config { + uint32_t ctrl; +}; + +static inline void genclk_config_defaults(struct genclk_config *cfg, + unsigned int id) +{ + cfg->ctrl = 0; +} + +static inline void genclk_config_read(struct genclk_config *cfg, + unsigned int id) +{ + cfg->ctrl = AVR32_SCIF.gcctrl[id]; +} + +static inline void genclk_config_write(const struct genclk_config *cfg, + unsigned int id) +{ + AVR32_SCIF.gcctrl[id] = cfg->ctrl; +} + +static inline void genclk_config_set_source(struct genclk_config *cfg, + enum genclk_source src) +{ + cfg->ctrl = (cfg->ctrl & ~AVR32_SCIF_GCCTRL_OSCSEL_MASK) + | (src << AVR32_SCIF_GCCTRL_OSCSEL); +} + +static inline void genclk_config_set_divider(struct genclk_config *cfg, + unsigned int divider) +{ + Assert(divider > 0 && divider <= GENCLK_DIV_MAX); + + /* Clear all the bits we're about to modify */ + cfg->ctrl &= ~(AVR32_SCIF_GCCTRL_DIVEN_MASK + | AVR32_SCIF_GCCTRL_DIV_MASK); + + if (divider > 1) { + cfg->ctrl |= 1U << AVR32_SCIF_GCCTRL_DIVEN; + cfg->ctrl |= (((divider + 1) / 2) - 1) << AVR32_SCIF_GCCTRL_DIV; + } +} + +static inline void genclk_enable(const struct genclk_config *cfg, + unsigned int id) +{ + AVR32_SCIF.gcctrl[id] = cfg->ctrl | (1U << AVR32_SCIF_GCCTRL_CEN); +} + +static inline void genclk_disable(unsigned int id) +{ + AVR32_SCIF.gcctrl[id] = 0; +} + +#endif /* __ASSEMBLY__ */ + +//! @} + +#endif /* CHIP_GENCLK_H_INCLUDED */ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/osc.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/osc.c new file mode 100644 index 0000000..032146f --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/osc.c @@ -0,0 +1,169 @@ +/** + * \file + * + * \brief Chip-specific oscillator management functions + * + * Copyright (C) 2010 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#include + +#ifdef BOARD_OSC0_HZ +void osc_priv_enable_osc0(void) +{ + irqflags_t flags; + + flags = cpu_irq_save(); + AVR32_SCIF.unlock = 0xaa000000 | AVR32_SCIF_OSCCTRL; + AVR32_SCIF.oscctrl[0] = + (OSC0_STARTUP_VALUE << AVR32_SCIF_OSCCTRL_STARTUP) + | (OSC0_GAIN_VALUE << AVR32_SCIF_OSCCTRL_GAIN) + | (OSC0_MODE_VALUE << AVR32_SCIF_OSCCTRL_MODE) + | (1U << AVR32_SCIF_OSCCTRL_OSCEN); + cpu_irq_restore(flags); +} + +void osc_priv_disable_osc0(void) +{ + irqflags_t flags; + + flags = cpu_irq_save(); + AVR32_SCIF.unlock = 0xaa000000 | AVR32_SCIF_OSCCTRL; + AVR32_SCIF.oscctrl[0] = 0; + cpu_irq_restore(flags); +} +#endif /* BOARD_OSC0_HZ */ + +#ifdef BOARD_OSC1_HZ +void osc_priv_enable_osc1(void) +{ + irqflags_t flags; + + flags = cpu_irq_save(); + AVR32_SCIF.unlock = 0xaa000000 | AVR32_SCIF_OSCCTRL; + AVR32_SCIF.oscctrl[1] = + (OSC0_STARTUP_VALUE << AVR32_SCIF_OSCCTRL_STARTUP) + | (OSC0_GAIN_VALUE << AVR32_SCIF_OSCCTRL_GAIN) + | (OSC0_MODE_VALUE << AVR32_SCIF_OSCCTRL_MODE) + | (1U << AVR32_SCIF_OSCCTRL_OSCEN); + cpu_irq_restore(flags); +} + +void osc_priv_disable_osc1(void) +{ + irqflags_t flags; + + flags = cpu_irq_save(); + AVR32_SCIF.unlock = 0xaa000000 | AVR32_SCIF_OSCCTRL; + AVR32_SCIF.oscctrl[1] = 0; + cpu_irq_restore(flags); +} +#endif /* BOARD_OSC0_HZ */ + +#ifdef BOARD_OSC32_HZ +void osc_priv_enable_osc32(void) +{ + irqflags_t flags; + + flags = cpu_irq_save(); + AVR32_SCIF.unlock = 0xaa000000 | AVR32_SCIF_OSCCTRL32; + AVR32_SCIF.oscctrl32 = + (OSC32_STARTUP_VALUE << AVR32_SCIF_OSCCTRL32_STARTUP) + | (OSC32_MODE_VALUE << AVR32_SCIF_OSCCTRL32_MODE) + | (1U << AVR32_SCIF_OSCCTRL32_OSC32EN); + cpu_irq_restore(flags); +} + +void osc_priv_disable_osc32(void) +{ + irqflags_t flags; + + flags = cpu_irq_save(); + AVR32_SCIF.unlock = 0xaa000000 | AVR32_SCIF_OSCCTRL32; + AVR32_SCIF.oscctrl32 = 0; + cpu_irq_restore(flags); +} +#endif /* BOARD_OSC0_HZ */ + +void osc_priv_enable_rc8m(void) +{ + irqflags_t flags; + uint32_t rccr8; + uint32_t* calibration_bits = (uint32_t*)0x80800200; + /* Wait for the CALIB field to be updated from fuses after reset */ + while (!(AVR32_SCIF.rccr8 & AVR32_SCIF_RCCR8_FCD_MASK)) { + /* Do nothing */ + } + + /* Enable the oscillator without touching the CALIB and FCD fields */ + flags = cpu_irq_save(); + rccr8 = AVR32_SCIF.rccr8; + rccr8 &= AVR32_SCIF_RCCR8_FCD_MASK | ((*calibration_bits)&AVR32_SCIF_RCCR8_CALIB_MASK); + rccr8 |= 1U << AVR32_SCIF_RCOSC8_EN; + AVR32_SCIF.unlock = 0xaa000000 | AVR32_SCIF_RCCR8; + AVR32_SCIF.rccr8 = rccr8; + cpu_irq_restore(flags); +} + +void osc_priv_disable_rc8m(void) +{ + irqflags_t flags; + uint32_t rccr8; + + /* Disable the oscillator without touching the CALIB and FCD fields */ + flags = cpu_irq_save(); + rccr8 = AVR32_SCIF.rccr8; + rccr8 &= AVR32_SCIF_RCCR8_FCD_MASK | AVR32_SCIF_RCCR8_CALIB_MASK; + AVR32_SCIF.unlock = 0xaa000000 | AVR32_SCIF_RCCR8; + AVR32_SCIF.rccr8 = rccr8; + cpu_irq_restore(flags); +} + +void osc_priv_enable_rc120m(void) +{ + irqflags_t flags; + + flags = cpu_irq_save(); + AVR32_SCIF.unlock = 0xaa000000 | AVR32_SCIF_RC120MCR; + AVR32_SCIF.rc120mcr = 1U << AVR32_SCIF_RC120MCR_EN; + cpu_irq_restore(flags); +} + +void osc_priv_disable_rc120m(void) +{ + irqflags_t flags; + + flags = cpu_irq_save(); + AVR32_SCIF.unlock = 0xaa000000 | AVR32_SCIF_RC120MCR; + AVR32_SCIF.rc120mcr = 0; + cpu_irq_restore(flags); +} diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/osc.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/osc.h new file mode 100644 index 0000000..0f235e2 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/osc.h @@ -0,0 +1,600 @@ +/** + * \file + * + * \brief Chip-specific oscillator management functions + * + * Copyright (C) 2010 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#ifndef CHIP_OSC_H_INCLUDED +#define CHIP_OSC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// Bugzilla #11803 +#ifdef AVR32_SCIF_OSCCTRL32_MODE_CRYSTAL_AGC +#undef AVR32_SCIF_OSCCTRL32_MODE_CRYSTAL_AGC +#endif +#define AVR32_SCIF_OSCCTRL32_MODE_CRYSTAL_AGC AVR32_SCIF_OSCCTRL32_MODE_CRYSTAL_ACG +#ifdef AVR32_SCIF_OSCCTRL32_MODE_CRYSTAL_NO_AGC +#undef AVR32_SCIF_OSCCTRL32_MODE_CRYSTAL_NO_AGC +#endif +#define AVR32_SCIF_OSCCTRL32_MODE_CRYSTAL_NO_AGC AVR32_SCIF_OSCCTRL32_MODE_CRYSTAL_NO_ACG + +/** + * \weakgroup osc_group + * @{ + */ + +//! \name Oscillator identifiers +//@{ +#define OSC_ID_OSC0 0 //!< External Oscillator 0 +#define OSC_ID_OSC1 1 //!< External Oscillator 1 +#define OSC_ID_RC8M 2 //!< Internal 8 MHz RC oscillator +#define OSC_ID_OSC32 3 //!< External 32 kHz oscillator +#define OSC_ID_RC120M 4 //!< Internal 120 MHz RC oscillator +#define OSC_ID_RCSYS 5 //!< Internal System RC oscillator +//@} + +//! \name OSC0/OSC1 mode values +//@{ +//! External clock connected to XIN +#define OSC_MODE_EXTERNAL AVR32_SCIF_OSCCTRL_MODE_EXT_CLOCK +//! Crystal connected to XIN/XOUT +#define OSC_MODE_XTAL AVR32_SCIF_OSCCTRL_MODE_CRYSTAL +//@} + +//! \name OSC32 mode values +//@{ +//! External clock connected to XIN32 +#define OSC32_MODE_EXTERNAL AVR32_SCIF_OSCCTRL32_MODE_EXT_CLOCK +//! Crystal connected to XIN32/XOUT32 +#define OSC32_MODE_XTAL AVR32_SCIF_OSCCTRL32_MODE_CRYSTAL_AGC +//! Crystal connected to XIN32/XOUT32 in high current mode +#define OSC32_MODE_XTAL_HC AVR32_SCIF_OSCCTRL32_MODE_CRYSTAL_NO_AGC +//@} + +//! \name OSC0/OSC1 startup values +//@{ +//! 0 cycles +#define OSC_STARTUP_0 AVR32_SCIF_OSCCTRL0_STARTUP_0_RCOSC +//! 4 cycles (35 us) +#define OSC_STARTUP_4 AVR32_SCIF_OSCCTRL0_STARTUP_4_RCOSC +//! 8 cycles (70 us) +#define OSC_STARTUP_8 AVR32_SCIF_OSCCTRL0_STARTUP_8_RCOSC +//! 16 cycles (140 us) +#define OSC_STARTUP_16 AVR32_SCIF_OSCCTRL0_STARTUP_16_RCOSC +//! 32 cycles (280 us) +#define OSC_STARTUP_32 AVR32_SCIF_OSCCTRL0_STARTUP_32_RCOSC +//! 64 cycles (560 us) +#define OSC_STARTUP_64 AVR32_SCIF_OSCCTRL0_STARTUP_64_RCOSC +//! 128 cycles (1.1 ms) +#define OSC_STARTUP_128 AVR32_SCIF_OSCCTRL0_STARTUP_128_RCOSC +//! 256 cycles (2.2 ms) +#define OSC_STARTUP_256 AVR32_SCIF_OSCCTRL0_STARTUP_256_RCOSC +//! 512 cycles (4.5 ms) +#define OSC_STARTUP_512 AVR32_SCIF_OSCCTRL0_STARTUP_512_RCOSC +//! 1024 cycles (9.0 ms) +#define OSC_STARTUP_1024 AVR32_SCIF_OSCCTRL0_STARTUP_1024_RCOSC +//! 2048 cycles (18 ms) +#define OSC_STARTUP_2048 AVR32_SCIF_OSCCTRL0_STARTUP_2048_RCOSC +//! 4096 cycles (36 ms) +#define OSC_STARTUP_4096 AVR32_SCIF_OSCCTRL0_STARTUP_4096_RCOSC +//! 8192 cycles (71 ms) +#define OSC_STARTUP_8192 AVR32_SCIF_OSCCTRL0_STARTUP_8192_RCOSC +//! 16384 cycles (142 ms) +#define OSC_STARTUP_16384 AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC +//@} + +//! \name OSC32 startup values +//@{ +//! 0 cycles +#define OSC32_STARTUP_0 AVR32_SCIF_OSCCTRL32_STARTUP_0_RCOSC +//! 128 cycles (1.1 ms) +#define OSC32_STARTUP_128 AVR32_SCIF_OSCCTRL32_STARTUP_128_RCOSC +//! 8192 cycles (72.3 ms) +#define OSC32_STARTUP_8192 AVR32_SCIF_OSCCTRL32_STARTUP_8192_RCOSC +//! 16384 cycles (143 ms) +#define OSC32_STARTUP_16384 AVR32_SCIF_OSCCTRL32_STARTUP_16384_RCOSC +//! 65536 cycles (570 ms) +#define OSC32_STARTUP_65536 AVR32_SCIF_OSCCTRL32_STARTUP_65536_RCOSC +//! 131072 cycles (1.1 s) +#define OSC32_STARTUP_131072 AVR32_SCIF_OSCCTRL32_STARTUP_131072_RCOSC +//! 262144 cycles (2.3 s) +#define OSC32_STARTUP_262144 AVR32_SCIF_OSCCTRL32_STARTUP_262144_RCOSC +//! 524288 cycles (4.6 s) +#define OSC32_STARTUP_524288 AVR32_SCIF_OSCCTRL32_STARTUP_524288_RCOSC +//@} + +/** + * \def OSC0_STARTUP_TIMEOUT + * \brief Number of slow clock cycles to wait for OSC0 to start + * + * This is the number of slow clock cycles corresponding to + * OSC0_STARTUP_VALUE with an additional 25% safety margin. If the + * oscillator isn't running when this timeout has expired, it is assumed + * to have failed to start. + */ +/** + * \def OSC0_MODE_VALUE + * \brief Board-dependent value written to the MODE bitfield of + * PM_OSCCTRL(0) + */ +/** + * \def OSC0_STARTUP_VALUE + * \brief Board-dependent value written to the STARTUP bitfield of + * PM_OSCCTRL(0) + */ +/** + * \def OSC1_STARTUP_TIMEOUT + * \brief Number of slow clock cycles to wait for OSC1 to start + * + * This is the number of slow clock cycles corresponding to + * OSC1_STARTUP_VALUE with an additional 25% safety margin. If the + * oscillator isn't running when this timeout has expired, it is assumed + * to have failed to start. + */ +/** + * \def OSC1_MODE_VALUE + * \brief Board-dependent value written to the MODE bitfield of + * PM_OSCCTRL(1) + */ +/** + * \def OSC1_STARTUP_VALUE + * \brief Board-dependent value written to the STARTUP bitfield of + * PM_OSCCTRL(1) + */ + +#if defined(BOARD_OSC0_STARTUP_US) +# if BOARD_OSC0_STARTUP_US == 0 +# define OSC0_STARTUP_VALUE OSC_STARTUP_0 +# define OSC0_STARTUP_TIMEOUT 1 +# elif BOARD_OSC0_STARTUP_US <= 35 +# define OSC0_STARTUP_VALUE OSC_STARTUP_4 +# define OSC0_STARTUP_TIMEOUT 5 +# elif BOARD_OSC0_STARTUP_US <= 70 +# define OSC0_STARTUP_VALUE OSC_STARTUP_8 +# define OSC0_STARTUP_TIMEOUT 10 +# elif BOARD_OSC0_STARTUP_US <= 140 +# define OSC0_STARTUP_VALUE OSC_STARTUP_16 +# define OSC0_STARTUP_TIMEOUT 20 +# elif BOARD_OSC0_STARTUP_US <= 280 +# define OSC0_STARTUP_VALUE OSC_STARTUP_32 +# define OSC0_STARTUP_TIMEOUT 40 +# elif BOARD_OSC0_STARTUP_US <= 560 +# define OSC0_STARTUP_VALUE OSC_STARTUP_64 +# define OSC0_STARTUP_TIMEOUT 80 +# elif BOARD_OSC0_STARTUP_US <= 1100 +# define OSC0_STARTUP_VALUE OSC_STARTUP_128 +# define OSC0_STARTUP_TIMEOUT 160 +# elif BOARD_OSC0_STARTUP_US <= 2200 +# define OSC0_STARTUP_VALUE OSC_STARTUP_256 +# define OSC0_STARTUP_TIMEOUT 320 +# elif BOARD_OSC0_STARTUP_US <= 4500 +# define OSC0_STARTUP_VALUE OSC_STARTUP_512 +# define OSC0_STARTUP_TIMEOUT 640 +# elif BOARD_OSC0_STARTUP_US <= 9000 +# define OSC0_STARTUP_VALUE OSC_STARTUP_1024 +# define OSC0_STARTUP_TIMEOUT 1280 +# elif BOARD_OSC0_STARTUP_US <= 18000 +# define OSC0_STARTUP_VALUE OSC_STARTUP_2048 +# define OSC0_STARTUP_TIMEOUT 2560 +# elif BOARD_OSC0_STARTUP_US <= 36000 +# define OSC0_STARTUP_VALUE OSC_STARTUP_4096 +# define OSC0_STARTUP_TIMEOUT 5120 +# elif BOARD_OSC0_STARTUP_US <= 71000 +# define OSC0_STARTUP_VALUE OSC_STARTUP_8192 +# define OSC0_STARTUP_TIMEOUT 10240 +# elif BOARD_OSC0_STARTUP_US <= 142000 +# define OSC0_STARTUP_VALUE OSC_STARTUP_16384 +# define OSC0_STARTUP_TIMEOUT 20480 +# else +# error BOARD_OSC0_STARTUP_US is too high +# endif +# if BOARD_OSC0_IS_XTAL == true +# define OSC0_MODE_VALUE OSC_MODE_XTAL +# if BOARD_OSC0_HZ < 900000 +# define OSC0_GAIN_VALUE AVR32_SCIF_OSCCTRL0_GAIN_G0 +# elif BOARD_OSC0_HZ < 3000000 +# define OSC0_GAIN_VALUE AVR32_SCIF_OSCCTRL0_GAIN_G1 +# elif BOARD_OSC0_HZ < 8000000 +# define OSC0_GAIN_VALUE AVR32_SCIF_OSCCTRL0_GAIN_G2 +# else +# define OSC0_GAIN_VALUE AVR32_SCIF_OSCCTRL0_GAIN_G3 +# endif +# else +# define OSC0_MODE_VALUE OSC_MODE_EXTERNAL +# endif +#else +# if defined(BOARD_OSC0_HZ) +# error BOARD_OSC0_STARTUP_US must be defined by the board code +# endif +# ifdef __DOXYGEN__ +# define OSC0_STARTUP_VALUE UNDEFINED +# define OSC0_STARTUP_TIMEOUT UNDEFINED +# define OSC0_MODE_VALUE UNDEFINED +# endif +#endif +#if defined(BOARD_OSC1_STARTUP_US) +# if BOARD_OSC1_STARTUP_US == 0 +# define OSC1_STARTUP_VALUE OSC_STARTUP_0 +# define OSC1_STARTUP_TIMEOUT 1 +# elif BOARD_OSC1_STARTUP_US <= 35 +# define OSC1_STARTUP_VALUE OSC_STARTUP_4 +# define OSC1_STARTUP_TIMEOUT 5 +# elif BOARD_OSC1_STARTUP_US <= 70 +# define OSC1_STARTUP_VALUE OSC_STARTUP_8 +# define OSC1_STARTUP_TIMEOUT 10 +# elif BOARD_OSC1_STARTUP_US <= 140 +# define OSC1_STARTUP_VALUE OSC_STARTUP_16 +# define OSC1_STARTUP_TIMEOUT 20 +# elif BOARD_OSC1_STARTUP_US <= 280 +# define OSC1_STARTUP_VALUE OSC_STARTUP_32 +# define OSC1_STARTUP_TIMEOUT 40 +# elif BOARD_OSC1_STARTUP_US <= 560 +# define OSC1_STARTUP_VALUE OSC_STARTUP_64 +# define OSC1_STARTUP_TIMEOUT 80 +# elif BOARD_OSC1_STARTUP_US <= 1100 +# define OSC1_STARTUP_VALUE OSC_STARTUP_128 +# define OSC1_STARTUP_TIMEOUT 160 +# elif BOARD_OSC1_STARTUP_US <= 2200 +# define OSC1_STARTUP_VALUE OSC_STARTUP_256 +# define OSC1_STARTUP_TIMEOUT 320 +# elif BOARD_OSC1_STARTUP_US <= 4500 +# define OSC1_STARTUP_VALUE OSC_STARTUP_512 +# define OSC1_STARTUP_TIMEOUT 640 +# elif BOARD_OSC1_STARTUP_US <= 9000 +# define OSC1_STARTUP_VALUE OSC_STARTUP_1024 +# define OSC1_STARTUP_TIMEOUT 1280 +# elif BOARD_OSC1_STARTUP_US <= 18000 +# define OSC1_STARTUP_VALUE OSC_STARTUP_2048 +# define OSC1_STARTUP_TIMEOUT 2560 +# elif BOARD_OSC1_STARTUP_US <= 36000 +# define OSC1_STARTUP_VALUE OSC_STARTUP_4096 +# define OSC1_STARTUP_TIMEOUT 5120 +# elif BOARD_OSC1_STARTUP_US <= 71000 +# define OSC1_STARTUP_VALUE OSC_STARTUP_8192 +# define OSC1_STARTUP_TIMEOUT 10240 +# elif BOARD_OSC1_STARTUP_US <= 142000 +# define OSC1_STARTUP_VALUE OSC_STARTUP_16384 +# define OSC1_STARTUP_TIMEOUT 20480 +# else +# error BOARD_OSC1_STARTUP_US is too high +# endif +# if BOARD_OSC1_IS_XTAL == true +# define OSC1_MODE_VALUE OSC_MODE_XTAL +# if BOARD_OSC1_HZ < 900000 +# define OSC1_GAIN_VALUE AVR32_SCIF_OSCCTRL1_GAIN_G0 +# elif BOARD_OSC1_HZ < 3000000 +# define OSC1_GAIN_VALUE AVR32_SCIF_OSCCTRL1_GAIN_G1 +# elif BOARD_OSC1_HZ < 8000000 +# define OSC1_GAIN_VALUE AVR32_SCIF_OSCCTRL1_GAIN_G2 +# else +# define OSC1_GAIN_VALUE AVR32_SCIF_OSCCTRL1_GAIN_G3 +# endif +# else +# define OSC1_MODE_VALUE OSC_MODE_EXTERNAL +# endif +#else +# if defined(BOARD_OSC1_HZ) +# error BOARD_OSC1_STARTUP_US must be defined by the board code +# endif +# ifdef __DOXYGEN__ +# define OSC1_STARTUP_VALUE UNDEFINED +# define OSC1_STARTUP_TIMEOUT UNDEFINED +# define OSC1_MODE_VALUE UNDEFINED +# endif +#endif + +#if defined(BOARD_OSC32_STARTUP_US) +# if BOARD_OSC32_STARTUP_US == 0 +# define OSC32_STARTUP_VALUE OSC32_STARTUP_0 +# elif BOARD_OSC32_STARTUP_US <= 1100 +# define OSC32_STARTUP_VALUE OSC32_STARTUP_128 +# elif BOARD_OSC32_STARTUP_US <= 72300 +# define OSC32_STARTUP_VALUE OSC32_STARTUP_8192 +# elif BOARD_OSC32_STARTUP_US <= 143000 +# define OSC32_STARTUP_VALUE OSC32_STARTUP_16384 +# elif BOARD_OSC32_STARTUP_US <= 570000 +# define OSC32_STARTUP_VALUE OSC32_STARTUP_65536 +# elif BOARD_OSC32_STARTUP_US <= 1100000 +# define OSC32_STARTUP_VALUE OSC32_STARTUP_131072 +# elif BOARD_OSC32_STARTUP_US <= 2300000 +# define OSC32_STARTUP_VALUE OSC32_STARTUP_262144 +# elif BOARD_OSC32_STARTUP_US <= 4600000 +# define OSC32_STARTUP_VALUE OSC32_STARTUP_524288 +# else +# error BOARD_OSC32_STARTUP_US is too high +# endif +# if BOARD_OSC32_IS_XTAL == true +# define OSC32_MODE_VALUE OSC32_MODE_XTAL +# else +# define OSC32_MODE_VALUE OSC32_MODE_EXTERNAL +# endif +#else +# if defined(BOARD_OSC32_HZ) +# error BOARD_OSC32_STARTUP_US must be defined by the board code +# endif +# ifdef __DOXYGEN__ +# define OSC32_STARTUP_VALUE UNDEFINED +# define OSC32_STARTUP_TIMEOUT UNDEFINED +# define OSC32_MODE_VALUE UNDEFINED +# endif +#endif + +/** + * \name Board-specific configuration parameters + * The following definitions must be provided by the board code for all + * working oscillators on the board. + */ +//@{ +/** + * \def BOARD_OSC0_HZ + * \brief Clock frequency of OSC0 in Hz + */ +/** + * \def BOARD_OSC0_STARTUP_US + * \brief Startup time of OSC0 in microseconds + */ +/** + * \def BOARD_OSC0_IS_XTAL + * \brief OSC0 uses a crystal, not an external clock + */ +/** + * \def BOARD_OSC1_HZ + * \brief Clock frequency of OSC1 in Hz + */ +/** + * \def BOARD_OSC1_STARTUP_US + * \brief Startup time of OSC1 in microseconds + */ +/** + * \def BOARD_OSC1_IS_XTAL + * \brief OSC1 uses a crystal, not an external clock + */ +/** + * \def BOARD_OSC32_HZ + * \brief Clock frequency of OSC32 in Hz + */ +/** + * \def BOARD_OSC32_STARTUP_US + * \brief Startup time of OSC32 in microseconds + */ +/** + * \def BOARD_OSC32_IS_XTAL + * \brief OSC32 uses a crystal, not an external clock + */ + +/** + * \name RC oscillator frequency limits + * The frequency of the internal RC oscillators may drift a bit as a + * result of temperature changes. These definitions provide upper and + * lower limits which may be used to calculate upper and lower limits of + * timeouts, derived clock frequencies, etc. + */ +//@{ +//! Nominal frequency of RCSYS in Hz +#define OSC_RCSYS_NOMINAL_HZ 115000 +//! Minimum frequency of RCSYS in Hz +#define OSC_RCSYS_MIN_HZ 100000 +//! Maximum frequency of RCSYS in Hz +#define OSC_RCSYS_MAX_HZ 120000 +//! Nominal frequency of RC8M in Hz +#define OSC_RC8M_NOMINAL_HZ 8000000 +//! Nominal frequency of RC120M in Hz +#define OSC_RC120M_NOMINAL_HZ 120000000 +//@} + +#ifndef __ASSEMBLY__ + +#include +#include +#include + +extern void osc_priv_enable_osc0(void); +extern void osc_priv_disable_osc0(void); +extern bool osc_priv_osc0_is_ready(void); +extern void osc_priv_enable_osc1(void); +extern void osc_priv_disable_osc1(void); +extern bool osc_priv_osc1_is_ready(void); +extern void osc_priv_enable_osc32(void); +extern void osc_priv_disable_osc32(void); +extern bool osc_priv_osc32_is_ready(void); +extern void osc_priv_enable_rc8m(void); +extern void osc_priv_disable_rc8m(void); +extern bool osc_priv_rc8m_is_ready(void); +extern void osc_priv_enable_rc120m(void); +extern void osc_priv_disable_rc120m(void); +extern bool osc_priv_rc120m_is_ready(void); + +static inline void osc_enable(uint8_t id) +{ + switch (id) { +#ifdef BOARD_OSC0_HZ + case OSC_ID_OSC0: + osc_priv_enable_osc0(); + break; +#endif + +#ifdef BOARD_OSC1_HZ + case OSC_ID_OSC1: + osc_priv_enable_osc1(); + break; +#endif + +#ifdef BOARD_OSC32_HZ + case OSC_ID_OSC32: + osc_priv_enable_osc32(); + break; +#endif + + case OSC_ID_RC8M: + osc_priv_enable_rc8m(); + break; + + case OSC_ID_RC120M: + osc_priv_enable_rc120m(); + break; + + case OSC_ID_RCSYS: + /* RCSYS is always running */ + break; + + default: + /* unhandled_case(id); */ + break; + } +} + +static inline void osc_disable(uint8_t id) +{ + switch (id) { +#ifdef BOARD_OSC0_HZ + case OSC_ID_OSC0: + osc_priv_disable_osc0(); + break; +#endif + +#ifdef BOARD_OSC1_HZ + case OSC_ID_OSC1: + osc_priv_disable_osc1(); + break; +#endif + +#ifdef BOARD_OSC32_HZ + case OSC_ID_OSC32: + osc_priv_disable_osc32(); + break; +#endif + + case OSC_ID_RC8M: + osc_priv_disable_rc8m(); + break; + + case OSC_ID_RC120M: + osc_priv_disable_rc120m(); + break; + + case OSC_ID_RCSYS: + /* RCSYS is always running */ + break; + + default: + /* unhandled_case(id); */ + break; + } +} + +static inline bool osc_is_ready(uint8_t id) +{ + switch (id) { +#ifdef BOARD_OSC0_HZ + case OSC_ID_OSC0: + return !!(AVR32_SCIF.pclksr & (1 << AVR32_SCIF_OSC0RDY)); +#endif + +#ifdef BOARD_OSC1_HZ + case OSC_ID_OSC1: + return !!(AVR32_SCIF.pclksr & (1 << AVR32_SCIF_OSC1RDY)); +#endif + +#ifdef BOARD_OSC32_HZ + case OSC_ID_OSC32: + return !!(AVR32_SCIF.pclksr & (1 << AVR32_SCIF_OSC32RDY)); +#endif + + case OSC_ID_RC8M: + return !!(AVR32_SCIF.pclksr & (1U << AVR32_SCIF_RCOSC8MRDY)); + + case OSC_ID_RC120M: + return !!(AVR32_SCIF.rc120mcr & (1 << AVR32_SCIF_RC120MCR_EN)); + + case OSC_ID_RCSYS: + /* RCSYS is always ready */ + return true; + + default: + /* unhandled_case(id); */ + return false; + } +} + +/** + * \todo RC8M may run at either 8 MHz or 1 MHz. Currently, we assume + * it's always running at 8 MHz. + */ +static inline uint32_t osc_get_rate(uint8_t id) +{ + switch (id) { +#ifdef BOARD_OSC0_HZ + case OSC_ID_OSC0: + return BOARD_OSC0_HZ; +#endif + +#ifdef BOARD_OSC1_HZ + case OSC_ID_OSC1: + return BOARD_OSC1_HZ; +#endif + +#ifdef BOARD_OSC32_HZ + case OSC_ID_OSC32: + return BOARD_OSC32_HZ; +#endif + + case OSC_ID_RC8M: + return OSC_RC8M_NOMINAL_HZ; + + case OSC_ID_RC120M: + return OSC_RC120M_NOMINAL_HZ; + + case OSC_ID_RCSYS: + return OSC_RCSYS_NOMINAL_HZ; + + default: + /* unhandled_case(id); */ + return 0; + } +} + +#endif /* !__ASSEMBLY__ */ + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif /* CHIP_OSC_H_INCLUDED */ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/pll.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/pll.c new file mode 100644 index 0000000..64029d4 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/pll.c @@ -0,0 +1,76 @@ +/** + * \file + * + * \brief Chip-specific PLL implementation + * + * Copyright (C) 2010 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#include +#include +#include + +void pll_config_write(const struct pll_config *cfg, unsigned int pll_id) +{ + irqflags_t flags; + + Assert(pll_id < NR_PLLS); + + flags = cpu_irq_save(); + AVR32_SCIF.unlock = 0xaa000000 | (AVR32_SCIF_PLL + (4 * pll_id)); + AVR32_SCIF.pll[pll_id] = cfg->ctrl; + cpu_irq_restore(flags); +} + +void pll_enable(const struct pll_config *cfg, unsigned int pll_id) +{ + irqflags_t flags; + + Assert(pll_id < NR_PLLS); + + flags = cpu_irq_save(); + AVR32_SCIF.unlock = 0xaa000000 | (AVR32_SCIF_PLL + (4 * pll_id)); + AVR32_SCIF.pll[pll_id] = cfg->ctrl | (1U << AVR32_SCIF_PLLEN); + cpu_irq_restore(flags); +} + +void pll_disable(unsigned int pll_id) +{ + irqflags_t flags; + + Assert(pll_id < NR_PLLS); + + flags = cpu_irq_save(); + AVR32_SCIF.unlock = 0xaa000000 | (AVR32_SCIF_PLL + (4 * pll_id)); + AVR32_SCIF.pll[pll_id] = 0; + cpu_irq_restore(flags); +} diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/pll.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/pll.h new file mode 100644 index 0000000..df1a5f8 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/pll.h @@ -0,0 +1,228 @@ +/** + * \file + * + * \brief Chip-specific PLL definitions + * + * Copyright (C) 2010 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#ifndef CHIP_PLL_H_INCLUDED +#define CHIP_PLL_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +// Bugzilla #11801 +#ifdef AVR32_SCIF_PLL_VCO_RANGE0_MAX_FREQ +#undef AVR32_SCIF_PLL_VCO_RANGE0_MAX_FREQ +#endif +#define AVR32_SCIF_PLL_VCO_RANGE0_MAX_FREQ 240000000 +#ifdef AVR32_SCIF_PLL_VCO_RANGE0_MIN_FREQ +#undef AVR32_SCIF_PLL_VCO_RANGE0_MIN_FREQ +#endif +#define AVR32_SCIF_PLL_VCO_RANGE0_MIN_FREQ 160000000 +#ifdef AVR32_SCIF_PLL_VCO_RANGE1_MAX_FREQ +#undef AVR32_SCIF_PLL_VCO_RANGE1_MAX_FREQ +#endif +#define AVR32_SCIF_PLL_VCO_RANGE1_MAX_FREQ 180000000 +#ifdef AVR32_SCIF_PLL_VCO_RANGE1_MIN_FREQ +#undef AVR32_SCIF_PLL_VCO_RANGE1_MIN_FREQ +#endif +#define AVR32_SCIF_PLL_VCO_RANGE1_MIN_FREQ 80000000 +/** + * \weakgroup pll_group + * @{ + */ + +#define PLL_MAX_STARTUP_CYCLES ((1 << AVR32_SCIF_PLL_PLLCOUNT_SIZE) - 1) +#define NR_PLLS 2 + +/** + * \brief Number of milliseconds to wait for PLL lock + */ +#define PLL_TIMEOUT_MS \ + div_ceil(1000 * (PLL_MAX_STARTUP_CYCLES * 2), OSC_RCSYS_MIN_HZ) + +/** + * \note The PLL must run at twice this frequency internally, but the + * output frequency may be divided by two by setting the PLLOPT[1] bit. + */ +#define PLL_MIN_HZ 40000000 +#define PLL_MAX_HZ 240000000 + +//! \name Chip-specific PLL options +//@{ +//! VCO frequency range is 80-180 MHz (160-240 MHz if unset). +#define PLL_OPT_VCO_RANGE_LOW 0 +//! Divide output frequency by two +#define PLL_OPT_OUTPUT_DIV 1 +//! Disable wide-bandwidth mode +#define PLL_OPT_WBM_DISABLE 2 +//! Number of PLL options +#define PLL_NR_OPTIONS AVR32_SCIF_PLL_PLLOPT_SIZE +//! The threshold under which to set the #PLL_OPT_VCO_RANGE_LOW option +#define PLL_VCO_LOW_THRESHOLD ((AVR32_SCIF_PLL_VCO_RANGE0_MIN_FREQ \ + + AVR32_SCIF_PLL_VCO_RANGE1_MAX_FREQ) / 2) +//@} + +#ifndef __ASSEMBLY__ + +#include +#include +#include +#include + +enum pll_source { + PLL_SRC_OSC0 = 0, //!< Oscillator 0 + PLL_SRC_OSC1 = 1, //!< Oscillator 1 + PLL_SRC_RC8M = 2, //!< 8MHz/1MHz RC oscillator + PLL_NR_SOURCES, //!< Number of PLL sources +}; + +struct pll_config { + uint32_t ctrl; +}; + +#define pll_get_default_rate(pll_id) \ + ((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE) \ + * CONFIG_PLL##pll_id##_MUL) \ + / CONFIG_PLL##pll_id##_DIV) + +static inline void pll_config_set_option(struct pll_config *cfg, + unsigned int option) +{ + Assert(option < PLL_NR_OPTIONS); + + cfg->ctrl |= 1U << (AVR32_SCIF_PLLOPT + option); +} + +static inline void pll_config_clear_option(struct pll_config *cfg, + unsigned int option) +{ + Assert(option < PLL_NR_OPTIONS); + + cfg->ctrl &= ~(1U << (AVR32_SCIF_PLLOPT + option)); +} + +/** + * The PLL options #PLL_OPT_VCO_RANGE_LOW and #PLL_OPT_OUTPUT_DIV will + * be set automatically based on the calculated target frequency. + */ +static inline void pll_config_init(struct pll_config *cfg, + enum pll_source src, unsigned int div, unsigned int mul) +{ + uint32_t vco_hz; + + Assert(src < PLL_NR_SOURCES); + + /* Calculate internal VCO frequency */ + vco_hz = osc_get_rate(src) * mul; + vco_hz /= div; + Assert(vco_hz >= PLL_MIN_HZ); + Assert(vco_hz <= PLL_MAX_HZ); + + cfg->ctrl = 0; + + /* Bring the internal VCO frequency up to the minimum value */ + if ((vco_hz < PLL_MIN_HZ * 2) && (mul <= 8)) { + mul *= 2; + vco_hz *= 2; + pll_config_set_option(cfg, PLL_OPT_OUTPUT_DIV); + } + + /* Set VCO frequency range according to calculated value */ + if (vco_hz < PLL_VCO_LOW_THRESHOLD) + pll_config_set_option(cfg, PLL_OPT_VCO_RANGE_LOW); + + Assert(mul > 2 && mul <= 16); + Assert(div > 0 && div <= 15); + + cfg->ctrl |= ((mul - 1) << AVR32_SCIF_PLLMUL) + | (div << AVR32_SCIF_PLLDIV) + | (PLL_MAX_STARTUP_CYCLES << AVR32_SCIF_PLLCOUNT) + | (src << AVR32_SCIF_PLLOSC); +} + +#define pll_config_defaults(cfg, pll_id) \ + pll_config_init(cfg, \ + CONFIG_PLL##pll_id##_SOURCE, \ + CONFIG_PLL##pll_id##_DIV, \ + CONFIG_PLL##pll_id##_MUL) + +static inline void pll_config_read(struct pll_config *cfg, unsigned int pll_id) +{ + Assert(pll_id < NR_PLLS); + + cfg->ctrl = AVR32_SCIF.pll[pll_id]; +} + +extern void pll_config_write(const struct pll_config *cfg, unsigned int pll_id); +extern void pll_enable(const struct pll_config *cfg, unsigned int pll_id); +extern void pll_disable(unsigned int pll_id); + +static inline bool pll_is_locked(unsigned int pll_id) +{ + Assert(pll_id < NR_PLLS); + + return !!(AVR32_SCIF.pclksr & (1U << (AVR32_SCIF_PLL0_LOCK + pll_id))); +} + +static inline void pll_enable_source_sync(enum pll_source src) +{ + switch (src) { + case PLL_SRC_OSC0: /* Fall through */ + case PLL_SRC_OSC1: + osc_enable(src); + osc_wait_ready(src); + break; + + case PLL_SRC_RC8M: + osc_enable(OSC_ID_RC8M); + osc_wait_ready(OSC_ID_RC8M); + break; + + default: + // unhandled_case(src); + break; + } +} + +#endif /* __ASSEMBLY__ */ + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif /* CHIP_PLL_H_INCLUDED */ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/sysclk.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/sysclk.c new file mode 100644 index 0000000..6dc383e --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/sysclk.c @@ -0,0 +1,407 @@ +/** + * \file + * + * \brief Chip-specific system clock management functions + * + * Copyright (C) 2009 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#include +#include +#include +#include +#include + +/** + * \weakgroup sysclk_group + * @{ + */ + +/** + * \internal + * \defgroup sysclk_internals_group System Clock internals + * + * System clock management is fairly straightforward apart from one + * thing: Enabling and disabling bus bridges. When all peripherals on a + * given bus are disabled, the bridge to the bus may be disabled. Only + * the PBA, PBB and PBC busses support this, and it is not practical to + * disable the PBA bridge as it includes the Power Manager, so turning + * it off would make it impossible to turn anything back on again. + * + * @{ + */ + +#if ((CONFIG_SYSCLK_CPU_DIV > CONFIG_SYSCLK_PBA_DIV) || \ + (CONFIG_SYSCLK_CPU_DIV > CONFIG_SYSCLK_PBB_DIV) || \ + (CONFIG_SYSCLK_CPU_DIV > CONFIG_SYSCLK_PBC_DIV)) +# error CONFIG_SYSCLK_PBx_DIV must be equal to or more than CONFIG_SYSCLK_CPU_DIV. +#endif + +/** + * \internal + * \name Initial module clock masks + * + * These are the mask values written to the xxxMASK registers during + * initialization if the user has overriden the default behaviour of all clocks + * left enabled. These values assume that: + * - Debugging should be possible + * - The program may be running from flash + * - The PM should be available to unmask other clocks + * - All on-chip RAM should be available + * - INTC, SCIF, PM and GPIO are made permanently available for now; this + * may change in the future. + */ +//@{ +//! \internal +//! \brief Initial value of CPUMASK +#define SYSCLK_INIT_MINIMAL_CPUMASK \ + ((1 << SYSCLK_OCD) \ + | (1 << SYSCLK_SYSTIMER)) +//! \internal +//! \brief Initial value of HSBMASK +#define SYSCLK_INIT_MINIMAL_HSBMASK \ + ((1 << SYSCLK_FLASHC_DATA) \ + | (1 << SYSCLK_PBA_BRIDGE) \ + | (1 << SYSCLK_HSB_RAM)) +//! \internal +//! \brief Initial value of PBAMASK +#define SYSCLK_INIT_MINIMAL_PBAMASK \ + ((1 << SYSCLK_INTC) \ + | (1 << SYSCLK_GPIO) \ + | (1 << SYSCLK_SCIF) \ + | (1 << SYSCLK_PM)) +//! \internal +//! \brief Initial value of PBBMASK +#define SYSCLK_INIT_MINIMAL_PBBMASK 0 +//! \internal +//! \brief Initial value of PBCMASK +#define SYSCLK_INIT_MINIMAL_PBCMASK 0 +//@} + +#if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) +/** + * \brief boolean signaling that the sysclk_init is done. + */ +bool sysclk_initialized = false; +#endif + +/** + * \internal + * \brief Enable a maskable module clock. + * \param bus_id Bus index, given by the \c AVR32_PM_CLK_GRP_xxx definitions. + * \param module_index Index of the module to be enabled. This is the + * bit number in the corresponding xxxMASK register. + */ +void sysclk_priv_enable_module(unsigned int bus_id, unsigned int module_index) +{ + irqflags_t flags; + uint32_t mask; + + flags = cpu_irq_save(); + + /* Enable the clock */ + mask = *(&AVR32_PM.cpumask + bus_id); + mask |= 1U << module_index; + AVR32_PM.unlock = 0xaa000020 + (4 * bus_id); + *(&AVR32_PM.cpumask + bus_id) = mask; + + cpu_irq_restore(flags); +} + +/** + * \internal + * \brief Disable a maskable module clock. + * \param bus_id Bus index, given by the \c AVR32_PM_CLK_GRP_xxx definitions. + * \param module_index Index of the module to be disabled. This is the + * bit number in the corresponding xxxMASK register. + */ +void sysclk_priv_disable_module(unsigned int bus_id, unsigned int module_index) +{ + irqflags_t flags; + uint32_t mask; + + flags = cpu_irq_save(); + + /* Disable the clock */ + mask = *(&AVR32_PM.cpumask + bus_id); + mask &= ~(1U << module_index); + AVR32_PM.unlock = 0xaa000020 + (4 * bus_id); + *(&AVR32_PM.cpumask + bus_id) = mask; + + cpu_irq_restore(flags); +} + +//! @} + +/** + * \brief Set system clock prescaler configuration + * + * This function will change the system clock prescaler configuration to + * match the parameters. + * + * \note The parameters to this function are device-specific. + * + * \param cpu_shift The CPU clock will be divided by \f$2^{cpu\_shift}\f$ + * \param pba_shift The PBA clock will be divided by \f$2^{pba\_shift}\f$ + * \param pbb_shift The PBB clock will be divided by \f$2^{pbb\_shift}\f$ + * \param pbc_shift The PBC clock will be divided by \f$2^{pbc\_shift}\f$ + */ +void sysclk_set_prescalers(unsigned int cpu_shift, + unsigned int pba_shift, unsigned int pbb_shift, + unsigned int pbc_shift) +{ + irqflags_t flags; + uint32_t cpu_cksel = 0; + uint32_t pba_cksel = 0; + uint32_t pbb_cksel = 0; + uint32_t pbc_cksel = 0; + + Assert(cpu_shift <= pba_shift); + Assert(cpu_shift <= pbb_shift); + + if (cpu_shift > 0) + cpu_cksel = ((cpu_shift - 1) << AVR32_PM_CPUSEL) + | (1U << AVR32_PM_CPUDIV); + + if (pba_shift > 0) + pba_cksel = ((pba_shift - 1) << AVR32_PM_PBASEL) + | (1U << AVR32_PM_PBADIV); + + if (pbb_shift > 0) + pbb_cksel = ((pbb_shift - 1) << AVR32_PM_PBBSEL) + | (1U << AVR32_PM_PBBDIV); + + if (pbc_shift > 0) + pbc_cksel = ((pbc_shift - 1) << AVR32_PM_PBCSEL) + | (1U << AVR32_PM_PBCDIV); + + flags = cpu_irq_save(); + AVR32_PM.unlock = 0xaa000000 | AVR32_PM_CPUSEL; + AVR32_PM.cpusel = cpu_cksel; + AVR32_PM.unlock = 0xaa000000 | AVR32_PM_PBASEL; + AVR32_PM.pbasel = pba_cksel; + AVR32_PM.unlock = 0xaa000000 | AVR32_PM_PBBSEL; + AVR32_PM.pbbsel = pbb_cksel; + AVR32_PM.unlock = 0xaa000000 | AVR32_PM_PBCSEL; + AVR32_PM.pbbsel = pbc_cksel; + cpu_irq_restore(flags); +} + +/** + * \brief Change the source of the main system clock. + * + * \param src The new system clock source. Must be one of the constants + * from the System Clock Sources section. + */ +void sysclk_set_source(uint_fast8_t src) +{ + irqflags_t flags; + + Assert(src <= SYSCLK_SRC_RC8M); + + flags = cpu_irq_save(); + AVR32_PM.unlock = 0xaa000000 | AVR32_PM_MCCTRL; + AVR32_PM.mcctrl = src; + cpu_irq_restore(flags); +} + +#if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__) +/** + * \brief Enable the USB generic clock + * + * \pre The USB generick clock must be configurated to 48MHz. + * CONFIG_USBCLK_SOURCE and CONFIG_USBCLK_DIV must be defined with proper + * configuration. The selected clock source must also be configured. + */ +void sysclk_enable_usb(void) +{ + struct genclk_config gcfg; + + genclk_config_defaults(&gcfg, AVR32_USBC_GCLK_NUM); + + /* + * Switch to the system clock selected by the user. + */ + switch (CONFIG_USBCLK_SOURCE) { +#ifdef BOARD_OSC0_HZ + case USBCLK_SRC_OSC0: + osc_enable(OSC_ID_OSC0); + osc_wait_ready(OSC_ID_OSC0); + genclk_config_set_source(&gcfg, GENCLK_SRC_OSC0); + break; +#endif + +#ifdef BOARD_OSC1_HZ + case USBCLK_SRC_OSC1: + osc_enable(OSC_ID_OSC1); + osc_wait_ready(OSC_ID_OSC1); + genclk_config_set_source(&gcfg, GENCLK_SRC_OSC1); + break; +#endif + +#ifdef CONFIG_PLL0_SOURCE + case USBCLK_SRC_PLL0: { + struct pll_config pllcfg; + pll_enable_source_sync(CONFIG_PLL0_SOURCE); + pll_config_defaults(&pllcfg, 0); + pll_enable(&pllcfg, 0); + pll_wait_for_lock(0); + genclk_config_set_source(&gcfg, GENCLK_SRC_PLL0); + break; + } +#endif + +#ifdef CONFIG_PLL1_SOURCE + case USBCLK_SRC_PLL1: { + struct pll_config pllcfg; + pll_enable_source_sync(CONFIG_PLL1_SOURCE); + pll_config_defaults(&pllcfg, 1); + pll_enable(&pllcfg, 1); + pll_wait_for_lock(1); + genclk_config_set_source(&gcfg, GENCLK_SRC_PLL1); + break; + } +#endif + + default: + /* unhandled_case(CONFIG_USBCLK_SOURCE); */ + break; + } + + genclk_config_set_divider(&gcfg, CONFIG_USBCLK_DIV); + genclk_enable(&gcfg, AVR32_USBC_GCLK_NUM); +} + +/** + * \brief Disable the USB generic clock + */ +void sysclk_disable_usb(void) +{ + genclk_disable(AVR32_USBC_GCLK_NUM); +} +#endif // CONFIG_USBCLK_SOURCE + + +void sysclk_init(void) +{ + /* Set up system clock dividers if different from defaults */ + if ((CONFIG_SYSCLK_CPU_DIV > 0) || (CONFIG_SYSCLK_PBA_DIV > 0) || + (CONFIG_SYSCLK_PBB_DIV > 0) || (CONFIG_SYSCLK_PBC_DIV > 0)) { + sysclk_set_prescalers(CONFIG_SYSCLK_CPU_DIV, + CONFIG_SYSCLK_PBA_DIV, + CONFIG_SYSCLK_PBB_DIV, + CONFIG_SYSCLK_PBC_DIV); + } + + /* Switch to system clock selected by user */ + switch (CONFIG_SYSCLK_SOURCE) { + case SYSCLK_SRC_RCSYS: + /* Already running from RCSYS */ + break; + +#ifdef BOARD_OSC0_HZ + case SYSCLK_SRC_OSC0: + osc_enable(OSC_ID_OSC0); + osc_wait_ready(OSC_ID_OSC0); + sysclk_set_source(SYSCLK_SRC_OSC0); + break; +#endif + +#ifdef BOARD_OSC1_HZ + case SYSCLK_SRC_OSC1: + osc_enable(OSC_ID_OSC1); + osc_wait_ready(OSC_ID_OSC1); + sysclk_set_source(SYSCLK_SRC_OSC1); + break; +#endif + +#ifdef CONFIG_PLL0_SOURCE + case SYSCLK_SRC_PLL0: { + struct pll_config pllcfg; + + pll_enable_source_sync(CONFIG_PLL0_SOURCE); + pll_config_defaults(&pllcfg, 0); + pll_enable(&pllcfg, 0); + pll_wait_for_lock(0); + // Set a flash wait state depending on the new cpu frequency. + flash_set_bus_freq(sysclk_get_main_hz()); + sysclk_set_source(SYSCLK_SRC_PLL0); + break; + } +#endif + +#ifdef CONFIG_PLL1_SOURCE + case SYSCLK_SRC_PLL1: { + struct pll_config pllcfg; + + pll_enable_source_sync(CONFIG_PLL1_SOURCE); + pll_config_defaults(&pllcfg, 1); + pll_enable(&pllcfg, 1); + pll_wait_for_lock(1); + // Set a flash wait state depending on the new cpu frequency. + flash_set_bus_freq(sysclk_get_main_hz()); + sysclk_set_source(SYSCLK_SRC_PLL1); + break; + } +#endif + + case SYSCLK_SRC_RC8M: + osc_enable(OSC_ID_RC8M); + osc_wait_ready(OSC_ID_RC8M); + sysclk_set_source(SYSCLK_SRC_RC8M); + break; + } + + /* If the user has specified clock masks, enable only requested clocks */ +#if defined(CONFIG_SYSCLK_INIT_CPUMASK) + AVR32_PM.cpumask = SYSCLK_INIT_MINIMAL_CPUMASK | CONFIG_SYSCLK_INIT_CPUMASK; +#endif +#if defined(CONFIG_SYSCLK_INIT_PBAMASK) + AVR32_PM.pbamask = SYSCLK_INIT_MINIMAL_PBAMASK | CONFIG_SYSCLK_INIT_PBAMASK; +#endif +#if defined(CONFIG_SYSCLK_INIT_PBBMASK) + AVR32_PM.pbbmask = SYSCLK_INIT_MINIMAL_PBBMASK | CONFIG_SYSCLK_INIT_PBBMASK; +#endif +#if defined(CONFIG_SYSCLK_INIT_PBCMASK) + AVR32_PM.pbcmask = SYSCLK_INIT_MINIMAL_PBCMASK | CONFIG_SYSCLK_INIT_PBCMASK; +#endif +#if defined(CONFIG_SYSCLK_INIT_HSBMASK) + AVR32_PM.hsbmask = SYSCLK_INIT_MINIMAL_HSBMASK | CONFIG_SYSCLK_INIT_HSBMASK; +#endif + +#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) + /* Signal that the internal frequencies are setup */ + sysclk_initialized = true; +#endif +} + +//! @} diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/sysclk.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/sysclk.h new file mode 100644 index 0000000..32618b4 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/services/clock/uc3c/sysclk.h @@ -0,0 +1,1169 @@ +/** + * \file + * + * \brief Chip-specific system clock management functions + * + * Copyright (C) 2010 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#ifndef CHIP_SYSCLK_H_INCLUDED +#define CHIP_SYSCLK_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// Bugzilla #11808 +#ifndef AVR32_PDCA_CLK_PBC +#define AVR32_PDCA_CLK_PBC 128 +#endif + +#ifndef AVR32_MDMA_CLK_PBC +#define AVR32_MDMA_CLK_PBC 129 +#endif + +#ifndef AVR32_USART1_CLK_PBC +#define AVR32_USART1_CLK_PBC 130 +#endif + +#ifndef AVR32_SPI0_CLK_PBC +#define AVR32_SPI0_CLK_PBC 131 +#endif + +#ifndef AVR32_CANIF_CLK_PBC +#define AVR32_CANIF_CLK_PBC 132 +#endif + +#ifndef AVR32_TC0_CLK_PBC +#define AVR32_TC0_CLK_PBC 133 +#endif + +#ifndef AVR32_ADCIFA_CLK_PBC +#define AVR32_ADCIFA_CLK_PBC 134 +#endif +/** + * \weakgroup sysclk_group + * @{ + */ + +//! \name Configuration Symbols +//@{ +/** + * \def CONFIG_SYSCLK_SOURCE + * \brief Initial/static main system clock source + * + * The main system clock will be configured to use this clock during + * initialization. + */ +#ifndef CONFIG_SYSCLK_SOURCE +# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RCSYS +#endif +/** + * \def CONFIG_SYSCLK_CPU_DIV + * \brief Initial/static CPU/HSB/PBB clock divider (log2) + * + * The CPU, HSB and PBA clocks will run at + * \f[ + * f_{cpu} = \frac{f_{sys}}{2^\mathrm{CONFIG\_SYSCLK\_CPU\_DIV}}\,\mbox{Hz} + * \f] + * after initialization. + */ +#ifndef CONFIG_SYSCLK_CPU_DIV +# define CONFIG_SYSCLK_CPU_DIV 0 +#endif +/** + * \def CONFIG_SYSCLK_PBA_DIV + * \brief Initial/static PBA clock divider (log2) + * + * The PBA clock will run at + * \f[ + * f_{PBA} = \frac{f_{sys}}{2^\mathrm{CONFIG\_SYSCLK\_PBA\_DIV}}\,\mbox{Hz} + * \f] + * after initialization. + */ +#ifndef CONFIG_SYSCLK_PBA_DIV +# define CONFIG_SYSCLK_PBA_DIV 0 +#endif +/** + * \def CONFIG_SYSCLK_PBB_DIV + * \brief Initial/static PBB clock divider (log2) + * + * The PBB clock will run at + * \f[ + * f_{PBB} = \frac{f_{sys}}{2^\mathrm{CONFIG\_SYSCLK\_PBB\_DIV}}\,\mbox{Hz} + * \f] + * after initialization. + */ +#ifndef CONFIG_SYSCLK_PBB_DIV +# define CONFIG_SYSCLK_PBB_DIV 0 +#endif +/** + * \def CONFIG_SYSCLK_PBC_DIV + * \brief Initial/static PBC clock divider (log2) + * + * The PBC clock will run at + * \f[ + * f_{PBC} = \frac{f_{sys}}{2^\mathrm{CONFIG\_SYSCLK\_PBC\_DIV}}\,\mbox{Hz} + * \f] + * after initialization. + */ +#ifndef CONFIG_SYSCLK_PBC_DIV +# define CONFIG_SYSCLK_PBC_DIV 0 +#endif + +/** + * \def CONFIG_SYSCLK_INIT_CPUMASK + * \brief Configuration symbol for the CPU clocks enabled at power-on after the + * sysclock module has been initialized. By default, all CPU clocks are left + * enabled, however to save power these can be automatically disabled by defining + * this value to a mask of \c SYSCLOCK_xxx settings. + * + * If this symbol is not defined, then all CPU clocks are left enabled. + * + * This symbol may be defined in \ref conf_clock.h. + */ +#ifdef __DOXYGEN__ +# define CONFIG_SYSCLK_INIT_CPUMASK +#endif + +/** + * \def CONFIG_SYSCLK_INIT_PBAMASK + * \brief Configuration symbol for the PBA clocks enabled at power-on after the + * sysclock module has been initialized. By default, all PBA clocks are left + * enabled, however to save power these can be automatically disabled by defining + * this value to a mask of \c SYSCLOCK_xxx settings. + * + * If this symbol is not defined, then all PBA clocks are left enabled. + * + * This symbol may be defined in \ref conf_clock.h. + */ +#ifdef __DOXYGEN__ +# define CONFIG_SYSCLK_INIT_PBAMASK +#endif + +/** + * \def CONFIG_SYSCLK_INIT_PBBMASK + * \brief Configuration symbol for the PBB clocks enabled at power-on after the + * sysclock module has been initialized. By default, all PBB clocks are left + * enabled, however to save power these can be automatically disabled by defining + * this value to a mask of \c SYSCLOCK_xxx settings. + * + * If this symbol is not defined, then all PBB clocks are left enabled. + * + * This symbol may be defined in \ref conf_clock.h. + */ +#ifdef __DOXYGEN__ +# define CONFIG_SYSCLK_INIT_PBBMASK +#endif + +/** + * \def CONFIG_SYSCLK_INIT_PBCMASK + * \brief Configuration symbol for the PBC clocks enabled at power-on after the + * sysclock module has been initialized. By default, all PBC clocks are left + * enabled, however to save power these can be automatically disabled by defining + * this value to a mask of \c SYSCLOCK_xxx settings. + * + * If this symbol is not defined, then all PBC clocks are left enabled. + * + * This symbol may be defined in \ref conf_clock.h. + */ +#ifdef __DOXYGEN__ +# define CONFIG_SYSCLK_INIT_PBCMASK +#endif +//@} + +//! \name System clock source +//@{ +#define SYSCLK_SRC_RCSYS 0 //!< System RC oscillator +#define SYSCLK_SRC_OSC0 1 //!< Oscillator 0 +#define SYSCLK_SRC_OSC1 2 //!< Oscillator 1 +#define SYSCLK_SRC_PLL0 3 //!< Phase Locked Loop 0 +#define SYSCLK_SRC_PLL1 4 //!< Phase Locked Loop 1 +#define SYSCLK_SRC_RC8M 5 //!< 8 MHz RC oscillator +//@} + +//! \name USB Clock Sources +//@{ +#define USBCLK_SRC_OSC0 1 //!< Use OSC0 +#define USBCLK_SRC_OSC1 2 //!< Use OSC1 +#define USBCLK_SRC_PLL0 3 //!< Use PLL0 +#define USBCLK_SRC_PLL1 4 //!< Use PLL1 +//@} + +//! \name Clocks derived from the CPU clock +//@{ +//! On-Chip Debug system +#define SYSCLK_OCD AVR32_OCD_CLK_CPU +//! COUNT/COMPARE system registers +#define SYSCLK_SYSTIMER AVR32_CORE_CLK_CPU_COUNT +//@} + +//! \name Clocks derived from the HSB clock +//@{ +//! Secure Access Unit HSB interface +#define SYSCLK_SAU_HSB (AVR32_SAU_CLK_HSB % 32) +//! PDCA memory interface +#define SYSCLK_PDCA_HSB (AVR32_PDCA_CLK_HSB % 32) +//! MDMA memory interface +#define SYSCLK_MDMA_HSB (AVR32_MDMA_CLK_HSB % 32) +//! USBC DMA and FIFO interface +#define SYSCLK_USBC_DATA (AVR32_USBC_CLK_HSB % 32) +//! CANIF DMA interface +#define SYSCLK_CANIF_DATA (AVR32_CANIF_CLK_HSB % 32) +//! Flash data interface +#define SYSCLK_FLASHC_DATA (AVR32_FLASHC_CLK_HSB % 32) +//! HSB<->PBA bridge +#define SYSCLK_PBA_BRIDGE (AVR32_HMATRIX_CLK_HSB_PBA_BRIDGE % 32) +//! HSB<->PBB bridge +#define SYSCLK_PBB_BRIDGE (AVR32_HMATRIX_CLK_HSB_PBB_BRIDGE % 32) +//! HSB<->PBC bridge +#define SYSCLK_PBC_BRIDGE (AVR32_HMATRIX_CLK_HSB_PBC_BRIDGE % 32) +//! HSB RAM +#define SYSCLK_HSB_RAM (AVR32_RAM_CLK_HSB % 32) +//! External Bus Interface +#define SYSCLK_EBI (AVR32_EBI_CLK_HSB % 32) +//! Peripheral Event Controller +#define SYSCLK_PEVC_HSB (AVR32_PEVC_CLK_HSB % 32) +//@} + +//! \name Clocks derived from the PBA clock +//@{ +//! Internal interrupt controller +#define SYSCLK_INTC (AVR32_INTC_CLK_PBA % 32) +//! PM/RTC/EIM configuration +#define SYSCLK_PM (AVR32_PM_CLK_PBA % 32) +//! System Control Interface +#define SYSCLK_SCIF (AVR32_SCIF_CLK_PBA % 32) +//! Asynchronous Timer +#define SYSCLK_AST (AVR32_AST_CLK_PBA % 32) +//! Watchdog Timer +#define SYSCLK_WDT (AVR32_WDT_CLK_PBA % 32) +//! External Interrupt Controller +#define SYSCLK_EIC (AVR32_EIC_CLK_PBA % 32) +//! Frequency Meter +#define SYSCLK_FREQM (AVR32_FREQM_CLK_PBA % 32) +//! General-Purpose I/O +#define SYSCLK_GPIO (AVR32_GPIO_CLK_PBA % 32) +//! USART 0 +#define SYSCLK_USART0 (AVR32_USART0_CLK_PBA % 32) +//! USART 2 +#define SYSCLK_USART2 (AVR32_USART2_CLK_PBA % 32) +//! USART 3 +#define SYSCLK_USART3 (AVR32_USART3_CLK_PBA % 32) +//! SPI Controller 1 +#define SYSCLK_SPI1 (AVR32_SPI1_CLK_PBA % 32) +//! TWI Master 0 +#define SYSCLK_TWIM0 (AVR32_TWIM0_CLK_PBA % 32) +//! TWI Master 1 +#define SYSCLK_TWIM1 (AVR32_TWIM1_CLK_PBA % 32) +//! TWI Slave 0 +#define SYSCLK_TWIS0 (AVR32_TWIS0_CLK_PBA % 32) +//! TWI Slave 1 +#define SYSCLK_TWIS1 (AVR32_TWIS1_CLK_PBA % 32) +//! Pulse Width Modulator +#define SYSCLK_PWM (AVR32_PWM_CLK_PBA % 32) +//! Quadrature Decoder 0 +#define SYSCLK_QDEC0 (AVR32_QDEC0_CLK_PBA % 32) +//! Quadrature Decoder 1 +#define SYSCLK_QDEC1 (AVR32_QDEC1_CLK_PBA % 32) +//! Timer/Counter 1 +#define SYSCLK_TC1 (AVR32_TC1_CLK_PBA % 32) +//! Peripheral Event Controller +#define SYSCLK_PEVC_REGS (AVR32_PEVC_CLK_PBA % 32) +//! Analog Comparator 0 +#define SYSCLK_ACIFA0 (AVR32_ACIFA0_CLK_PBA % 32) +//! Analog Comparator 1 +#define SYSCLK_ACIFA1 (AVR32_ACIFA1_CLK_PBA % 32) +//! D/A Converter 0 +#define SYSCLK_DACIFB0 (AVR32_DACIFB0_CLK_PBA % 32) +//! D/A Converter 1 +#define SYSCLK_DACIFB1 (AVR32_DACIFB1_CLK_PBA % 32) +//! aWire UART +#define SYSCLK_AW (AVR32_AW_CLK_PBA % 32) +//@} + +//! \name Clocks derived from the PBB clock +//@{ +//! Flash Controller registers +#define SYSCLK_FLASHC_REGS (AVR32_FLASHC_CLK_PBB % 32) +//! USBB registers +#define SYSCLK_USBC_REGS (AVR32_USBC_CLK_PBB % 32) +//! HSB Matrix configuration +#define SYSCLK_HMATRIX (AVR32_HMATRIX_CLK_PBB % 32) +//! Secure Access Unit register +#define SYSCLK_SAU_REGS (AVR32_SAU_CLK_PBB % 32) +//! Static Memory Controller registers +#define SYSCLK_SMC_REGS (AVR32_SMC_CLK_PBB % 32) +//! SDRAM Controller registers +#define SYSCLK_SDRAMC_REGS (AVR32_SDRAMC_CLK_PBB % 32) +//@} + +//! \name Clocks derived from the PBC clock +//@{ +//! PDCA peripheral bus interface +#define SYSCLK_PDCA_PB (AVR32_PDCA_CLK_PBC % 32) +//! MDMA registers +#define SYSCLK_MDMA_REGS (AVR32_MDMA_CLK_PBC % 32) +//! USART 1 +#define SYSCLK_USART1 (AVR32_USART1_CLK_PBC % 32) +//! SPI Controller 0 +#define SYSCLK_SPI0 (AVR32_SPI0_CLK_PBC % 32) +//! CANIF registers +#define SYSCLK_CANIF_REGS (AVR32_CANIF_CLK_PBC % 32) +//! Timer/Counter 0 +#define SYSCLK_TC0 (AVR32_TC0_CLK_PBC % 32) +//! A/D Converter +#define SYSCLK_ADCIFA (AVR32_ADCIFA_CLK_PBC % 32) +//@} + +#ifndef __ASSEMBLY__ + +#include +#include +#include +#include + +// Use the slow clock (RCOSC) with no prescaling if config was empty. +#ifndef CONFIG_SYSCLK_SOURCE +# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RCSYS +#endif /* CONFIG_SYSCLK_SOURCE */ + +/** + * \def CONFIG_SYSCLK_CPU_DIV + * \brief Configuration symbol for dividing the CPU clock frequency by + * \f$2^{CONFIG\_SYSCLK\_CPU\_DIV}\f$ + * + * If this symbol is not defined, the CPU clock frequency is not divided. + * + * This symbol may be defined in \ref conf_clock.h. + */ +#ifndef CONFIG_SYSCLK_CPU_DIV +# define CONFIG_SYSCLK_CPU_DIV 0 +#endif /* CONFIG_SYSCLK_CPU_DIV */ + +/** + * \def CONFIG_SYSCLK_INIT_HSBMASK + * \brief Configuration symbol for the HSB clocks enabled at power-on after the + * sysclock module has been initialized. By default, all HSB clocks are left + * enabled, however to save power these can be automatically disabled by defining + * this value to a mask of \c SYSCLOCK_xxx settings. + * + * If this symbol is not defined, then all HSB clocks are left enabled. + * + * This symbol may be defined in \ref conf_clock.h. + */ +#ifdef __DOXYGEN__ +# define CONFIG_SYSCLK_INIT_HSBMASK +#endif + +/** + * \def CONFIG_SYSCLK_PBA_DIV + * \brief Configuration symbol for dividing the PBA clock frequency by + * \f$2^{CONFIG\_SYSCLK\_PBA\_DIV}\f$ + * + * If this symbol is not defined, the PBA clock frequency is not divided. + * + * This symbol may be defined in \ref conf_clock.h. + */ +#ifndef CONFIG_SYSCLK_PBA_DIV +# define CONFIG_SYSCLK_PBA_DIV 0 +#endif /* CONFIG_SYSCLK_PBA_DIV */ + +/** + * \def CONFIG_SYSCLK_PBB_DIV + * \brief Configuration symbol for dividing the PBB clock frequency by + * \f$2^{CONFIG\_SYSCLK\_PBB\_DIV}\f$ + * + * If this symbol is not defined, the PBB clock frequency is not divided. + * + * This symbol may be defined in \ref conf_clock.h. + */ +#ifndef CONFIG_SYSCLK_PBB_DIV +# define CONFIG_SYSCLK_PBB_DIV 0 +#endif /* CONFIG_SYSCLK_PBB_DIV */ + +/** + * \def CONFIG_SYSCLK_PBC_DIV + * \brief Configuration symbol for dividing the PBC clock frequency by + * \f$2^{CONFIG\_SYSCLK\_PBC\_DIV}\f$ + * + * If this symbol is not defined, the PBC clock frequency is not divided. + * + * This symbol may be defined in \ref conf_clock.h. + */ +#ifndef CONFIG_SYSCLK_PBC_DIV +# define CONFIG_SYSCLK_PBC_DIV 0 +#endif /* CONFIG_SYSCLK_PBC_DIV */ + +/** + * \def CONFIG_USBCLK_SOURCE + * \brief Configuration symbol for the USB generic clock source + * + * Sets the clock source to use for the USB. The source must also be properly + * configured. + * + * Define this to one of the \c USBCLK_SRC_xxx settings. Leave it undefined if + * USB is not required. + */ +#ifdef __DOXYGEN__ +# define CONFIG_USBCLK_SOURCE +#endif + +/** + * \def CONFIG_USBCLK_DIV + * \brief Configuration symbol for the USB generic clock divider setting + * + * Sets the clock division for the USB generic clock. If a USB clock source is + * selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be + * defined. + * + * Define this as any value that does not exceed \c GENCLK_DIV_MAX, and which + * will give a 48 MHz clock frequency from the selected source. + */ +#ifdef __DOXYGEN__ +# define CONFIG_USBCLK_DIV +#endif + +/** + * \name Querying the system clock and its derived clocks + * + * The following functions may be used to query the current frequency of + * the system clock and the CPU and bus clocks derived from it. + * sysclk_get_main_hz() and sysclk_get_cpu_hz() can be assumed to be + * available on all platforms, although some platforms may define + * additional accessors for various chip-internal bus clocks. These are + * usually not intended to be queried directly by generic code. + */ +//@{ + +/** + * \brief Return the current rate in Hz of the main system clock + * + * \todo This function assumes that the main clock source never changes + * once it's been set up, and that PLL0 always runs at the compile-time + * configured default rate. While this is probably the most common + * configuration, which we want to support as a special case for + * performance reasons, we will at some point need to support more + * dynamic setups as well. + */ +#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) +extern bool sysclk_initialized; +#endif +static inline uint32_t sysclk_get_main_hz(void) +{ +#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) + if (!sysclk_initialized ) { + return OSC_RCSYS_NOMINAL_HZ; + } +#endif + + switch (CONFIG_SYSCLK_SOURCE) { + case SYSCLK_SRC_RCSYS: + return OSC_RCSYS_NOMINAL_HZ; + +#ifdef BOARD_OSC0_HZ + case SYSCLK_SRC_OSC0: + return BOARD_OSC0_HZ; +#endif + +#ifdef BOARD_OSC1_HZ + case SYSCLK_SRC_OSC1: + return BOARD_OSC1_HZ; +#endif + +#ifdef CONFIG_PLL0_SOURCE + case SYSCLK_SRC_PLL0: + return pll_get_default_rate(0); +#endif + +#ifdef CONFIG_PLL1_SOURCE + case SYSCLK_SRC_PLL1: + return pll_get_default_rate(1); +#endif + + case SYSCLK_SRC_RC8M: + return OSC_RC8M_NOMINAL_HZ; + + default: + /* unhandled_case(CONFIG_SYSCLK_SOURCE); */ + return 0; + } +} + +/** + * \brief Return the current rate in Hz of the CPU clock + * + * \todo This function assumes that the CPU always runs at the system + * clock frequency. We want to support at least two more scenarios: + * Fixed CPU/bus clock dividers (config symbols) and dynamic CPU/bus + * clock dividers (which may change at run time). Ditto for all the bus + * clocks. + * + * \return Frequency of the CPU clock, in Hz. + */ +static inline uint32_t sysclk_get_cpu_hz(void) +{ + return sysclk_get_main_hz() >> CONFIG_SYSCLK_CPU_DIV; +} + +/** + * \brief Return the current rate in Hz of the High-Speed Bus clock + * + * \return Frequency of the High Speed Peripheral Bus clock, in Hz. + */ +static inline uint32_t sysclk_get_hsb_hz(void) +{ + return sysclk_get_main_hz() >> CONFIG_SYSCLK_CPU_DIV; +} + +/** + * \brief Return the current rate in Hz of the Peripheral Bus A clock + * + * \return Frequency of the Peripheral Bus A clock, in Hz. + */ +static inline uint32_t sysclk_get_pba_hz(void) +{ + return sysclk_get_main_hz() >> CONFIG_SYSCLK_PBA_DIV; +} + +/** + * \brief Return the current rate in Hz of the Peripheral Bus B clock + * + * \return Frequency of the Peripheral Bus B clock, in Hz. + */ +static inline uint32_t sysclk_get_pbb_hz(void) +{ + return sysclk_get_main_hz() >> CONFIG_SYSCLK_CPU_DIV; +} + +/** + * \brief Return the current rate in Hz of the Peripheral Bus C clock + * + * \return Frequency of the Peripheral Bus C clock, in Hz. + */ +static inline uint32_t sysclk_get_pbc_hz(void) +{ + return sysclk_get_main_hz() >> CONFIG_SYSCLK_PBC_DIV; +} + +/** + * \brief Retrieves the current rate in Hz of the Peripheral Bus clock attached + * to the specified peripheral. + * + * \param module Pointer to the module's base address. + * + * \return Frequency of the bus attached to the specified peripheral, in Hz. + */ +static inline uint32_t sysclk_get_peripheral_bus_hz(const volatile void *module) +{ + /* Fallthroughs intended for modules sharing the same peripheral bus. */ + switch ((uintptr_t)module) { + case AVR32_INTC_ADDRESS: + case AVR32_PM_ADDRESS: + case AVR32_SCIF_ADDRESS: + case AVR32_AST_ADDRESS: + case AVR32_WDT_ADDRESS: + case AVR32_EIC_ADDRESS: + case AVR32_FREQM_ADDRESS: + case AVR32_GPIO_ADDRESS: + case AVR32_USART0_ADDRESS: + case AVR32_USART2_ADDRESS: + case AVR32_USART3_ADDRESS: + case AVR32_SPI1_ADDRESS: + case AVR32_TWIM0_ADDRESS: + case AVR32_TWIM1_ADDRESS: + case AVR32_TWIS0_ADDRESS: + case AVR32_TWIS1_ADDRESS: + case AVR32_PWM_ADDRESS: + case AVR32_QDEC0_ADDRESS: + case AVR32_QDEC1_ADDRESS: + case AVR32_TC1_ADDRESS: + case AVR32_PEVC_ADDRESS: + case AVR32_ACIFA0_ADDRESS: + case AVR32_ACIFA1_ADDRESS: + case AVR32_DACIFB0_ADDRESS: + case AVR32_DACIFB1_ADDRESS: + case AVR32_AW_ADDRESS: + return sysclk_get_pba_hz(); + + case AVR32_FLASHC_ADDRESS: + case AVR32_USBC_ADDRESS: + case AVR32_HMATRIXB_ADDRESS: + case AVR32_SAU_ADDRESS: +#if defined(AVR32_SMC_ADDRESS) + case AVR32_SMC_ADDRESS: +#endif +#if defined(AVR32_SDRAMC_ADDRESS) + case AVR32_SDRAMC_ADDRESS: +#endif + return sysclk_get_pbb_hz(); + + case AVR32_PDCA_ADDRESS: + case AVR32_MDMA_ADDRESS: + case AVR32_USART1_ADDRESS: + case AVR32_SPI0_ADDRESS: + case AVR32_CANIF_ADDRESS: + case AVR32_TC0_ADDRESS: + case AVR32_ADCIFA_ADDRESS: + return sysclk_get_pbc_hz(); + + default: + Assert(false); + return 0; + } +} + +//@} + +extern void sysclk_priv_enable_module(unsigned int bus_id, + unsigned int module_index); +extern void sysclk_priv_disable_module(unsigned int bus_id, + unsigned int module_index); + +//! \name Enabling and disabling synchronous clocks +//@{ + +/** + * \brief Enable a module clock derived from the CPU clock + * \param index Index of the module clock in the CPUMASK register + */ +static inline void sysclk_enable_cpu_module(unsigned int index) +{ + sysclk_priv_enable_module(AVR32_PM_CLK_GRP_CPU, index); +} + +/** + * \brief Disable a module clock derived from the CPU clock + * \param index Index of the module clock in the CPUMASK register + */ +static inline void sysclk_disable_cpu_module(unsigned int index) +{ + sysclk_priv_disable_module(AVR32_PM_CLK_GRP_CPU, index); +} + +/** + * \brief Enable a module clock derived from the HSB clock + * \param index Index of the module clock in the HSBMASK register + */ +static inline void sysclk_enable_hsb_module(unsigned int index) +{ + sysclk_priv_enable_module(AVR32_PM_CLK_GRP_HSB, index); +} + +/** + * \brief Disable a module clock derived from the HSB clock + * \param index Index of the module clock in the HSBMASK register + */ +static inline void sysclk_disable_hsb_module(unsigned int index) +{ + sysclk_priv_disable_module(AVR32_PM_CLK_GRP_HSB, index); +} + +/** + * \brief Enable a module clock derived from the PBA clock + * \param index Index of the module clock in the PBAMASK register + */ +static inline void sysclk_enable_pba_module(unsigned int index) +{ + sysclk_priv_enable_module(AVR32_PM_CLK_GRP_PBA, index); +} + +/** + * \brief Disable a module clock derived from the PBA clock + * \param index Index of the module clock in the PBAMASK register + */ +static inline void sysclk_disable_pba_module(unsigned int index) +{ + sysclk_priv_disable_module(AVR32_PM_CLK_GRP_PBA, index); +} + +/** + * \brief Enable a module clock derived from the PBB clock + * \param index Index of the module clock in the PBBMASK register + */ +static inline void sysclk_enable_pbb_module(unsigned int index) +{ + sysclk_priv_enable_module(AVR32_PM_CLK_GRP_PBB, index); +} + +/** + * \brief Disable a module clock derived from the PBB clock + * \param index Index of the module clock in the PBBMASK register + */ +static inline void sysclk_disable_pbb_module(unsigned int index) +{ + sysclk_priv_disable_module(AVR32_PM_CLK_GRP_PBB, index); +} + +/** + * \brief Enable a module clock derived from the PBC clock + * \param index Index of the module clock in the PBCMASK register + */ +static inline void sysclk_enable_pbc_module(unsigned int index) +{ + sysclk_priv_enable_module(AVR32_PM_CLK_GRP_PBC, index); +} + +/** + * \brief Disable a module clock derived from the PBC clock + * \param index Index of the module clock in the PBCMASK register + */ +static inline void sysclk_disable_pbc_module(unsigned int index) +{ + sysclk_priv_disable_module(AVR32_PM_CLK_GRP_PBC, index); +} + +/** + * \brief Enable a peripheral's clock from its base address. + * + * Enables the clock to a peripheral, given its base address. If the peripheral + * has an associated clock on the HSB bus, this will be enabled also. + * + * \param module Pointer to the module's base address. + */ +static inline void sysclk_enable_peripheral_clock(const volatile void *module) +{ + switch ((uintptr_t)module) { + case AVR32_INTC_ADDRESS: + sysclk_enable_pba_module(SYSCLK_INTC); + break; + + case AVR32_PM_ADDRESS: + sysclk_enable_pba_module(SYSCLK_PM); + break; + + case AVR32_SCIF_ADDRESS: + sysclk_enable_pba_module(SYSCLK_SCIF); + break; + + case AVR32_AST_ADDRESS: + sysclk_enable_pba_module(SYSCLK_AST); + break; + + case AVR32_WDT_ADDRESS: + sysclk_enable_pba_module(SYSCLK_WDT); + break; + + case AVR32_EIC_ADDRESS: + sysclk_enable_pba_module(SYSCLK_EIC); + break; + + case AVR32_FREQM_ADDRESS: + sysclk_enable_pba_module(SYSCLK_FREQM); + break; + + case AVR32_GPIO_ADDRESS: + sysclk_enable_pba_module(SYSCLK_GPIO); + break; + + case AVR32_USART0_ADDRESS: + sysclk_enable_pba_module(SYSCLK_USART0); + break; + + case AVR32_USART2_ADDRESS: + sysclk_enable_pba_module(SYSCLK_USART2); + break; + + case AVR32_USART3_ADDRESS: + sysclk_enable_pba_module(SYSCLK_USART2); + break; + + case AVR32_SPI1_ADDRESS: + sysclk_enable_pba_module(SYSCLK_SPI1); + break; + + case AVR32_TWIM0_ADDRESS: + sysclk_enable_pba_module(SYSCLK_TWIM0); + break; + + case AVR32_TWIM1_ADDRESS: + sysclk_enable_pba_module(SYSCLK_TWIM1); + break; + + case AVR32_TWIS0_ADDRESS: + sysclk_enable_pba_module(SYSCLK_TWIS0); + break; + + case AVR32_TWIS1_ADDRESS: + sysclk_enable_pba_module(SYSCLK_TWIS1); + break; + + case AVR32_PWM_ADDRESS: + sysclk_enable_pba_module(SYSCLK_PWM); + break; + + case AVR32_QDEC0_ADDRESS: + sysclk_enable_pba_module(SYSCLK_QDEC0); + break; + + case AVR32_QDEC1_ADDRESS: + sysclk_enable_pba_module(SYSCLK_QDEC1); + break; + + case AVR32_TC1_ADDRESS: + sysclk_enable_pba_module(SYSCLK_TC1); + break; + + case AVR32_PEVC_ADDRESS: + sysclk_enable_hsb_module(SYSCLK_PEVC_HSB); + sysclk_enable_pba_module(SYSCLK_PEVC_REGS); + break; + + case AVR32_ACIFA0_ADDRESS: + sysclk_enable_pba_module(SYSCLK_ACIFA0); + break; + + case AVR32_ACIFA1_ADDRESS: + sysclk_enable_pba_module(SYSCLK_ACIFA1); + break; + + case AVR32_DACIFB0_ADDRESS: + sysclk_enable_pba_module(SYSCLK_DACIFB0); + break; + + case AVR32_DACIFB1_ADDRESS: + sysclk_enable_pba_module(SYSCLK_DACIFB1); + break; + + case AVR32_AW_ADDRESS: + sysclk_enable_pba_module(SYSCLK_AW); + break; + + case AVR32_FLASHC_ADDRESS: + sysclk_enable_hsb_module(SYSCLK_FLASHC_DATA); + sysclk_enable_pbb_module(SYSCLK_FLASHC_REGS); + break; + + case AVR32_USBC_ADDRESS: + sysclk_enable_hsb_module(SYSCLK_USBC_DATA); + sysclk_enable_pbb_module(SYSCLK_USBC_REGS); + break; + + case AVR32_HMATRIXB_ADDRESS: + sysclk_enable_pbb_module(SYSCLK_HMATRIX); + break; + + case AVR32_SAU_ADDRESS: + sysclk_enable_hsb_module(SYSCLK_SAU_HSB); + sysclk_enable_pbb_module(SYSCLK_SAU_REGS); + break; + +#if defined(AVR32_SMC_ADDRESS) + case AVR32_SMC_ADDRESS: + sysclk_enable_pbb_module(SYSCLK_SMC_REGS); + break; +#endif + +#if defined(AVR32_SDRAMC_ADDRESS) + case AVR32_SDRAMC_ADDRESS: + sysclk_enable_pbb_module(SYSCLK_SDRAMC_REGS); + break; +#endif + + case AVR32_PDCA_ADDRESS: + sysclk_enable_hsb_module(SYSCLK_PDCA_HSB); + sysclk_enable_pbc_module(SYSCLK_PDCA_PB); + break; + + case AVR32_MDMA_ADDRESS: + sysclk_enable_pbc_module(SYSCLK_MDMA_REGS); + break; + + case AVR32_USART1_ADDRESS: + sysclk_enable_pbc_module(SYSCLK_USART1); + break; + + case AVR32_SPI0_ADDRESS: + sysclk_enable_pbc_module(SYSCLK_SPI0); + break; + + case AVR32_CANIF_ADDRESS: + sysclk_enable_hsb_module(SYSCLK_CANIF_DATA); + sysclk_enable_pbc_module(SYSCLK_CANIF_REGS); + break; + + case AVR32_TC0_ADDRESS: + sysclk_enable_pbc_module(SYSCLK_TC0); + break; + + case AVR32_ADCIFA_ADDRESS: + sysclk_enable_pbc_module(SYSCLK_ADCIFA); + break; + + default: + Assert(false); + return; + } +} + +/** + * \brief Disable a peripheral's clock from its base address. + * + * Disables the clock to a peripheral, given its base address. If the peripheral + * has an associated clock on the HSB bus, this will be disabled also. + * + * \param module Pointer to the module's base address. + */ +static inline void sysclk_disable_peripheral_clock(const volatile void *module) +{ + switch ((uintptr_t)module) { + case AVR32_INTC_ADDRESS: + sysclk_disable_pba_module(SYSCLK_INTC); + break; + + case AVR32_PM_ADDRESS: + sysclk_disable_pba_module(SYSCLK_PM); + break; + + case AVR32_SCIF_ADDRESS: + sysclk_disable_pba_module(SYSCLK_SCIF); + break; + + case AVR32_AST_ADDRESS: + sysclk_disable_pba_module(SYSCLK_AST); + break; + + case AVR32_WDT_ADDRESS: + sysclk_disable_pba_module(SYSCLK_WDT); + break; + + case AVR32_EIC_ADDRESS: + sysclk_disable_pba_module(SYSCLK_EIC); + break; + + case AVR32_FREQM_ADDRESS: + sysclk_disable_pba_module(SYSCLK_FREQM); + break; + + case AVR32_GPIO_ADDRESS: + sysclk_disable_pba_module(SYSCLK_GPIO); + break; + + case AVR32_USART0_ADDRESS: + sysclk_disable_pba_module(SYSCLK_USART0); + break; + + case AVR32_USART2_ADDRESS: + sysclk_disable_pba_module(SYSCLK_USART2); + break; + + case AVR32_USART3_ADDRESS: + sysclk_disable_pba_module(SYSCLK_USART2); + break; + + case AVR32_SPI1_ADDRESS: + sysclk_disable_pba_module(SYSCLK_SPI1); + break; + + case AVR32_TWIM0_ADDRESS: + sysclk_disable_pba_module(SYSCLK_TWIM0); + break; + + case AVR32_TWIM1_ADDRESS: + sysclk_disable_pba_module(SYSCLK_TWIM1); + break; + + case AVR32_TWIS0_ADDRESS: + sysclk_disable_pba_module(SYSCLK_TWIS0); + break; + + case AVR32_TWIS1_ADDRESS: + sysclk_disable_pba_module(SYSCLK_TWIS1); + break; + + case AVR32_PWM_ADDRESS: + sysclk_disable_pba_module(SYSCLK_PWM); + break; + + case AVR32_QDEC0_ADDRESS: + sysclk_disable_pba_module(SYSCLK_QDEC0); + break; + + case AVR32_QDEC1_ADDRESS: + sysclk_disable_pba_module(SYSCLK_QDEC1); + break; + + case AVR32_TC1_ADDRESS: + sysclk_disable_pba_module(SYSCLK_TC1); + break; + + case AVR32_PEVC_ADDRESS: + sysclk_disable_hsb_module(SYSCLK_PEVC_HSB); + sysclk_disable_pba_module(SYSCLK_PEVC_REGS); + break; + + case AVR32_ACIFA0_ADDRESS: + sysclk_disable_pba_module(SYSCLK_ACIFA0); + break; + + case AVR32_ACIFA1_ADDRESS: + sysclk_disable_pba_module(SYSCLK_ACIFA1); + break; + + case AVR32_DACIFB0_ADDRESS: + sysclk_disable_pba_module(SYSCLK_DACIFB0); + break; + + case AVR32_DACIFB1_ADDRESS: + sysclk_disable_pba_module(SYSCLK_DACIFB1); + break; + + case AVR32_AW_ADDRESS: + sysclk_disable_pba_module(SYSCLK_AW); + break; + + case AVR32_FLASHC_ADDRESS: + sysclk_disable_hsb_module(SYSCLK_FLASHC_DATA); + sysclk_disable_pbb_module(SYSCLK_FLASHC_REGS); + break; + + case AVR32_USBC_ADDRESS: + sysclk_disable_hsb_module(SYSCLK_USBC_DATA); + sysclk_disable_pbb_module(SYSCLK_USBC_REGS); + break; + + case AVR32_HMATRIXB_ADDRESS: + sysclk_disable_pbb_module(SYSCLK_HMATRIX); + break; + + case AVR32_SAU_ADDRESS: + sysclk_disable_hsb_module(SYSCLK_SAU_HSB); + sysclk_disable_pbb_module(SYSCLK_SAU_REGS); + break; + +#if defined(AVR32_SMC_ADDRESS) + case AVR32_SMC_ADDRESS: + sysclk_disable_pbb_module(SYSCLK_SMC_REGS); + break; +#endif + +#if defined(AVR32_SDRAMC_ADDRESS) + case AVR32_SDRAMC_ADDRESS: + sysclk_disable_pbb_module(SYSCLK_SDRAMC_REGS); + break; +#endif + + case AVR32_PDCA_ADDRESS: + sysclk_disable_hsb_module(SYSCLK_PDCA_HSB); + sysclk_disable_pbc_module(SYSCLK_PDCA_PB); + break; + + case AVR32_MDMA_ADDRESS: + sysclk_disable_pbc_module(SYSCLK_MDMA_REGS); + break; + + case AVR32_USART1_ADDRESS: + sysclk_disable_pbc_module(SYSCLK_USART1); + break; + + case AVR32_SPI0_ADDRESS: + sysclk_disable_pbc_module(SYSCLK_SPI0); + break; + + case AVR32_CANIF_ADDRESS: + sysclk_disable_hsb_module(SYSCLK_CANIF_DATA); + sysclk_disable_pbc_module(SYSCLK_CANIF_REGS); + break; + + case AVR32_TC0_ADDRESS: + sysclk_disable_pbc_module(SYSCLK_TC0); + break; + + case AVR32_ADCIFA_ADDRESS: + sysclk_disable_pbc_module(SYSCLK_ADCIFA); + break; + + default: + Assert(false); + return; + } +} + +//@} + +//! \name System Clock Source and Prescaler configuration +//@{ + +extern void sysclk_set_prescalers(unsigned int cpu_shift, + unsigned int pba_shift, unsigned int pbb_shift, + unsigned int pbc_shift); +extern void sysclk_set_source(uint_fast8_t src); + +//@} + +#if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__) + +/** + * \def USBCLK_STARTUP_TIMEOUT + * \brief Number of us to wait for USB clock to start + */ +#if CONFIG_USBCLK_SOURCE==USBCLK_SRC_OSC0 +# define USBCLK_STARTUP_TIMEOUT (OSC0_STARTUP_TIMEOUT*(1000000/AVR32_SCIF_RCOSC_FREQUENCY)) +#elif CONFIG_USBCLK_SOURCE==USBCLK_SRC_OSC1 +# define USBCLK_STARTUP_TIMEOUT (OSC1_STARTUP_TIMEOUT*(1000000/AVR32_SCIF_RCOSC_FREQUENCY)) +#elif CONFIG_USBCLK_SOURCE==USBCLK_SRC_PLL0 +# if CONFIG_PLL0_SOURCE==PLL_SRC_OSC0 +# define USBCLK_STARTUP_TIMEOUT (OSC0_STARTUP_TIMEOUT*(1000000/AVR32_SCIF_RCOSC_FREQUENCY)) +# elif CONFIG_PLL0_SOURCE==PLL_SRC_OSC1 +# define USBCLK_STARTUP_TIMEOUT (OSC1_STARTUP_TIMEOUT*(1000000/AVR32_SCIF_RCOSC_FREQUENCY)) +# else +# error Unknown value for CONFIG_PLL0_SOURCE, see conf_clock.h. +# endif +#elif CONFIG_USBCLK_SOURCE==USBCLK_SRC_PLL1 +# if CONFIG_PLL1_SOURCE==PLL_SRC_OSC0 +# define USBCLK_STARTUP_TIMEOUT (OSC0_STARTUP_TIMEOUT*(1000000/AVR32_SCIF_RCOSC_FREQUENCY)) +# elif CONFIG_PLL1_SOURCE==PLL_SRC_OSC1 +# define USBCLK_STARTUP_TIMEOUT (OSC1_STARTUP_TIMEOUT*(1000000/AVR32_SCIF_RCOSC_FREQUENCY)) +# else +# error Unknown value for CONFIG_PLL1_SOURCE, see conf_clock.h. +# endif +#else +# error Unknown value for CONFIG_USBCLK_SOURCE, see conf_clock.h. +#endif + +extern void sysclk_enable_usb(void); +extern void sysclk_disable_usb(void); +#endif + +extern void sysclk_init(void); + +#endif /* !__ASSEMBLY__ */ + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif /* CHIP_SYSCLK_H_INCLUDED */ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/utils/interrupt.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/utils/interrupt.h new file mode 100644 index 0000000..f2c8770 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/utils/interrupt.h @@ -0,0 +1,132 @@ +/** + * \file + * + * \brief Global interrupt management for 8- and 32-bit AVR + * + * Copyright (C) 2010 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#ifndef UTILS_INTERRUPT_H +#define UTILS_INTERRUPT_H + +#include + +#if XMEGA || MEGA +# include "interrupt/interrupt_avr8.h" +#elif UC3 +# include "interrupt/interrupt_avr32.h" +#else +# error Unsupported device. +#endif + +/** + * \defgroup interrupt_group Global interrupt management + * + * This is a driver for global enabling and disabling of interrupts. + * + * @{ + */ + +#if defined(__DOXYGEN__) +/** + * \def CONFIG_INTERRUPT_FORCE_INTC + * \brief Force usage of the ASF INTC driver + * + * Predefine this symbol when preprocessing to force the use of the ASF INTC driver. + * This is useful to ensure compatibilty accross compilers and shall be used only when required + * by the application needs. + */ +# define CONFIG_INTERRUPT_FORCE_INTC +#endif + +//! \name Global interrupt flags +//@{ +/** + * \typedef irqflags_t + * \brief Type used for holding state of interrupt flag + */ + +/** + * \def cpu_irq_enable + * \brief Enable interrupts globally + */ + +/** + * \def cpu_irq_disable + * \brief Disable interrupts globally + */ + +/** + * \fn irqflags_t cpu_irq_save(void) + * \brief Get and clear the global interrupt flags + * + * Use in conjunction with \ref cpu_irq_restore. + * + * \return Current state of interrupt flags. + * + * \note This function leaves interrupts disabled. + */ + +/** + * \fn void cpu_irq_restore(irqflags_t flags) + * \brief Restore global interrupt flags + * + * Use in conjunction with \ref cpu_irq_save. + * + * \param flags State to set interrupt flag to. + */ + +/** + * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags) + * \brief Check if interrupts are globally enabled in supplied flags + * + * \param flags Currents state of interrupt flags. + * + * \return True if interrupts are enabled. + */ + +/** + * \def cpu_irq_is_enabled + * \brief Check if interrupts are globally enabled + * + * \return True if interrupts are enabled. + */ +//@} + +//! @} + +/** + * \ingroup interrupt_group + * \defgroup interrupt_deprecated_group Deprecated interrupt definitions + */ + +#endif /* UTILS_INTERRUPT_H */ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/utils/interrupt/interrupt_avr32.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/utils/interrupt/interrupt_avr32.h new file mode 100644 index 0000000..b94bf33 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/asf/common/utils/interrupt/interrupt_avr32.h @@ -0,0 +1,342 @@ +/** + * \file + * + * \brief Global interrupt management for 32-bit AVR + * + * Copyright (C) 2010 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#ifndef UTILS_INTERRUPT_INTERRUPT_H +#define UTILS_INTERRUPT_INTERRUPT_H + +#include +#include + +/** + * \weakgroup interrupt_group + * + * @{ + */ + +//! Pointer to interrupt handler. +#if (defined __GNUC__) +typedef void (*__int_handler)(void); +#elif (defined __ICCAVR32__) +typedef void (__interrupt *__int_handler)(void); +#endif + +/** + * \name Interrupt Service Routine definition and registration + * + * @{ + */ +#if defined(__GNUC__) || defined(__DOXYGEN__) + +/** + * \brief Define service routine + * + * With GCC, this macro only causes the function to be defined as an interrupt + * service routine, i.e., it does not add any initialization code. A valid + * function name is required for use with \ref irq_register_handler. + * + * With IAR, this macro defines the function as an interrupt service routine and + * causes the compiler to add initialization code for the interrupt controller + * (INTC). The interrupt group and level, as well as a valid function name are + * therefore required.\n + * \note If \ref CONFIG_INTERRUPT_FORCE_INTC is defined, only a valid function + * name is required for use with \ref irq_register_handler. The initialization + * code will be handled by the interrupt controller itself. + * + * Usage: + * \code + * ISR(foo_irq_handler, AVR32_xxx_IRQ_GROUP, n) + * { + * // Function definition + * ... + * } + * \endcode + * + * \param func Name for the function, needed by \ref irq_register_handler. + * \param int_grp Interrupt group to define service routine for. + * \param int_lvl Priority level to set for the interrupt group, in the range + * \c 0 to \c 3. + * + * \note The interrupt groups can be found in the device header files for the + * IAR toolchain (avr32/io\.h). + * + * \todo Update to use IRQ numbers when these are made available in the + * device header files of both IAR and GCC. + */ +# define ISR(func, int_grp, int_lvl) \ + __attribute__((__interrupt__)) static void func (void) + +#elif defined(__ICCAVR32__) +# define ISR0(...) _Pragma(#__VA_ARGS__) +# define ISR(func, int_grp, int_lvl) \ + ISR0(handler=int_grp, int_lvl) \ + __interrupt static void func (void) +#endif + +#if defined(__GNUC__) || defined(__DOXYGEN__) || defined(CONFIG_INTERRUPT_FORCE_INTC) +# include + +/** + * \brief Initialize interrupt vectors + * + * With GCC, this macro adds code for initialization of the interrupt vectors + * with the driver for the interrupt controller (INTC). + * + * With IAR and unless \ref CONFIG_INTERRUPT_FORCE_INTC is defined this macro + * adds no code, since initialization of the INTC is handled by the compiler. + * \note Defining \ref CONFIG_INTERRUPT_FORCE_INTC will force the use of the + * INTC driver, replacing the compiler built-in interrupt handler. + * + * This must be called prior to \ref irq_register_handler. + */ +# define irq_initialize_vectors() INTC_init_interrupts() + +/** + * \brief Register handler for interrupt + * + * With GCC, this macro adds code for registering an interrupt handler with the + * driver for the interrupt controller (INTC). + * + * With IAR and unless \ref CONFIG_INTERRUPT_FORCE_INTC is defined this macro + * adds no code, since initialization of the INTC is handled by the compiler. + * \note Defining \ref CONFIG_INTERRUPT_FORCE_INTC will force the use of the + * INTC driver, replacing the compiler built-in interrupt handler. + * + * \param func Name of handler function to register for interrupt. + * \param int_num Number of the interrupt line to register function for. + * \param int_lvl Priority level to set for the interrupt's group, in the range + * \c 0 to \c 3. + * + * Usage: + * \code + * irq_initialize_vectors(); + * irq_register_handler(foo_irq_handler, AVR32_xxx_IRQ, n); + * \endcode + * + * \note The function \a func must be defined with the \ref ISR macro. + * \note The interrupt line number can be found in the device header files for + * the GCC toolchain (avr32/\.h). + */ +# define irq_register_handler(func, int_num, int_lvl) \ + INTC_register_interrupt(func, int_num, \ + TPASTE2(AVR32_INTC_INT, int_lvl)) + +#elif defined(__ICCAVR32__) +# define irq_initialize_vectors() do{ } while(0) +# define irq_register_handler(func, int_num, int_lvl) do{ } while(0) +#endif + +//@} + +#if (defined __GNUC__) +# define cpu_irq_enable() \ + do { \ + barrier(); \ + __builtin_csrf(AVR32_SR_GM_OFFSET); \ + } while (0) +# define cpu_irq_disable() \ + do { \ + __builtin_ssrf(AVR32_SR_GM_OFFSET); \ + barrier(); \ + } while (0) +#elif (defined __ICCAVR32__) +# if (defined CONFIG_INTERRUPT_FORCE_INTC) +# define cpu_irq_enable() \ + do { \ + barrier(); \ + __clear_status_flag(AVR32_SR_GM_OFFSET); \ + } while(0) +# define cpu_irq_disable() \ + do { \ + __set_status_flag(AVR32_SR_GM_OFFSET); \ + barrier(); \ + } while (0) +# else +# define cpu_irq_enable() __enable_interrupt() +# define cpu_irq_disable() __disable_interrupt() +# endif +#endif + +typedef uint32_t irqflags_t; + +static inline irqflags_t cpu_irq_save(void) +{ + irqflags_t flags; + + flags = sysreg_read(AVR32_SR); + cpu_irq_disable(); + + return flags; +} + +static inline bool cpu_irq_is_enabled_flags(irqflags_t flags) +{ + return !(flags & AVR32_SR_GM_MASK); +} + +static inline void cpu_irq_restore(irqflags_t flags) +{ + barrier(); +#if defined(__ICCAVR32__) + // Barrier " __asm__ __volatile__ ("")" + // Don't work with sysreg_write(AVR32_SR, flags) + if( cpu_irq_is_enabled_flags(flags) ) { + cpu_irq_enable(); + } +#else + sysreg_write(AVR32_SR, flags); +#endif + barrier(); +} + +#define cpu_irq_is_enabled() cpu_irq_is_enabled_flags(sysreg_read(AVR32_SR)) + +//! \name Global interrupt levels +//@{ + +/** + * \brief Check if interrupt level is enabled in supplied flags + * + * \param flags State of interrupt flags. + * \param level Bit position for interrupt level. + * + * \return True if interrupt level is enabled. + */ +static inline bool cpu_irq_level_is_enabled_flags(irqflags_t flags, + uint32_t level) +{ + return !(flags & (1 << level)); +} + +/** + * \brief Check if interrupt level is enabled + * + * \param level Interrupt level (0 to 3). + * + * \return True if interrupt level \a level is enabled. + * + * \note The interrupt level must be known at compile time. + */ +#define cpu_irq_level_is_enabled(level) \ + cpu_irq_level_is_enabled_flags(sysreg_read(AVR32_SR), \ + TPASTE3(AVR32_SR_I, level, M_OFFSET)) + +#if defined(__GNUC__) || defined(__DOXYGEN__) +/** + * \brief Enable interrupt level + * + * \param level Interrupt level to enable (0 to 3). + * + * \note The interrupt level must be known at compile time. + */ +# define cpu_irq_enable_level(level) \ + do { \ + barrier(); \ + __builtin_csrf(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \ + } while (0) + +/** + * \brief Disable interrupt level + * + * \param level Interrupt level to disable (0 to 3). + * + * \note The interrupt level must be known at compile time. + */ +# define cpu_irq_disable_level(level) \ + do { \ + __builtin_ssrf(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \ + barrier(); \ + } while (0) + +#elif (defined __ICCAVR32__) +# define cpu_irq_enable_level(level) \ + do { \ + barrier(); \ + __clear_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \ + } while(0) +# define cpu_irq_disable_level(level) \ + do { \ + __set_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \ + barrier(); \ + } while (0) +#endif + +//@} + +//@} + +/** + * \weakgroup interrupt_deprecated_group + * @{ + */ + +#define Enable_global_interrupt() cpu_irq_enable() +#define Disable_global_interrupt() cpu_irq_disable() +#define Is_global_interrupt_enabled() cpu_irq_is_enabled() + +#define Enable_interrupt_level(level) cpu_irq_enable_level(level) +#define Disable_interrupt_level(level) cpu_irq_disable_level(level) +#define Is_interrupt_level_enabled(level) cpu_irq_level_is_enabled(level) + +/** + * \name Interrupt protection of code sections + * \note Use \ref cpu_irq_save and \ref cpu_irq_restore instead of these macros. + * @{ + */ + +/** + * \brief Start section with code protected against interrupts + */ +#define AVR32_ENTER_CRITICAL_REGION() \ + { \ + bool global_interrupt_enabled = Is_global_interrupt_enabled(); \ + Disable_global_interrupt(); + +/** + * \brief End section with code protected against interrupts + * + * \note This macro must always be used in conjunction with + * \ref AVR32_ENTER_CRITICAL_REGION so that interrupts are enabled again. + */ +#define AVR32_LEAVE_CRITICAL_REGION() \ + if (global_interrupt_enabled) Enable_global_interrupt(); \ + } + +//@} + +//@} + +#endif /* UTILS_INTERRUPT_INTERRUPT_H */ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/can1ce.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/can1ce.h new file mode 100644 index 0000000..e076e19 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/can1ce.h @@ -0,0 +1,141 @@ +#ifndef CAN_CE_H +#define CAN_CE_H + + + +/*Konfiguration für CAN-Subsystem*/ +#define CAN__nPollCycle 10 /*ms*/ + + +#define CAN_MakeDbConfig \ +MakeTxMessages() \ + /* dummy message 1 */ \ + /* NAME, CAN_Ch, ID, DLC, Tx-Mode, Cycle, Pre-Tx-Callback */ \ + MakeTxMsg( CAN_nenMsg_Dummy001, CAN_nenCh0, 0x103, 8, TxModeCyclic, 100, CAN_vNoPreTx_Cb ) \ + /* Msg.-ID, Sig.-ID, Start-Bit, Size, Init-Timeout-Ersatz */ \ + MakeSignal( CAN_nenMsg_Dummy001, CAN_nenSig_Dummy001_01, 0, 8, 0 ) \ + MakeSignal( CAN_nenMsg_Dummy001, CAN_nenSig_Dummy001_02, 8, 8, 0 ) \ + MakeSignal( CAN_nenMsg_Dummy001, CAN_nenSig_Dummy001_03, 16, 8, 0 ) \ + MakeSignal( CAN_nenMsg_Dummy001, CAN_nenSig_Dummy001_04, 24, 8, 0 ) \ + MakeSignal( CAN_nenMsg_Dummy001, CAN_nenSig_Dummy001_05, 32, 8, 0 ) \ + MakeSignal( CAN_nenMsg_Dummy001, CAN_nenSig_Dummy001_06, 40, 8, 0 ) \ + MakeSignal( CAN_nenMsg_Dummy001, CAN_nenSig_Dummy001_07, 48, 8, 0 ) \ + MakeSignal( CAN_nenMsg_Dummy001, CAN_nenSig_Dummy001_08, 56, 8, 0 ) \ + MakeTxMsgEnd() \ +MakeTxMessagesEnd() \ + \ +/*RX Messages */ \ +MakeRxMessages() \ +MakeRxMessagesEnd() \ + +/******************************/ +/* Konfiguration CAN-Treiber */ +/******************************/ + +#define CAN_MessageBoxConfig \ +/* Ch.-Name, Baud-Rate, Rx-Indication_Cb, Tx-Confirmation_Cb */\ +MakeCanChannel( CAN_nenCh0, 1000000, CANIF_vRxIndication, CANIF_vTxConfirmation ) \ + /* MsgBoxId, ID-Value, ID-Mask, Rx/Tx/unused */ \ + MakeMsgBox( CAN_enCh0MBox0, 0x000, 0, CAN__nenMbMode_Tx ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh0MBox1, 0x000, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh0MBox2, 0x000, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh0MBox3, 0x000, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh0MBox4, 0x000, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh0MBox5, 0x000, 0x000, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh0MBox6, 0x000, 0x000, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh0MBox7, 0x000, 0x000, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh0MBox8, 0x000, 0x000, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh0MBox9, 0x000, 0x000, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh0MBox10, 0x000, 0x000, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh0MBox11, 0x000, 0x000, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh0MBox12, 0, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh0MBox13, 0, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh0MBox14, 0, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh0MBox15, 0, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ +MakeCanChannelEnd() \ +/* Ch.-Name, Baud-Rate, Rx-Indication_Cb, Tx-Confirmation_Cb */\ +MakeCanChannel( CAN_nenCh1, 1000000, CANIF_vRxIndication, CANIF_vTxConfirmation ) \ + /* MsgBoxId, ID-Value, ID-Mask, Rx/Tx/unused */ \ + MakeMsgBox( CAN_enCh1MBox0, 0x000, 0, CAN__nenMbMode_Tx ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh1MBox1, 0x000, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh1MBox2, 0x000, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh1MBox3, 0x000, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh1MBox4, 0x000, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh1MBox5, 0x000, 0x000, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh1MBox6, 0x000, 0x000, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh1MBox7, 0x000, 0x000, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh1MBox8, 0x000, 0x000, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh1MBox9, 0x000, 0x000, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh1MBox10, 0x000, 0x000, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh1MBox11, 0x000, 0x000, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh1MBox12, 0, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh1MBox13, 0, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh1MBox14, 0, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ + MakeMsgBox( CAN_enCh1MBox15, 0, 0, CAN__nenMbMode_NotUsed ) \ + MakeRxMsg( CAN__nenMb_Invalid ) \ + MakeMsgBoxEnd() \ +MakeCanChannelEnd() \ + +#endif /*CAN_CE_H*/ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/cdef.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/cdef.h new file mode 100644 index 0000000..b8b2670 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/cdef.h @@ -0,0 +1,70 @@ +#ifndef CDEF_H +#define CDEF_H + +#ifdef _WINECU_ + +#ifndef __cplusplus + +typedef unsigned char bool; +#define true (1==1) +#define false (!true) +#endif /*__cplusplus*/ + +/** Unsigned 8-bit datatype : 0..255 */ + typedef unsigned char uint8_t; + +/** Unsigned 16-bit datatype: 0..65535 */ + typedef unsigned short int uint16_t; + +/** Unsigned 32-bit datatype: 0..4294967295 */ + typedef unsigned long int uint32_t; + +#ifdef WIN32 /* @Ale080429 */ + typedef unsigned __int64 uint64_t; +#else + typedef unsigned long long int uint64_t; +#endif /* WIN32 */ + + +/** Signed 8-bit datatype : -128...+127 */ + typedef signed char int8_t; + +/** Signed 16-bit datatype : -32768..+32767 */ + typedef signed short int int16_t; + +/** Signed 32-bit datatype : -2147483648..2147483647 */ + typedef signed long int int32_t; + +#ifdef WIN32 /* @Ale080429 */ + typedef signed __int64 int64_t; +#else + typedef signed long long int int64_t; +#endif + +#define inline __inline + +#endif /*_WINECU_*/ + +/*Target*/ +#ifndef _WINECU_ +#include "avr_compiler.h" +#endif + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#ifndef MIN +#define MIN( A, B ) ((A)<(B)?(A):(B)) +#endif //MIN + +#ifndef MAX +#define MAX( A, B ) ((A)>(B)?(A):(B)) +#endif //MAX + + +#endif /*CDEF_H*/ + +/*Allgemein*/ + +#define compile_time_assert(x) extern int compile_time_assert[(x) ? 1 : -1] diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/CANDCI.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/CANDCI.h new file mode 100644 index 0000000..fcfc926 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/CANDCI.h @@ -0,0 +1,89 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief CAN driver for AVR32 UC3. + * + * This file contains basic functions for the AVR32 CAN, with support for all + * modes, settings and clock speeds. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a CAN module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ + + +#ifndef _CANDCI_H +#define _CANDCI_H + +//_____ I N C L U D E S ________________________________________________________ +#include "avr32/io.h" +#include "compiler.h" +#include "can.h" +#include "board.h" + +/* + * + *//* + * Mail Box Definition + */ +// ----------------------------------------------------------------- +// CAN Message Definition: Tx Message +#if defined (__ICCAVR32__) +can_msg_t msg_tx_sot = +{ + 0x000, // Identifier + 0x000, // Mask + 0x0000000000000000LL, // Data +}; +#else +can_msg_t msg_tx_sot = +{ + { + { + .id = 0x000, // Identifier + .id_mask = 0x000, // Mask + }, + }, + .data.u64 = 0x0000000000000000LL, // Data +}; +#endif +can_msg_t pcan_msg[2][16]; +// MOB Message Definition: Tx Message +can_mob_t appli_tx_msg[2][16]; + +#endif // _CANDCI_H diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/conf_board.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/conf_board.h new file mode 100644 index 0000000..3275aab --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/conf_board.h @@ -0,0 +1,11 @@ +/** + * \file + * + * \brief User board configuration template + * + */ + +#ifndef CONF_BOARD_H +#define CONF_BOARD_H + +#endif // CONF_BOARD_H diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/conf_can.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/conf_can.h new file mode 100644 index 0000000..1032fb5 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/conf_can.h @@ -0,0 +1,97 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief CAN Configuration File for AVR32 UC3. + * + * This file contains basic functions for the AVR32 CAN, with support for all + * modes, settings and clock speeds. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a CAN module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2009 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an Atmel + * AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + */ +#ifndef _CONF_CAN_H +#define _CONF_CAN_H + +//! Define the number of MOB per channel. It is a fixed value: 16. +#define NB_MOB_CHANNEL 16 +//! Setup the usage of Autobaud feature, here the stack does not support it +#define CAN_AUTOBAUD false +//! Setup the usage of CAN Under interruption +#define CAN_LIB_UNDER_INTERRUPT + +#define CAN_SPEED CAN_SPEED_500//CAN_SPEED_1000 + +#if CAN_SPEED == CAN_SPEED_1000 +/* CAN config für 1MBit/s */ +#define CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz +#define CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz_SJW 1 +#define CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz_PRES 1 +#define CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz_PRS 2 +#define CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz_PHS1 1 +#define CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz_PHS2 1 +#elif CAN_SPEED == CAN_SPEED_500 +/* CAN config 500kBit/s */ +#define CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz +#define CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz_SJW 1 +#define CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz_PRES 1 +#define CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz_PRS 2 +#define CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz_PHS1 6 +#define CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz_PHS2 4 +#endif + +#define BAUDRATE CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz +#define BAUDRATE_SJW CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz_SJW +#define BAUDRATE_PRES CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz_PRES +#define BAUDRATE_PRS CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz_PRS +#define BAUDRATE_PHS1 CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz_PHS1 +#define BAUDRATE_PHS2 CAN_BAUDRATE_1MHZ_CANCLOCK_16MHz_PHS2 + +#define CAN0_INT_TX_LEVEL AVR32_INTC_INT0 +#define CAN0_INT_RX_LEVEL AVR32_INTC_INT0 +#define CAN0_INT_ERR_LEVEL AVR32_INTC_INT0 +#define CAN0_INT_BOFF_LEVEL AVR32_INTC_INT0 +#define CAN0_INT_WAKE_UP_LEVEL AVR32_INTC_INT0 + +#define CAN1_INT_TX_LEVEL AVR32_INTC_INT0 +#define CAN1_INT_RX_LEVEL AVR32_INTC_INT0 +#define CAN1_INT_ERR_LEVEL AVR32_INTC_INT0 +#define CAN1_INT_BOFF_LEVEL AVR32_INTC_INT0 +#define CAN1_INT_WAKE_UP_LEVEL AVR32_INTC_INT0 + +#endif // _CONF_CAN_H diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/conf_clock.h b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/conf_clock.h new file mode 100644 index 0000000..48ee84e --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/config/conf_clock.h @@ -0,0 +1,55 @@ +/** + * \file + * + * \brief Chip-specific system clock manager configuration + * + * Copyright (C) 2011 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ +#ifndef CONF_CLOCK_H_INCLUDED +#define CONF_CLOCK_H_INCLUDED + +#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL0 + +/* Fbus = Fsys / (2 ^ BUS_div) */ +#define CONFIG_SYSCLK_CPU_DIV 0 +#define CONFIG_SYSCLK_PBA_DIV 1 +#define CONFIG_SYSCLK_PBB_DIV 1 +#define CONFIG_SYSCLK_PBC_DIV 1 + +#define CONFIG_PLL0_SOURCE PLL_SRC_OSC0 + +/* Fpll0 = (Fclk * PLL_mul) / PLL_div */ +#define CONFIG_PLL0_MUL 4 +#define CONFIG_PLL0_DIV 1 + +#endif /* CONF_CLOCK_H_INCLUDED */ diff --git a/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/main.c b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/main.c new file mode 100644 index 0000000..b25906f --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/CANVerificationTool/src/main.c @@ -0,0 +1,29 @@ +/** + * \file + * + * \brief Empty user application template + * + */ + +/* + * Include header files for all drivers that have been imported from + * AVR Software Framework (ASF). + */ +#include +#include "START1C1.h" + +void board_init(void) +{ + /* This function is meant to contain board-specific initialization code + * for, e.g., the I/O pins. The initialization can rely on application- + * specific board configuration, found in conf_board.h. + */ +} + +int main (void) +{ + board_init(); + + // Insert application code here, after the board has been initialized. + START_vMain(); +} diff --git a/Master/Masterarbeit/src/CANVerificationTool/doc/Doxyfile b/Master/Masterarbeit/src/CANVerificationTool/doc/Doxyfile new file mode 100644 index 0000000..fc94577 --- /dev/null +++ b/Master/Masterarbeit/src/CANVerificationTool/doc/Doxyfile @@ -0,0 +1,1813 @@ +# Doxyfile 1.7.6.1 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project +# +# All text after a hash (#) is considered a comment and will be ignored +# The format is: +# TAG = value [value, ...] +# For lists items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (" ") + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the config file +# that follow. The default is UTF-8 which is also the encoding used for all +# text before the first occurrence of this tag. Doxygen uses libiconv (or the +# iconv built into libc) for the transcoding. See +# http://www.gnu.org/software/libiconv for the list of possible encodings. + +DOXYFILE_ENCODING = UTF-8 + +# The PROJECT_NAME tag is a single word (or sequence of words) that should +# identify the project. Note that if you do not use Doxywizard you need +# to put quotes around the project name if it contains spaces. + +PROJECT_NAME = "Atmel CAN verification tool" + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. +# This could be handy for archiving the generated documentation or +# if some version control system is used. + +PROJECT_NUMBER = + +# Using the PROJECT_BRIEF tag one can provide an optional one line description +# for a project that appears at the top of each page and should give viewer +# a quick idea about the purpose of the project. Keep the description short. + +PROJECT_BRIEF = + +# With the PROJECT_LOGO tag one can specify an logo or icon that is +# included in the documentation. The maximum height of the logo should not +# exceed 55 pixels and the maximum width should not exceed 200 pixels. +# Doxygen will copy the logo to the output directory. + +PROJECT_LOGO = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) +# base path where the generated documentation will be put. +# If a relative path is entered, it will be relative to the location +# where doxygen was started. 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Doxygen will use this +# information to generate all constant output in the proper language. +# The default language is English, other supported languages are: +# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, +# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, +# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English +# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, +# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak, +# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. + +OUTPUT_LANGUAGE = English + +# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will +# include brief member descriptions after the members that are listed in +# the file and class documentation (similar to JavaDoc). +# Set to NO to disable this. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend +# the brief description of a member or function before the detailed description. +# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator +# that is used to form the text in various listings. Each string +# in this list, if found as the leading text of the brief description, will be +# stripped from the text and the result after processing the whole list, is +# used as the annotated text. Otherwise, the brief description is used as-is. +# If left blank, the following values are used ("$name" is automatically +# replaced with the name of the entity): "The $name class" "The $name widget" +# "The $name file" "is" "provides" "specifies" "contains" +# "represents" "a" "an" "the" + +ABBREVIATE_BRIEF = "The $name class" \ + "The $name widget" \ + "The $name file" \ + is \ + provides \ + specifies \ + contains \ + represents \ + a \ + an \ + the + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# Doxygen will generate a detailed section even if there is only a brief +# description. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all +# inherited members of a class in the documentation of that class as if those +# members were ordinary class members. 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If set to NO the members will appear in +# declaration order. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the +# brief documentation of file, namespace and class members alphabetically +# by member name. If set to NO (the default) the members will appear in +# declaration order. + +SORT_BRIEF_DOCS = NO + +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen +# will sort the (brief and detailed) documentation of class members so that +# constructors and destructors are listed first. If set to NO (the default) +# the constructors will appear in the respective orders defined by +# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. +# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO +# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. + +SORT_MEMBERS_CTORS_1ST = NO + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the +# hierarchy of group names into alphabetical order. If set to NO (the default) +# the group names will appear in their defined order. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be +# sorted by fully-qualified names, including namespaces. If set to +# NO (the default), the class list will be sorted only by class name, +# not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the +# alphabetical list. + +SORT_BY_SCOPE_NAME = NO + +# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to +# do proper type resolution of all parameters of a function it will reject a +# match between the prototype and the implementation of a member function even +# if there is only one candidate or it is obvious which candidate to choose +# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen +# will still accept a match between prototype and implementation in such cases. + +STRICT_PROTO_MATCHING = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or +# disable (NO) the todo list. This list is created by putting \todo +# commands in the documentation. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or +# disable (NO) the test list. This list is created by putting \test +# commands in the documentation. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or +# disable (NO) the bug list. This list is created by putting \bug +# commands in the documentation. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or +# disable (NO) the deprecated list. This list is created by putting +# \deprecated commands in the documentation. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional +# documentation sections, marked by \if sectionname ... \endif. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines +# the initial value of a variable or macro consists of for it to appear in +# the documentation. If the initializer consists of more lines than specified +# here it will be hidden. Use a value of 0 to hide initializers completely. +# The appearance of the initializer of individual variables and macros in the +# documentation can be controlled using \showinitializer or \hideinitializer +# command in the documentation regardless of this setting. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated +# at the bottom of the documentation of classes and structs. If set to YES the +# list will mention the files that were used to generate the documentation. + +SHOW_USED_FILES = YES + +# If the sources in your project are distributed over multiple directories +# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy +# in the documentation. The default is NO. + +SHOW_DIRECTORIES = NO + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. +# This will remove the Files entry from the Quick Index and from the +# Folder Tree View (if specified). The default is YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the +# Namespaces page. This will remove the Namespaces entry from the Quick Index +# and from the Folder Tree View (if specified). The default is YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command , where is the value of +# the FILE_VERSION_FILTER tag, and is the name of an input file +# provided by doxygen. Whatever the program writes to standard output +# is used as the file version. See the manual for examples. + +FILE_VERSION_FILTER = + +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed +# by doxygen. The layout file controls the global structure of the generated +# output files in an output format independent way. The create the layout file +# that represents doxygen's defaults, run doxygen with the -l option. +# You can optionally specify a file name after the option, if omitted +# DoxygenLayout.xml will be used as the name of the layout file. + +LAYOUT_FILE = + +# The CITE_BIB_FILES tag can be used to specify one or more bib files +# containing the references data. This must be a list of .bib files. The +# .bib extension is automatically appended if omitted. Using this command +# requires the bibtex tool to be installed. See also +# http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style +# of the bibliography can be controlled using LATEX_BIB_STYLE. To use this +# feature you need bibtex and perl available in the search path. + +CITE_BIB_FILES = + +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated +# by doxygen. Possible values are YES and NO. If left blank NO is used. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated by doxygen. Possible values are YES and NO. If left blank +# NO is used. + +WARNINGS = YES + +# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings +# for undocumented members. If EXTRACT_ALL is set to YES then this flag will +# automatically be disabled. + +WARN_IF_UNDOCUMENTED = YES + +# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some +# parameters in a documented function, or documenting parameters that +# don't exist or using markup commands wrongly. + +WARN_IF_DOC_ERROR = YES + +# The WARN_NO_PARAMDOC option can be enabled to get warnings for +# functions that are documented, but have no documentation for their parameters +# or return value. If set to NO (the default) doxygen will only warn about +# wrong or incomplete parameter documentation, but not about the absence of +# documentation. + +WARN_NO_PARAMDOC = NO + +# The WARN_FORMAT tag determines the format of the warning messages that +# doxygen can produce. The string should contain the $file, $line, and $text +# tags, which will be replaced by the file and line number from which the +# warning originated and the warning text. Optionally the format may contain +# $version, which will be replaced by the version of the file (if it could +# be obtained via FILE_VERSION_FILTER) + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning +# and error messages should be written. If left blank the output is written +# to stderr. + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag can be used to specify the files and/or directories that contain +# documented source files. You may enter file names like "myfile.cpp" or +# directories like "/usr/src/myproject". Separate the files or directories +# with spaces. + +INPUT = ../CANVerificationTool + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is +# also the default input encoding. Doxygen uses libiconv (or the iconv built +# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for +# the list of possible encodings. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank the following patterns are tested: +# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh +# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py +# *.f90 *.f *.for *.vhd *.vhdl + +FILE_PATTERNS = *.c \ + *.cc \ + *.cxx \ + *.cpp \ + *.c++ \ + *.d \ + *.java \ + *.ii \ + *.ixx \ + *.ipp \ + *.i++ \ + *.inl \ + *.h \ + *.hh \ + *.hxx \ + *.hpp \ + *.h++ \ + *.idl \ + *.odl \ + *.cs \ + *.php \ + *.php3 \ + *.inc \ + *.m \ + *.mm \ + *.dox \ + *.py \ + *.f90 \ + *.f \ + *.for \ + *.vhd \ + *.vhdl + +# The RECURSIVE tag can be used to turn specify whether or not subdirectories +# should be searched for input files as well. Possible values are YES and NO. +# If left blank NO is used. + +RECURSIVE = YES + +# The EXCLUDE tag can be used to specify files and/or directories that should be +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. +# Note that relative paths are relative to the directory from which doxygen is +# run. + +EXCLUDE = + +# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or +# directories that are symbolic links (a Unix file system feature) are excluded +# from the input. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. Note that the wildcards are matched +# against the file with absolute path, so to exclude all test directories +# for example use the pattern */test/* + +EXCLUDE_PATTERNS = */asf/* + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test + +EXCLUDE_SYMBOLS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or +# directories that contain example code fragments that are included (see +# the \include command). + +EXAMPLE_PATH = + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank all files are included. + +EXAMPLE_PATTERNS = * + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude +# commands irrespective of the value of the RECURSIVE tag. +# Possible values are YES and NO. If left blank NO is used. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or +# directories that contain image that are included in the documentation (see +# the \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command , where +# is the value of the INPUT_FILTER tag, and is the name of an +# input file. Doxygen will then use the output that the filter program writes +# to standard output. If FILTER_PATTERNS is specified, this tag will be +# ignored. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. The filters are a list of the form: +# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further +# info on how filters are used. If FILTER_PATTERNS is empty or if +# non of the patterns match the file name, INPUT_FILTER is applied. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will be used to filter the input files when producing source +# files to browse (i.e. when SOURCE_BROWSER is set to YES). + +FILTER_SOURCE_FILES = NO + +# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file +# pattern. A pattern will override the setting for FILTER_PATTERN (if any) +# and it is also possible to disable source filtering for a specific pattern +# using *.ext= (so without naming a filter). This option only has effect when +# FILTER_SOURCE_FILES is enabled. + +FILTER_SOURCE_PATTERNS = + +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will +# be generated. Documented entities will be cross-referenced with these sources. +# Note: To get rid of all source code in the generated output, make sure also +# VERBATIM_HEADERS is set to NO. + +SOURCE_BROWSER = NO + +# Setting the INLINE_SOURCES tag to YES will include the body +# of functions and classes directly in the documentation. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct +# doxygen to hide any special comment blocks from generated source code +# fragments. Normal C and C++ comments will always remain visible. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES +# then for each documented function all documented +# functions referencing it will be listed. + +REFERENCED_BY_RELATION = NO + +# If the REFERENCES_RELATION tag is set to YES +# then for each documented function all documented entities +# called/used by that function will be listed. + +REFERENCES_RELATION = NO + +# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) +# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from +# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will +# link to the source code. Otherwise they will link to the documentation. + +REFERENCES_LINK_SOURCE = YES + +# If the USE_HTAGS tag is set to YES then the references to source code +# will point to the HTML generated by the htags(1) tool instead of doxygen +# built-in source browser. The htags tool is part of GNU's global source +# tagging system (see http://www.gnu.org/software/global/global.html). You +# will need version 4.8.6 or higher. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen +# will generate a verbatim copy of the header file for each class for +# which an include is specified. Set to NO to disable this. + +VERBATIM_HEADERS = YES + +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index +# of all compounds will be generated. Enable this if the project +# contains a lot of classes, structs, unions or interfaces. + +ALPHABETICAL_INDEX = YES + +# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then +# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns +# in which this list will be split (can be a number in the range [1..20]) + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all +# classes will be put under the same header in the alphabetical index. +# The IGNORE_PREFIX tag can be used to specify one or more prefixes that +# should be ignored while generating the index headers. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES (the default) Doxygen will +# generate HTML output. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `html' will be used as the default path. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for +# each generated HTML page (for example: .htm,.php,.asp). If it is left blank +# doxygen will generate files with .html extension. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a personal HTML header for +# each generated HTML page. If it is left blank doxygen will generate a +# standard header. Note that when using a custom header you are responsible +# for the proper inclusion of any scripts and style sheets that doxygen +# needs, which is dependent on the configuration options used. +# It is advised to generate a default header using "doxygen -w html +# header.html footer.html stylesheet.css YourConfigFile" and then modify +# that header. Note that the header is subject to change so you typically +# have to redo this when upgrading to a newer version of doxygen or when +# changing the value of configuration settings such as GENERATE_TREEVIEW! + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a personal HTML footer for +# each generated HTML page. If it is left blank doxygen will generate a +# standard footer. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading +# style sheet that is used by each HTML page. It can be used to +# fine-tune the look of the HTML output. If the tag is left blank doxygen +# will generate a default style sheet. Note that doxygen will try to copy +# the style sheet file to the HTML output directory, so don't put your own +# style sheet in the HTML output directory as well, or it will be erased! + +HTML_STYLESHEET = + +# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or +# other source files which should be copied to the HTML output directory. Note +# that these files will be copied to the base HTML output directory. Use the +# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these +# files. In the HTML_STYLESHEET file, use the file name only. Also note that +# the files will be copied as-is; there are no commands or markers available. + +HTML_EXTRA_FILES = + +# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. +# Doxygen will adjust the colors in the style sheet and background images +# according to this color. Hue is specified as an angle on a colorwheel, +# see http://en.wikipedia.org/wiki/Hue for more information. +# For instance the value 0 represents red, 60 is yellow, 120 is green, +# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. +# The allowed range is 0 to 359. + +HTML_COLORSTYLE_HUE = 220 + +# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of +# the colors in the HTML output. For a value of 0 the output will use +# grayscales only. A value of 255 will produce the most vivid colors. + +HTML_COLORSTYLE_SAT = 100 + +# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to +# the luminance component of the colors in the HTML output. Values below +# 100 gradually make the output lighter, whereas values above 100 make +# the output darker. The value divided by 100 is the actual gamma applied, +# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, +# and 100 does not change the gamma. + +HTML_COLORSTYLE_GAMMA = 80 + +# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML +# page will contain the date and time when the page was generated. Setting +# this to NO can help when comparing the output of multiple runs. + +HTML_TIMESTAMP = YES + +# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, +# files or namespaces will be aligned in HTML using tables. If set to +# NO a bullet list will be used. + +HTML_ALIGN_MEMBERS = YES + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. For this to work a browser that supports +# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox +# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). + +HTML_DYNAMIC_SECTIONS = NO + +# If the GENERATE_DOCSET tag is set to YES, additional index files +# will be generated that can be used as input for Apple's Xcode 3 +# integrated development environment, introduced with OSX 10.5 (Leopard). +# To create a documentation set, doxygen will generate a Makefile in the +# HTML output directory. Running make will produce the docset in that +# directory and running "make install" will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find +# it at startup. +# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html +# for more information. + +GENERATE_DOCSET = NO + +# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the +# feed. A documentation feed provides an umbrella under which multiple +# documentation sets from a single provider (such as a company or product suite) +# can be grouped. + +DOCSET_FEEDNAME = "Doxygen generated docs" + +# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that +# should uniquely identify the documentation set bundle. This should be a +# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen +# will append .docset to the name. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify +# the documentation publisher. This should be a reverse domain-name style +# string, e.g. com.mycompany.MyDocSet.documentation. + +DOCSET_PUBLISHER_ID = org.doxygen.Publisher + +# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. + +DOCSET_PUBLISHER_NAME = Publisher + +# If the GENERATE_HTMLHELP tag is set to YES, additional index files +# will be generated that can be used as input for tools like the +# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) +# of the generated HTML documentation. + +GENERATE_HTMLHELP = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can +# be used to specify the file name of the resulting .chm file. You +# can add a path in front of the file if the result should not be +# written to the html output directory. + +CHM_FILE = + +# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can +# be used to specify the location (absolute path including file name) of +# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run +# the HTML help compiler on the generated index.hhp. + +HHC_LOCATION = + +# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag +# controls if a separate .chi index file is generated (YES) or that +# it should be included in the master .chm file (NO). + +GENERATE_CHI = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING +# is used to encode HtmlHelp index (hhk), content (hhc) and project file +# content. + +CHM_INDEX_ENCODING = + +# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag +# controls whether a binary table of contents is generated (YES) or a +# normal table of contents (NO) in the .chm file. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members +# to the contents of the HTML help documentation and to the tree view. + +TOC_EXPAND = NO + +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and +# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated +# that can be used as input for Qt's qhelpgenerator to generate a +# Qt Compressed Help (.qch) of the generated HTML documentation. + +GENERATE_QHP = NO + +# If the QHG_LOCATION tag is specified, the QCH_FILE tag can +# be used to specify the file name of the resulting .qch file. +# The path specified is relative to the HTML output folder. + +QCH_FILE = + +# The QHP_NAMESPACE tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#namespace + +QHP_NAMESPACE = org.doxygen.Project + +# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#virtual-folders + +QHP_VIRTUAL_FOLDER = doc + +# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to +# add. For more information please see +# http://doc.trolltech.com/qthelpproject.html#custom-filters + +QHP_CUST_FILTER_NAME = + +# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the +# custom filter to add. For more information please see +# +# Qt Help Project / Custom Filters. + +QHP_CUST_FILTER_ATTRS = + +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this +# project's +# filter section matches. +# +# Qt Help Project / Filter Attributes. + +QHP_SECT_FILTER_ATTRS = + +# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can +# be used to specify the location of Qt's qhelpgenerator. +# If non-empty doxygen will try to run qhelpgenerator on the generated +# .qhp file. + +QHG_LOCATION = + +# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files +# will be generated, which together with the HTML files, form an Eclipse help +# plugin. To install this plugin and make it available under the help contents +# menu in Eclipse, the contents of the directory containing the HTML and XML +# files needs to be copied into the plugins directory of eclipse. The name of +# the directory within the plugins directory should be the same as +# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before +# the help appears. + +GENERATE_ECLIPSEHELP = NO + +# A unique identifier for the eclipse help plugin. When installing the plugin +# the directory name containing the HTML and XML files should also have +# this name. + +ECLIPSE_DOC_ID = org.doxygen.Project + +# The DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) +# at top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. Since the tabs have the same information as the +# navigation tree you can set this option to NO if you already set +# GENERATE_TREEVIEW to YES. + +DISABLE_INDEX = NO + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. +# If the tag value is set to YES, a side panel will be generated +# containing a tree-like index structure (just like the one that +# is generated for HTML Help). For this to work a browser that supports +# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). +# Windows users are probably better off using the HTML help feature. +# Since the tree basically has the same information as the tab index you +# could consider to set DISABLE_INDEX to NO when enabling this option. + +GENERATE_TREEVIEW = YES + +# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values +# (range [0,1..20]) that doxygen will group on one line in the generated HTML +# documentation. Note that a value of 0 will completely suppress the enum +# values from appearing in the overview section. + +ENUM_VALUES_PER_LINE = 4 + +# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, +# and Class Hierarchy pages using a tree view instead of an ordered list. + +USE_INLINE_TREES = NO + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be +# used to set the initial width (in pixels) of the frame in which the tree +# is shown. + +TREEVIEW_WIDTH = 250 + +# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open +# links to external symbols imported via tag files in a separate window. + +EXT_LINKS_IN_WINDOW = NO + +# Use this tag to change the font size of Latex formulas included +# as images in the HTML documentation. The default is 10. Note that +# when you change the font size after a successful doxygen run you need +# to manually remove any form_*.png images from the HTML output directory +# to force them to be regenerated. + +FORMULA_FONTSIZE = 10 + +# Use the FORMULA_TRANPARENT tag to determine whether or not the images +# generated for formulas are transparent PNGs. Transparent PNGs are +# not supported properly for IE 6.0, but are supported on all modern browsers. +# Note that when changing this option you need to delete any form_*.png files +# in the HTML output before the changes have effect. + +FORMULA_TRANSPARENT = YES + +# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax +# (see http://www.mathjax.org) which uses client side Javascript for the +# rendering instead of using prerendered bitmaps. Use this if you do not +# have LaTeX installed or if you want to formulas look prettier in the HTML +# output. When enabled you also need to install MathJax separately and +# configure the path to it using the MATHJAX_RELPATH option. + +USE_MATHJAX = NO + +# When MathJax is enabled you need to specify the location relative to the +# HTML output directory using the MATHJAX_RELPATH option. The destination +# directory should contain the MathJax.js script. For instance, if the mathjax +# directory is located at the same level as the HTML output directory, then +# MATHJAX_RELPATH should be ../mathjax. The default value points to the +# mathjax.org site, so you can quickly see the result without installing +# MathJax, but it is strongly recommended to install a local copy of MathJax +# before deployment. + +MATHJAX_RELPATH = http://www.mathjax.org/mathjax + +# The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension +# names that should be enabled during MathJax rendering. + +MATHJAX_EXTENSIONS = + +# When the SEARCHENGINE tag is enabled doxygen will generate a search box +# for the HTML output. The underlying search engine uses javascript +# and DHTML and should work on any modern browser. Note that when using +# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets +# (GENERATE_DOCSET) there is already a search function so this one should +# typically be disabled. For large projects the javascript based search engine +# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. + +SEARCHENGINE = NO + +# When the SERVER_BASED_SEARCH tag is enabled the search engine will be +# implemented using a PHP enabled web server instead of at the web client +# using Javascript. Doxygen will generate the search PHP script and index +# file to put on the web server. The advantage of the server +# based approach is that it scales better to large projects and allows +# full text search. The disadvantages are that it is more difficult to setup +# and does not have live searching capabilities. + +SERVER_BASED_SEARCH = NO + +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- + +# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will +# generate Latex output. + +GENERATE_LATEX = NO + +# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `latex' will be used as the default path. + +LATEX_OUTPUT = latex + +# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be +# invoked. If left blank `latex' will be used as the default command name. +# Note that when enabling USE_PDFLATEX this option is only used for +# generating bitmaps for formulas in the HTML output, but not in the +# Makefile that is written to the output directory. + +LATEX_CMD_NAME = latex + +# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to +# generate index for LaTeX. If left blank `makeindex' will be used as the +# default command name. + +MAKEINDEX_CMD_NAME = makeindex + +# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact +# LaTeX documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_LATEX = NO + +# The PAPER_TYPE tag can be used to set the paper type that is used +# by the printer. Possible values are: a4, letter, legal and +# executive. If left blank a4wide will be used. + +PAPER_TYPE = a4 + +# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX +# packages that should be included in the LaTeX output. + +EXTRA_PACKAGES = + +# The LATEX_HEADER tag can be used to specify a personal LaTeX header for +# the generated latex document. The header should contain everything until +# the first chapter. If it is left blank doxygen will generate a +# standard header. Notice: only use this tag if you know what you are doing! + +LATEX_HEADER = + +# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for +# the generated latex document. The footer should contain everything after +# the last chapter. If it is left blank doxygen will generate a +# standard footer. Notice: only use this tag if you know what you are doing! + +LATEX_FOOTER = + +# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated +# is prepared for conversion to pdf (using ps2pdf). The pdf file will +# contain links (just like the HTML output) instead of page references +# This makes the output suitable for online browsing using a pdf viewer. + +PDF_HYPERLINKS = YES + +# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of +# plain latex in the generated Makefile. Set this option to YES to get a +# higher quality PDF documentation. + +USE_PDFLATEX = YES + +# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. +# command to the generated LaTeX files. This will instruct LaTeX to keep +# running if errors occur, instead of asking the user for help. +# This option is also used when generating formulas in HTML. + +LATEX_BATCHMODE = NO + +# If LATEX_HIDE_INDICES is set to YES then doxygen will not +# include the index chapters (such as File Index, Compound Index, etc.) +# in the output. + +LATEX_HIDE_INDICES = NO + +# If LATEX_SOURCE_CODE is set to YES then doxygen will include +# source code with syntax highlighting in the LaTeX output. +# Note that which sources are shown also depends on other settings +# such as SOURCE_BROWSER. + +LATEX_SOURCE_CODE = NO + +# The LATEX_BIB_STYLE tag can be used to specify the style to use for the +# bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See +# http://en.wikipedia.org/wiki/BibTeX for more info. + +LATEX_BIB_STYLE = plain + +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- + +# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output +# The RTF output is optimized for Word 97 and may not look very pretty with +# other RTF readers or editors. + +GENERATE_RTF = NO + +# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `rtf' will be used as the default path. + +RTF_OUTPUT = rtf + +# If the COMPACT_RTF tag is set to YES Doxygen generates more compact +# RTF documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_RTF = NO + +# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated +# will contain hyperlink fields. The RTF file will +# contain links (just like the HTML output) instead of page references. +# This makes the output suitable for online browsing using WORD or other +# programs which support those fields. +# Note: wordpad (write) and others do not support links. + +RTF_HYPERLINKS = NO + +# Load style sheet definitions from file. Syntax is similar to doxygen's +# config file, i.e. a series of assignments. You only have to provide +# replacements, missing definitions are set to their default value. + +RTF_STYLESHEET_FILE = + +# Set optional variables used in the generation of an rtf document. +# Syntax is similar to doxygen's config file. + +RTF_EXTENSIONS_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- + +# If the GENERATE_MAN tag is set to YES (the default) Doxygen will +# generate man pages + +GENERATE_MAN = NO + +# The MAN_OUTPUT tag is used to specify where the man pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `man' will be used as the default path. + +MAN_OUTPUT = man + +# The MAN_EXTENSION tag determines the extension that is added to +# the generated man pages (default is the subroutine's section .3) + +MAN_EXTENSION = .3 + +# If the MAN_LINKS tag is set to YES and Doxygen generates man output, +# then it will generate one additional man file for each entity +# documented in the real man page(s). These additional files +# only source the real man page, but without them the man command +# would be unable to find the correct page. The default is NO. + +MAN_LINKS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- + +# If the GENERATE_XML tag is set to YES Doxygen will +# generate an XML file that captures the structure of +# the code including all documentation. + +GENERATE_XML = NO + +# The XML_OUTPUT tag is used to specify where the XML pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `xml' will be used as the default path. + +XML_OUTPUT = xml + +# The XML_SCHEMA tag can be used to specify an XML schema, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_SCHEMA = + +# The XML_DTD tag can be used to specify an XML DTD, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_DTD = + +# If the XML_PROGRAMLISTING tag is set to YES Doxygen will +# dump the program listings (including syntax highlighting +# and cross-referencing information) to the XML output. Note that +# enabling this will significantly increase the size of the XML output. + +XML_PROGRAMLISTING = YES + +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- + +# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will +# generate an AutoGen Definitions (see autogen.sf.net) file +# that captures the structure of the code including all +# documentation. Note that this feature is still experimental +# and incomplete at the moment. + +GENERATE_AUTOGEN_DEF = NO + +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- + +# If the GENERATE_PERLMOD tag is set to YES Doxygen will +# generate a Perl module file that captures the structure of +# the code including all documentation. Note that this +# feature is still experimental and incomplete at the +# moment. + +GENERATE_PERLMOD = NO + +# If the PERLMOD_LATEX tag is set to YES Doxygen will generate +# the necessary Makefile rules, Perl scripts and LaTeX code to be able +# to generate PDF and DVI output from the Perl module output. + +PERLMOD_LATEX = NO + +# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be +# nicely formatted so it can be parsed by a human reader. This is useful +# if you want to understand what is going on. On the other hand, if this +# tag is set to NO the size of the Perl module output will be much smaller +# and Perl will parse it just the same. + +PERLMOD_PRETTY = YES + +# The names of the make variables in the generated doxyrules.make file +# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. +# This is useful so different doxyrules.make files included by the same +# Makefile don't overwrite each other's variables. + +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- + +# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will +# evaluate all C-preprocessor directives found in the sources and include +# files. + +ENABLE_PREPROCESSING = YES + +# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro +# names in the source code. If set to NO (the default) only conditional +# compilation will be performed. Macro expansion can be done in a controlled +# way by setting EXPAND_ONLY_PREDEF to YES. + +MACRO_EXPANSION = NO + +# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES +# then the macro expansion is limited to the macros specified with the +# PREDEFINED and EXPAND_AS_DEFINED tags. + +EXPAND_ONLY_PREDEF = NO + +# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files +# pointed to by INCLUDE_PATH will be searched when a #include is found. + +SEARCH_INCLUDES = YES + +# The INCLUDE_PATH tag can be used to specify one or more directories that +# contain include files that are not input files but should be processed by +# the preprocessor. + +INCLUDE_PATH = + +# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard +# patterns (like *.h and *.hpp) to filter out the header-files in the +# directories. If left blank, the patterns specified with FILE_PATTERNS will +# be used. + +INCLUDE_FILE_PATTERNS = + +# The PREDEFINED tag can be used to specify one or more macro names that +# are defined before the preprocessor is started (similar to the -D option of +# gcc). The argument of the tag is a list of macros of the form: name +# or name=definition (no spaces). If the definition and the = are +# omitted =1 is assumed. To prevent a macro definition from being +# undefined via #undef or recursively expanded use the := operator +# instead of the = operator. + +PREDEFINED = + +# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then +# this tag can be used to specify a list of macro names that should be expanded. +# The macro definition that is found in the sources will be used. +# Use the PREDEFINED tag if you want to use a different macro definition that +# overrules the definition found in the source code. + +EXPAND_AS_DEFINED = + +# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then +# doxygen's preprocessor will remove all references to function-like macros +# that are alone on a line, have an all uppercase name, and do not end with a +# semicolon, because these will confuse the parser if not removed. + +SKIP_FUNCTION_MACROS = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- + +# The TAGFILES option can be used to specify one or more tagfiles. +# Optionally an initial location of the external documentation +# can be added for each tagfile. The format of a tag file without +# this location is as follows: +# TAGFILES = file1 file2 ... +# Adding location for the tag files is done as follows: +# TAGFILES = file1=loc1 "file2 = loc2" ... +# where "loc1" and "loc2" can be relative or absolute paths or +# URLs. If a location is present for each tag, the installdox tool +# does not have to be run to correct the links. +# Note that each tag file must have a unique name +# (where the name does NOT include the path) +# If a tag file is not located in the directory in which doxygen +# is run, you must also specify the path to the tagfile here. + +TAGFILES = + +# When a file name is specified after GENERATE_TAGFILE, doxygen will create +# a tag file that is based on the input files it reads. + +GENERATE_TAGFILE = + +# If the ALLEXTERNALS tag is set to YES all external classes will be listed +# in the class index. If set to NO only the inherited external classes +# will be listed. + +ALLEXTERNALS = NO + +# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed +# in the modules index. If set to NO, only the current project's groups will +# be listed. + +EXTERNAL_GROUPS = YES + +# The PERL_PATH should be the absolute path and name of the perl script +# interpreter (i.e. the result of `which perl'). + +PERL_PATH = /usr/bin/perl + +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- + +# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will +# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base +# or super classes. Setting the tag to NO turns the diagrams off. Note that +# this option also works with HAVE_DOT disabled, but it is recommended to +# install and use dot, since it yields more powerful graphs. + +CLASS_DIAGRAMS = YES + +# You can define message sequence charts within doxygen comments using the \msc +# command. Doxygen will then run the mscgen tool (see +# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the +# documentation. The MSCGEN_PATH tag allows you to specify the directory where +# the mscgen tool resides. If left empty the tool is assumed to be found in the +# default search path. + +MSCGEN_PATH = + +# If set to YES, the inheritance and collaboration graphs will hide +# inheritance and usage relations if the target is undocumented +# or is not a class. + +HIDE_UNDOC_RELATIONS = YES + +# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is +# available from the path. This tool is part of Graphviz, a graph visualization +# toolkit from AT&T and Lucent Bell Labs. The other options in this section +# have no effect if this option is set to NO (the default) + +HAVE_DOT = NO + +# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is +# allowed to run in parallel. When set to 0 (the default) doxygen will +# base this on the number of processors available in the system. You can set it +# explicitly to a value larger than 0 to get control over the balance +# between CPU load and processing speed. + +DOT_NUM_THREADS = 0 + +# By default doxygen will use the Helvetica font for all dot files that +# doxygen generates. When you want a differently looking font you can specify +# the font name using DOT_FONTNAME. You need to make sure dot is able to find +# the font, which can be done by putting it in a standard location or by setting +# the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the +# directory containing the font. + +DOT_FONTNAME = Helvetica + +# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. +# The default size is 10pt. + +DOT_FONTSIZE = 10 + +# By default doxygen will tell dot to use the Helvetica font. +# If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to +# set the path where dot can find it. + +DOT_FONTPATH = + +# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect inheritance relations. Setting this tag to YES will force the +# CLASS_DIAGRAMS tag to NO. + +CLASS_GRAPH = YES + +# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect implementation dependencies (inheritance, containment, and +# class references variables) of the class with other documented classes. + +COLLABORATION_GRAPH = YES + +# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for groups, showing the direct groups dependencies + +GROUP_GRAPHS = YES + +# If the UML_LOOK tag is set to YES doxygen will generate inheritance and +# collaboration diagrams in a style similar to the OMG's Unified Modeling +# Language. + +UML_LOOK = NO + +# If set to YES, the inheritance and collaboration graphs will show the +# relations between templates and their instances. + +TEMPLATE_RELATIONS = NO + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT +# tags are set to YES then doxygen will generate a graph for each documented +# file showing the direct and indirect include dependencies of the file with +# other documented files. + +INCLUDE_GRAPH = YES + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and +# HAVE_DOT tags are set to YES then doxygen will generate a graph for each +# documented header file showing the documented files that directly or +# indirectly include this file. + +INCLUDED_BY_GRAPH = YES + +# If the CALL_GRAPH and HAVE_DOT options are set to YES then +# doxygen will generate a call dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable call graphs +# for selected functions only using the \callgraph command. + +CALL_GRAPH = NO + +# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then +# doxygen will generate a caller dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable caller +# graphs for selected functions only using the \callergraph command. + +CALLER_GRAPH = NO + +# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen +# will generate a graphical hierarchy of all classes instead of a textual one. + +GRAPHICAL_HIERARCHY = YES + +# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES +# then doxygen will show the dependencies a directory has on other directories +# in a graphical way. The dependency relations are determined by the #include +# relations between the files in the directories. + +DIRECTORY_GRAPH = YES + +# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images +# generated by dot. Possible values are svg, png, jpg, or gif. +# If left blank png will be used. If you choose svg you need to set +# HTML_FILE_EXTENSION to xhtml in order to make the SVG files +# visible in IE 9+ (other browsers do not have this requirement). + +DOT_IMAGE_FORMAT = png + +# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to +# enable generation of interactive SVG images that allow zooming and panning. +# Note that this requires a modern browser other than Internet Explorer. +# Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you +# need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files +# visible. Older versions of IE do not have SVG support. + +INTERACTIVE_SVG = NO + +# The tag DOT_PATH can be used to specify the path where the dot tool can be +# found. If left blank, it is assumed the dot tool can be found in the path. + +DOT_PATH = + +# The DOTFILE_DIRS tag can be used to specify one or more directories that +# contain dot files that are included in the documentation (see the +# \dotfile command). + +DOTFILE_DIRS = + +# The MSCFILE_DIRS tag can be used to specify one or more directories that +# contain msc files that are included in the documentation (see the +# \mscfile command). + +MSCFILE_DIRS = + +# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of +# nodes that will be shown in the graph. If the number of nodes in a graph +# becomes larger than this value, doxygen will truncate the graph, which is +# visualized by representing a node as a red box. Note that doxygen if the +# number of direct children of the root node in a graph is already larger than +# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note +# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. + +DOT_GRAPH_MAX_NODES = 50 + +# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the +# graphs generated by dot. A depth value of 3 means that only nodes reachable +# from the root by following a path via at most 3 edges will be shown. Nodes +# that lay further from the root node will be omitted. Note that setting this +# option to 1 or 2 may greatly reduce the computation time needed for large +# code bases. Also note that the size of a graph can be further restricted by +# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. + +MAX_DOT_GRAPH_DEPTH = 0 + +# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent +# background. This is disabled by default, because dot on Windows does not +# seem to support this out of the box. Warning: Depending on the platform used, +# enabling this option may lead to badly anti-aliased labels on the edges of +# a graph (i.e. they become hard to read). + +DOT_TRANSPARENT = NO + +# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output +# files in one run (i.e. multiple -o and -T options on the command line). This +# makes dot run faster, but since only newer versions of dot (>1.8.10) +# support this, this feature is disabled by default. + +DOT_MULTI_TARGETS = NO + +# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will +# generate a legend page explaining the meaning of the various boxes and +# arrows in the dot generated graphs. + +GENERATE_LEGEND = YES + +# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will +# remove the intermediate dot files that are used to generate +# the various graphs. + +DOT_CLEANUP = YES -- cgit v1.2.3