University of Pennsylvania

The following state diagram (Fig. 1) describes a finite state machine with one input X and one output Z. The FSM asserts its output Z when it recognizes the following input bit sequence: "1011". The machine will keep checking for the proper bit sequence and does not reset to the initial state after it has recognized the string. As an example the input string X= "..1011011..." will cause the output to go high twice: Z = "..0001001.." . The output will asserts only when it is in state S4 (after having seen the sequence 1011). The FSM is thus a Moore machine.

Figure 1: State diagram, describing the sequence detector implemented as a Moore machine. The number in italics underneath the states indicate which part of the sequence the state remembers.

This state diagram can be described in ABEL code given in Listing 1. The output is described after the STATE Si: statement.

Listing 1: ABEL source code for the Moore machine implementation of the sequence detector described in Fig. 1

module Seqdet2
Title 'Sequence detector implemented as Moore machine'
Declarations
"input and output signals

X, CLOCK, RST PIN;
Z PIN istype 'com';
Q2, Q1, Q0 PIN istype 'reg';

"State register declarations

SREG = [Q2,Q1,Q0];
S0 = [0,0,0];
S1 = [0,0,1];
S2 = [0,1,0];
S3 = [0,1,1];
S4 = [1,0,0];


Equations
"Definition of the state machine clock signal

[Q2,Q1,Q0].AR = RST;
[Q2,Q1,Q0].CLK = CLOCK;


"Define state diagram
STATE_DIAGRAM SREG

STATE S0: Z=0;


IF X THEN S1 ELSE S0;

STATE S1: Z=0;

IF X THEN S1 ELSE S2;

STATE S2: Z=0;

IF X THEN S3 ELSE S0;

STATE S3: Z=0;

IF X THEN S4 ELSE S2;

STATE S4: Z=1;

IF X THEN S1 ELSE S2;

end Seqdet2

The corresponding simulation is shown in Figure 2.

One notices that the output asserts after the input sequence 1011 as specified.