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| author | Sven Eisenhauer <sven@sven-eisenhauer.net> | 2023-11-10 15:11:48 +0100 |
|---|---|---|
| committer | Sven Eisenhauer <sven@sven-eisenhauer.net> | 2023-11-10 15:11:48 +0100 |
| commit | 33613a85afc4b1481367fbe92a17ee59c240250b (patch) | |
| tree | 670b842326116b376b505ec2263878912fca97e2 /Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON2.S | |
| download | Studium-33613a85afc4b1481367fbe92a17ee59c240250b.tar.gz Studium-33613a85afc4b1481367fbe92a17ee59c240250b.tar.bz2 | |
Diffstat (limited to 'Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON2.S')
| -rw-r--r-- | Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON2.S | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON2.S b/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON2.S new file mode 100644 index 0000000..53deb76 --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON2.S @@ -0,0 +1,26 @@ + AREA Loadcon2, CODE
+ ENTRY ; Mark first instruction
+ BL func1 ; Branch to first subroutine
+ BL func2 ; Branch to second subroutine
+ SWI 0x11 ; Terminate
+func1
+ LDR r0, =42 ; => MOV R0, #42
+ LDR r1, =0x55555555 ; => LDR R1, [PC, #offset to Literal
+ ; Pool 1]
+ LDR r2, =0xFFFFFFFF ; => MVN R2, #0
+ MOV pc, lr
+
+ LTORG ; Literal Pool 1 contains
+ ; literal &55555555
+func2
+ LDR r3, =0x55555555 ; => LDR R3, [PC, #offset to Literal
+ ; Pool 1]
+ ; LDR r4, =0x66666666 ; If this is uncommented it will
+ ; fail, as Literal Pool 2 is not
+ ; accessible (out of reach)
+ MOV pc, lr
+
+LargeTable % 4200 ; Clears a 4200 byte area of memory,
+ ; starting at the current location,
+ ; to zero.
+ END ;Literal Pool 2 is empty
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