add new repoHEADmaster

14 files changed, 1195 insertions, 0 deletions

diff --git a/Bachelor/Mikroprozessorsysteme2/mi2/h/Termin2Aufgabe2.c b/Bachelor/Mikroprozessorsysteme2/mi2/h/Termin2Aufgabe2.c
new file mode 100644
index 0000000..24171af
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/mi2/h/Termin2Aufgabe2.c
@@ -0,0 +1,35 @@
+// Lösung zu Termin2
+// Aufgabe 1
+// von: Manfred Pester
+// vom: 27.07.2003
+// 
+
+#define PIOB_PER		((volatile unsigned int *) 0xFFFF0000)
+#define PIOB_OER		((volatile unsigned int *) 0xFFFF0010)
+#define PIOB_SODR 	((volatile unsigned int *) 0xFFFF0030)
+#define PIOB_CODR 	((volatile unsigned int *) 0xFFFF0034)
+
+#define PMC_SCER		((volatile unsigned int *) 0xFFFF4000)
+#define PMC_SCDR		((volatile unsigned int *) 0xFFFF4004)
+#define PMC_SCSR		((volatile unsigned int *) 0xFFFF4008)
+#define PMC_PCER		((volatile unsigned int *) 0xFFFF4010)
+#define PMC_PCDR		((volatile unsigned int *) 0xFFFF4014)
+#define PMC_PCSR		((volatile unsigned int *) 0xFFFF4018)
+
+
+int main(void)
+{
+
+	*PMC_PCER		= 0x4000;	// Peripheral Clock für PIOB einschalten
+			
+	*PIOB_PER		= 0x0100;	// Enable Register 8 LED's und Taster an PB3
+	*PIOB_OER		= 0x0100;	// Output Enable Register 8 LED's sind aus
+	
+	while(1)
+	{
+		*PIOB_SODR 	= 0x0100;	// Set Output Data Register LED's sind aus
+		*PIOB_CODR 	= 0x0100;	// Clear Output Data Register LED's leuchten
+	}
+	
+	return 0;
+}
diff --git a/Bachelor/Mikroprozessorsysteme2/mi2/h/Termin2Aufgabe2.h b/Bachelor/Mikroprozessorsysteme2/mi2/h/Termin2Aufgabe2.h
new file mode 100644
index 0000000..670a0a9
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/mi2/h/Termin2Aufgabe2.h
@@ -0,0 +1,38 @@
+// Headerfile für Termin2
+
+#ifndef Termin2
+#define Termin2
+
+// Register von PIOB
+#define PIOB_PER		((volatile unsigned int *) 0xFFFF0000)
+#define PIOB_OER		((volatile unsigned int *) 0xFFFF0010)
+#define PIOB_SODR 	((volatile unsigned int *) 0xFFFF0030)
+#define PIOB_CODR 	((volatile unsigned int *) 0xFFFF0034)
+#define PIOB_PDSR		((volatile unsigned int *) 0xFFFF003C)
+
+// Leuchtdioden des AT91EB63
+#define LED1	0x0100		// PIOB8
+#define LED2	0x0200		// PIOB9
+#define LED3	0x0400		// PIOB10
+#define LED4	0x0800		// PIOB11
+#define LED5	0x1000		// PIOB12
+#define LED6	0x2000		// PIOB13
+#define LED7	0x4000		// PIOB14
+#define LED8	0x8000		// PIOB15
+// Taster SW1-3 an PIOB des AT91EB63
+#define SW1		0x08		// PIOB3
+#define SW2		0x10		// PIOB4
+#define SW3		0x20		// PIOB5
+// Taster SW4 an PIOA des AT91EB63
+#define SW4		0x200		// PIOA9	
+
+
+// Register vom PMC
+#define PMC_SCER		((volatile unsigned int *) 0xFFFF4000)
+#define PMC_SCDR		((volatile unsigned int *) 0xFFFF4004)
+#define PMC_SCSR		((volatile unsigned int *) 0xFFFF4008)
+#define PMC_PCER		((volatile unsigned int *) 0xFFFF4010)
+#define PMC_PCDR		((volatile unsigned int *) 0xFFFF4014)
+#define PMC_PCSR		((volatile unsigned int *) 0xFFFF4018)
+
+#endif // Termin2
diff --git a/Bachelor/Mikroprozessorsysteme2/mi2/h/aic.h b/Bachelor/Mikroprozessorsysteme2/mi2/h/aic.h
new file mode 100644
index 0000000..8a5d2bd
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/mi2/h/aic.h
@@ -0,0 +1,99 @@
+//----------------------------------------------------------------------------
+// File Name           : aic.h
+// Object              : Advanced Interrupt Controller Definition File.
+//
+// 1.0 27/10/02 GR     : Creation
+//----------------------------------------------------------------------------
+
+#ifndef aic_h
+#define aic_h
+
+#include    "std_c.h"
+
+/*-----------------------------------------*/
+/* AIC User Interface Structure Definition */
+/*-----------------------------------------*/
+
+typedef struct
+{
+    at91_reg        AIC_SMR[32] ;       /* Source Mode Register */
+    at91_reg        AIC_SVR[32] ;       /* Source Vector Register */
+    at91_reg        AIC_IVR ;           /* IRQ Vector Register */
+    at91_reg        AIC_FVR ;           /* FIQ Vector Register */
+    at91_reg        AIC_ISR ;           /* Interrupt Status Register */
+    at91_reg        AIC_IPR ;           /* Interrupt Pending Register */
+    at91_reg        AIC_IMR ;           /* Interrupt Mask Register */
+    at91_reg        AIC_CISR ;          /* Core Interrupt Status Register */
+    at91_reg        reserved0 ;
+    at91_reg        reserved1 ;
+    at91_reg        AIC_IECR ;          /* Interrupt Enable Command Register */
+    at91_reg        AIC_IDCR ;          /* Interrupt Disable Command Register */
+    at91_reg        AIC_ICCR ;          /* Interrupt Clear Command Register */
+    at91_reg        AIC_ISCR ;          /* Interrupt Set Command Register */
+    at91_reg        AIC_EOICR ;         /* End of Interrupt Command Register */
+    at91_reg        AIC_SPU ;           /* Spurious Vector Register */
+} StructAIC ;
+
+/*--------------------------------------------*/
+/* AIC_SMR[]: Interrupt Source Mode Registers */
+/*--------------------------------------------*/
+
+#define AIC_PRIOR                       0x07    /* Priority */
+
+#define AIC_SRCTYPE                     0x60    /* Source Type Definition */
+
+/* Internal Interrupts */
+#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00    /* Level Sensitive */
+#define AIC_SRCTYPE_INT_EDGE_TRIGGERED  0x20    /* Edge Triggered */
+
+/* External Interrupts */
+#define AIC_SRCTYPE_EXT_LOW_LEVEL       0x00    /* Low Level */
+#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE   0x20    /* Negative Edge */
+#define AIC_SRCTYPE_EXT_HIGH_LEVEL      0x40    /* High Level */
+#define AIC_SRCTYPE_EXT_POSITIVE_EDGE   0x60    /* Positive Edge */
+
+/*------------------------------------*/
+/* AIC_ISR: Interrupt Status Register */
+/*------------------------------------*/
+
+#define AIC_IRQID                       0x1F    /* Current source interrupt */
+
+/*------------------------------------------*/
+/* AIC_CISR: Interrupt Core Status Register */
+/*------------------------------------------*/
+
+#define AIC_NFIQ                        0x01    /* Core FIQ Status */
+#define AIC_NIRQ                        0x02    /* Core IRQ Status */
+
+/*-------------------------------------*/
+/* Peripheral and Interrupt Identifier */
+/*-------------------------------------*/
+
+#define FIQ_ID      0       /* Fast Interrupt */
+#define SWIRQ_ID    1       /* Soft Interrupt (generated by the AIC) */
+#define US0_ID      2       /* USART Channel 0 */
+#define US1_ID      3       /* USART Channel 1 */
+#define US2_ID      4       /* USART Channel 2 */
+#define SPI_ID      5       /* SPI */
+#define TC0_ID      6       /* Timer Channel 0 */
+#define TC1_ID      7       /* Timer Channel 1 */
+#define TC2_ID      8       /* Timer Channel 2 */
+#define TC3_ID      9       /* Timer Channel 3 */
+#define TC4_ID      10      /* Timer Channel 4 */
+#define TC5_ID      11      /* Timer Channel 5 */
+#define WD_ID       12      /* Watchdog */
+#define PIOA_ID     13      /* Parallel I/O Controller A */
+#define PIOB_ID     14      /* Parallel I/O Controller B */
+
+#define IRQ3_ID     28      /* External interrupt 3 */
+#define IRQ2_ID     29      /* External interrupt 2 */
+#define IRQ1_ID     30      /* External interrupt 1 */
+#define IRQ0_ID     31      /* External interrupt 0 */
+
+/*-------------------------------*/
+/* Advanced Interrupt Controller */
+/*-------------------------------*/
+
+#define AIC_BASE                        ((StructAIC *)0xFFFFF000)
+
+#endif /* aic_h */
diff --git a/Bachelor/Mikroprozessorsysteme2/mi2/h/aic.inc b/Bachelor/Mikroprozessorsysteme2/mi2/h/aic.inc
new file mode 100644
index 0000000..6638c20
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/mi2/h/aic.inc
@@ -0,0 +1,66 @@
+@----------------------------------------------------------------------------
+@ File Name           : aic.inc
+@ Object              : Advanced Interrupt Controller Header File.
+@
+@ 1.0 27/20/02 GR    : Creation
+@----------------------------------------------------------------------------
+
+#ifndef pmc_inc
+#define pmc_inc
+
+@------------------------------------------
+@- AIC User Interface Structure Definition
+@------------------------------------------
+
+AIC_SMR             =       0		@- Source Mode Register
+AIC_SVR             =       0x80        @- Source Vector Register
+AIC_IVR             =       0x100       @- IRQ Vector Register
+AIC_FVR             =       0x104	@- FIQ Vector Register
+AIC_ISR             =       0x108       @- Interrupt Status Register
+AIC_IPR             =       0x10c       @- Interrupt Pending Register
+AIC_IMR             =       0x110       @- Interrupt Mask Register
+AIC_CISR            =       0x114       @- Core Interrupt Status Register
+@                   =       0x118       @- Reserved 0
+@                   =       0x11c       @- Reserved 1
+AIC_IECR            =       0x120       @- Interrupt Enable Command Register
+AIC_IDCR            =       0x124       @- Interrupt Disable Command Register
+AIC_ICCR            =       0x128       @- Interrupt Clear Command Register
+AIC_ISCR            =       0x12c       @- Interrupt Set Command Register
+AIC_EOICR           =       0x130       @-  of Interrupt Command Register
+AIC_SPU             =       0x134       @- Spurious Vector Register
+
+@---------------------------------------------
+@- AIC_SMR[]: Interrupt Source Mode Registers
+@---------------------------------------------
+
+AIC_PRIOR                       =     0x07    @- Priority
+
+AIC_SRCTYPE                     =     0x60    @- Source Type Definition
+AIC_SRCTYPE_INT_LEVEL_SENSITIVE =     0x00    @- Level Sensitive
+AIC_SRCTYPE_INT_EDGE_TRIGGERED  =     0x20    @- Edge Triggered
+AIC_SRCTYPE_EXT_LOW_LEVEL       =     0x00    @- Low Level
+AIC_SRCTYPE_EXT_NEGATIVE_EDGE   =     0x20    @- Negative Edge
+AIC_SRCTYPE_EXT_HIGH_LEVEL      =     0x40    @- High Level
+AIC_SRCTYPE_EXT_POSITIVE_EDGE   =     0x60    @- Positive Edge
+
+@--------------------------------------
+@-  AIC_ISR: Interrupt Status Register
+@--------------------------------------
+
+AIC_IRQID               =     0x1F            @- Current source interrupt
+
+@-------------------------------------------
+@- AIC_CISR: Interrupt Core Status Register
+@-------------------------------------------
+
+AIC_NFIQ                =     0x01            @- Core FIQ Status
+AIC_NIRQ                =     0x02            @- Core IRQ Status
+
+@--------------------------------------------
+@- Advanced Interrupt COntroller BAse Address
+@--------------------------------------------
+
+AIC_BASE                =     0xFFFFF000
+
+#endif 
+
diff --git a/Bachelor/Mikroprozessorsysteme2/mi2/h/ebi.inc b/Bachelor/Mikroprozessorsysteme2/mi2/h/ebi.inc
new file mode 100644
index 0000000..d9ac97d
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/mi2/h/ebi.inc
@@ -0,0 +1,36 @@
+@----------------------------------------------------------------------------
+@ File Name           : ebi.inc
+@ Object              : Power Management Controller Header File.
+@
+@ 1.0 27/10/02 GR     : Creation
+@----------------------------------------------------------------------------
+
+#ifndef ebi_inc
+#define ebi_inc
+
+@------------------------------------------------------------------------------
+@- EBI Initialization Data
+@-------------------------
+@- The EBI values depend to target choice , Clock, and memories access time.
+@- Yous must be define these values in include file
+@- The EBI User Interface Image which is copied by the boot.
+@- The EBI_CSR_x are defined in the target and hardware depend.
+@- That's hardware! Details in the Electrical Datasheet of the AT91 device.
+@- EBI Base Address is added at the end for commodity in copy code.
+@- ICE note :For ICE debug no need to set the EBI value these values already set
+@- by the boot function.
+@------------------------------------------------------------------------------
+FLASH_BASE	=	0x1000000
+EXT_SRAM_BASE	=	0x2000000
+EBI_BASE        =     0xFFE00000      @- External Bus Interface
+
+EBI_CSR_0   	=     (FLASH_BASE  |  0x2529)    @ 0x01000000, 16MB, 2 tdf, 16 bits, 2 WS
+EBI_CSR_1   	=     (EXT_SRAM_BASE  |  0x2121) @ 0x02000000, 16MB, 0 hold, 16 bits, 1 WS
+EBI_CSR_2   	=     0x20000000  @ unused
+EBI_CSR_3   	=     0x30000000  @ unused
+EBI_CSR_4   	=     0x40000000  @ unused
+EBI_CSR_5   	=     0x50000000  @ unused
+EBI_CSR_6   	=     0x60000000  @ unused
+EBI_CSR_7   	=     0x70000000  @ unused
+
+#endif 
diff --git a/Bachelor/Mikroprozessorsysteme2/mi2/h/pio.h b/Bachelor/Mikroprozessorsysteme2/mi2/h/pio.h
new file mode 100644
index 0000000..b95084c
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/mi2/h/pio.h
@@ -0,0 +1,123 @@
+//----------------------------------------------------------------------------
+// File Name           : pio.h
+// Object              : Parallel I/O Header File
+//
+//* 1.0 27/10/02 GR     : Creation
+//----------------------------------------------------------------------------
+
+#ifndef pio_h
+#define pio_h
+
+#include    "std_c.h"
+
+/*------------------------------------------------------------*/
+/* User Interface Parallel I/O Interface Structure Definition */
+/*------------------------------------------------------------*/
+
+typedef struct
+{
+  at91_reg        PIO_PER ;           /* PIO Enable Register */
+  at91_reg        PIO_PDR ;           /* PIO Disable Register */
+  at91_reg        PIO_PSR ;           /* PIO Status Register */
+  at91_reg        Reserved0 ;
+  at91_reg        PIO_OER ;           /* Output Enable Register */
+  at91_reg        PIO_ODR ;           /* Output Disable Register */
+  at91_reg        PIO_OSR ;           /* Output Status Register */
+  at91_reg        Reserved1 ;
+  at91_reg        PIO_IFER ;          /* Input Filter Enable Register */
+  at91_reg        PIO_IFDR ;          /* Input Filter Disable Register */
+  at91_reg        PIO_IFSR ;          /* Input Filter Status Register */
+  at91_reg        Reserved2 ;
+  at91_reg        PIO_SODR ;          /* Set Output Data Register */
+  at91_reg        PIO_CODR ;          /* Clear Output Data Register */
+  at91_reg        PIO_ODSR ;          /* Output Data Status Register */
+  at91_reg        PIO_PDSR ;          /* Pin Data Status Register */
+  at91_reg        PIO_IER ;           /* Interrupt Enable Register */
+  at91_reg        PIO_IDR ;           /* Interrupt Disable Register */
+  at91_reg        PIO_IMR ;           /* Interrupt Mask Register */
+  at91_reg        PIO_ISR ;           /* Interrupt Status Register */
+  at91_reg        PIO_MDER ;          /* Multi Driver Enable Register */
+  at91_reg        PIO_MDDR ;          /* Multi Driver Disable Register */
+  at91_reg        PIO_MDSR ;          /* Multi Driver Status Register */
+} StructPIO ;
+
+#define PIOB_BASE       ((StructPIO *) 0xFFFF0000)      /* Parallel I/O Controller B */
+#define PIOA_BASE       ((StructPIO *) 0xFFFEC000)      /* Parallel I/O Controller A */
+
+/* PIO Controller A */
+#define PIOTCLK3        0         /* Timer 3 Clock signal */
+#define PIOTIOA3        1         /* Timer 3 Signal A */
+#define PIOTIOB3        2         /* Timer 3 Signal B */
+                                   
+#define PIOTCLK4        3         /* Timer 4 Clock signal */
+#define PIOTIOA4        4         /* Timer 4 Signal A */
+#define PIOTIOB4        5         /* Timer 4 Signal B */
+                                   
+#define PIOTCLK5        6         /* Timer 5 Clock signal */
+#define PIOTIOA5        7         /* Timer 5 Signal A */
+#define PIOTIOB5        8         /* Timer 5 Signal B */
+                                    
+#define PIOIRQ0         9         /* External Interrupt 0 */
+#define PIOIRQ1         10        /* External Interrupt 1 */
+#define PIOIRQ2         11        /* External Interrupt 2 */
+#define PIOIRQ3         12        /* External Interrupt 3 */
+#define PIOFIQ          13        /* Fast Interrupt */
+                                   
+#define PIOSCK0         14        /* USART 0 signal */
+#define PIOTXD0         15        /* USART 0 transmit data */
+#define PIORXD0         16        /* USART 0 receive data  */
+                                  
+#define PIOSCK1         17        /* USART 1 clock signal  */
+#define PIOTXD1         18        /* USART 1 transmit data */
+#define PIORXD1         19        /* USART 1 receive data  */
+                                   
+#define PIOSCK2         20        /* USART 2 clock signal   */
+#define PIOTXD2         21        /* USART 2 transmit data  */
+#define PIORXD2         22        /* USART 2 receive data   */
+                                   
+#define PIOSPCK         23        /* SPI clock signal */ 
+#define PIOMISO         24        /* SPI Master In Slave */
+#define PIOMOSI         25        /* SPI Master Out Slave */
+#define PIONPCS0        26        /* SPI Peripheral Chip Select 0 */
+#define PIONSS          PIONPCS0    
+#define PIONPCS1        27        /* SPI Peripheral Chip Select 1 */
+#define PIONPCS2        28        /* SPI Peripheral Chip Select 2 */
+#define PIONPCS3        29        /* SPI Peripheral Chip Select 3 */
+
+/* PIO Controller B */
+#define PIOTCLK0        19        /* Timer 0 Clock signal input */
+#define PIOTIOA0        20        /* Timer 0 Signal A   */
+#define PIOTIOB0        21        /* Timer 0 Signal B   */
+                                   
+#define PIOTCLK1        22        /* Timer 1 Clock signal */
+#define PIOTIOA1        23        /* Timer 1 Signal A */
+#define PIOTIOB1        24        /* Timer 1 Signal B */
+                                       
+#define PIOTCLK2        25        /* Timer 2 Clock signal */
+#define PIOTIOA2        26        /* Timer 2 Signal A */
+#define PIOTIOB2        27        /* Timer 2 Signal B */
+                                     
+#define PIOMCKO         17        /* Master Clock Output */
+                                  
+#define PIOBMS          18        /* Boot Mode Select */
+                                  
+#define PIOMPI_NOE      0         /* MPI output enable */
+#define PIOMPI_NLB      1         /* MPI lower byte select */
+#define PIOMPI_NUB      2         /* MPI upper byte select */
+
+#define LED1            (1<<8)         /* LED 1 (linke LED) */
+#define LED2            (1<<9)         /* LED 2 */
+#define LED3           (1<<10)         /* LED 3 */
+#define LED4           (1<<11)         /* LED 4 */
+#define LED5           (1<<12)         /* LED 5 */
+#define LED6           (1<<13)         /* LED 6 */
+#define LED7           (1<<14)         /* LED 7 */
+#define LED8           (1<<15)         /* LED 8 */
+#define ALL_LEDS       (LED1|LED2|LED3|LED4|LED5|LED6|LED7|LED8)
+
+#define KEY1            (1<<3)         /* TASTE 1 (linke Taste) auf PB3 */
+#define KEY2            (1<<4)         /* TASTE 2 auf PB4 */
+#define KEY3            (1<<5)         /* TASTE 3 auf PB5 */
+#define KEY4            (1<<9)         /* TASTE 4 auf PA9/IRQ0 */
+#define ALL_KEYS        (KEY1|KEY2|KEY3)                                            
+#endif /* pio_h */
diff --git a/Bachelor/Mikroprozessorsysteme2/mi2/h/pio.inc b/Bachelor/Mikroprozessorsysteme2/mi2/h/pio.inc
new file mode 100644
index 0000000..e694e7a
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/mi2/h/pio.inc
@@ -0,0 +1,120 @@
+@----------------------------------------------------------------------------
+@ File Name           : pio.inc
+@ Object              : Parallel I/O Header File
+@
+@ 1.0 27/10/02 GR    : Creation
+@----------------------------------------------------------------------------
+
+#ifndef pio_inc
+#define pio_inc
+
+
+@------------------------------------------------------------*/
+@ User Interface Parallel I/O Interface Structure Definition */
+@------------------------------------------------------------*/
+
+PIO_PER = 0x0           @ PIO Enable Register 
+PIO_PDR = 0x4           @ PIO Disable Register 
+PIO_PSR = 0x8           @ PIO Status Register 
+			@ Reserved 0xC
+PIO_OER = 0x10           @ Output Enable Register 
+PIO_ODR = 0x14           @ Output Disable Register 
+PIO_OSR = 0x18           @ Output Status Register 
+			@  Reserved 0x1C
+PIO_IFER = 0x20          @ Input Filter Enable Register 
+PIO_IFDR = 0x24          @ Input Filter Disable Register 
+PIO_IFSR = 0x28          @ Input Filter Status Register 
+			@  Reserved 0x2C
+PIO_SODR = 0x30         @ Set Output Data Register 
+PIO_CODR = 0x34         @ Clear Output Data Register 
+PIO_ODSR = 0x38         @ Output Data Status Register 
+PIO_PDSR = 0x3C         @ Pin Data Status Register 
+PIO_IER = 0x40          @ Interrupt Enable Register 
+PIO_IDR = 0x44          @ Interrupt Disable Register 
+PIO_IMR = 0x48          @ Interrupt Mask Register 
+PIO_ISR = 0x4C          @ Interrupt Status Register 
+PIO_MDER = 0x50         @ Multi Driver Enable Register 
+PIO_MDDR = 0x54         @ Multi Driver Disable Register 
+PIO_MDSR = 0x58          @ Multi Driver Status Register 
+			@  Reserved 0x5C
+
+PIOB_BASE     = 0xFFFF0000     @ Parallel I/O Controller B 
+PIOA_BASE     = 0xFFFEC000      @ Parallel I/O Controller A 
+
+@ PIO Controller A 
+PIOTCLK3   =     0         @ Timer 3 Clock signal 
+PIOTIOA3   =     1         @ Timer 3 Signal A 
+PIOTIOB3   =     2         @ Timer 3 Signal B 
+                                   
+PIOTCLK4   =     3         @ Timer 4 Clock signal 
+PIOTIOA4   =     4         @ Timer 4 Signal A 
+PIOTIOB4   =     5         @ Timer 4 Signal B 
+                                   
+PIOTCLK5   =     6         @ Timer 5 Clock signal 
+PIOTIOA5   =     7         @ Timer 5 Signal A 
+PIOTIOB5   =     8         @ Timer 5 Signal B 
+                                    
+PIOIRQ0    =     9         @ External Interrupt 0 
+PIOIRQ1    =     10        @ External Interrupt 1 
+PIOIRQ2    =     11        @ External Interrupt 2 
+PIOIRQ3    =     12        @ External Interrupt 3 
+PIOFIQ     =     13        @ Fast Interrupt 
+                                   
+PIOSCK0    =     14        @ USART 0 signal 
+PIOTXD0    =     15        @ USART 0 transmit data 
+PIORXD0    =     16        @ USART 0 receive data  
+                                  
+PIOSCK1    =     17        @ USART 1 clock signal  
+PIOTXD1    =     18        @ USART 1 transmit data 
+PIORXD1    =     19        @ USART 1 receive data  
+                                   
+PIOSCK2    =     20        @ USART 2 clock signal   
+PIOTXD2    =     21        @ USART 2 transmit data  
+PIORXD2    =     22        @ USART 2 receive data   
+                                   
+PIOSPCK    =     23        @ SPI clock signal  
+PIOMISO    =     24        @ SPI Master In Slave 
+PIOMOSI    =     25        @ SPI Master Out Slave 
+PIONPCS0   =     26        @ SPI Peripheral Chip Select 0 
+PIONSS     =     PIONPCS0    
+PIONPCS1   =     27        @ SPI Peripheral Chip Select 1 
+PIONPCS2   =     28        @ SPI Peripheral Chip Select 2 
+PIONPCS3   =     29        @ SPI Peripheral Chip Select 3 
+
+@ PIO Controller B 
+PIOTCLK0    =    19        @ Timer 0 Clock signal input 
+PIOTIOA0    =    20        @ Timer 0 Signal A   
+PIOTIOB0    =    21        @ Timer 0 Signal B   
+                                   
+PIOTCLK1    =    22        @ Timer 1 Clock signal 
+PIOTIOA1    =    23        @ Timer 1 Signal A 
+PIOTIOB1    =    24        @ Timer 1 Signal B 
+                                       
+PIOTCLK2    =    25        @ Timer 2 Clock signal 
+PIOTIOA2    =    26        @ Timer 2 Signal A 
+PIOTIOB2    =    27        @ Timer 2 Signal B 
+                                     
+PIOMCKO     =    17        @ Master Clock Output 
+                                  
+PIOBMS      =    18        @ Boot Mode Select 
+                                  
+PIOMPI_NOE  =    0         @ MPI output enable 
+PIOMPI_NLB  =    1         @ MPI lower byte select 
+PIOMPI_NUB  =    2         @ MPI upper byte select 
+
+LED1        =    (1<<8)         @ LED 1 (linke LED) 
+LED2        =    (1<<9)         @ LED 2 
+LED3        =   (1<<10)         @ LED 3 
+LED4        =   (1<<11)         @ LED 4 
+LED5        =   (1<<12)         @ LED 5 
+LED6        =   (1<<13)         @ LED 6 
+LED7        =   (1<<14)         @ LED 7 
+LED8        =   (1<<15)         @ LED 8 
+ALL_LEDS    =   (LED1|LED2|LED3|LED4|LED5|LED6|LED7|LED8)
+
+KEY1        =    (1<<3)         @ TASTE 1 (linke Taste) auf PB3 
+KEY2        =    (1<<4)         @ TASTE 2 auf PB4 
+KEY3        =    (1<<5)         @ TASTE 3 auf PB5 
+KEY4        =    (1<<9)         @ TASTE 4 auf PA9/IRQ0 
+ALL_KEYS    =    (KEY1|KEY2|KEY3)                                            
+#endif 
diff --git a/Bachelor/Mikroprozessorsysteme2/mi2/h/pmc.h b/Bachelor/Mikroprozessorsysteme2/mi2/h/pmc.h
new file mode 100644
index 0000000..4a7ab8b
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/mi2/h/pmc.h
@@ -0,0 +1,42 @@
+//----------------------------------------------------------------------------
+// File Name           : pmc.h
+// Object              : Power Management Controller Header File.
+//
+// 1.0 27/10/02 GR     : Creation
+//----------------------------------------------------------------------------
+#ifndef pmc_h
+#define pmc_h
+
+#include "std_c.h"
+
+/*--------------------------------------------------*/
+/* Power Management Controller Structure Definition */
+/*--------------------------------------------------*/
+
+typedef struct
+{
+    at91_reg    PMC_SCER ;  /* System Clock Enable  Register */
+    at91_reg    PMC_SCDR ;  /* System Clock Disable Register */
+    at91_reg    PMC_SCSR ;  /* System Clock Status  Register */
+    at91_reg    Reserved0 ;
+    at91_reg    PMC_PCER ;  /* Peripheral Clock Enable  Register */
+    at91_reg    PMC_PCDR ;  /* Peripheral Clock Disable Register */
+    at91_reg    PMC_PCSR ;  /* Peripheral Clock Status  Register */
+} StructPMC ;
+
+/*-----------------------------------------------*/
+/* Power Saving Control Register Bits Definition */
+/*-----------------------------------------------*/
+    
+#define PMC_ARM7DIS         0x1
+#define PMC_US0             0x4
+#define PMC_PCSR_ALL        0xffff
+
+/*------------------------------------------*/ 
+/* Power Management Controller Base Address */
+/*------------------------------------------*/ 
+
+#define PMC_BASE        (( StructPMC *) 0xFFFF4000)
+
+
+#endif /* pmc_h */
diff --git a/Bachelor/Mikroprozessorsysteme2/mi2/h/pmc.inc b/Bachelor/Mikroprozessorsysteme2/mi2/h/pmc.inc
new file mode 100644
index 0000000..f58d547
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/mi2/h/pmc.inc
@@ -0,0 +1,47 @@
+@----------------------------------------------------------------------------
+@ File Name           : pmc.inc
+@ Object              : Power Management Controller Header File.
+@
+@ 1.0 27/10/02 GR     : Creation
+@----------------------------------------------------------------------------
+#ifndef pmc_inc
+#define pmc_inc
+
+@--------------------------------------------------
+@ Power Management Controller Structure Definition 
+@--------------------------------------------------
+
+PMC_SCER = 0x0  @ System Clock Enable  Register 
+PMC_SCDR = 0x4  @ System Clock Disable Register 
+PMC_SCSR = 0x8  @ System Clock Status  Register 
+@ Reserved 
+PMC_PCER = 0x10  @ Peripheral Clock Enable  Register 
+PMC_PCDR = 0x14  @ Peripheral Clock Disable Register 
+PMC_PCSR = 0x18  @ Peripheral Clock Status  Register 
+
+@-----------------------------------------------
+@ Power Saving Control Register Bits Definition 
+@-----------------------------------------------
+    
+PMC_ARM7DIS = 0x1
+PMC_US0 = (1<<2)
+PMC_US1 = (1<<3)
+PMC_US2 = (1<<4)
+PMC_TC0 = (1<<6)		
+PMC_TC1 = (1<<7)		
+PMC_TC2 = (1<<8)		
+PMC_TC3 = (1<<9)		
+PMC_TC4 = (1<<10)		
+PMC_TC5 = (1<<11)		
+PMC_PIOA = (1<<13)
+PMC_PIOB = (1<<14)
+PMC_PCSR_ALL = 0xffff
+
+@------------------------------------------ 
+@ Power Management Controller Base Address 
+@------------------------------------------ 
+
+PMC_BASE = 0xFFFF4000
+
+
+#endif 
diff --git a/Bachelor/Mikroprozessorsysteme2/mi2/h/ser_io.h b/Bachelor/Mikroprozessorsysteme2/mi2/h/ser_io.h
new file mode 100644
index 0000000..8bf3eb5
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/mi2/h/ser_io.h
@@ -0,0 +1,18 @@
+//*----------------------------------------------------------------------------
+//* File Name           : ser_io.h
+//* Object              : Standard C Header File
+//*
+//* 1.0 27/10/02 GR     : Creation
+//*----------------------------------------------------------------------------
+
+#ifndef ser_io_h
+#define ser_io_h
+
+void putchar(int);
+unsigned char getchar(void);
+void init_ser(void);
+void puts(char*);
+unsigned int gets(char*,int);
+unsigned int getpw(char*,int);
+
+#endif /* ser_io_h */
diff --git a/Bachelor/Mikroprozessorsysteme2/mi2/h/std_c.h b/Bachelor/Mikroprozessorsysteme2/mi2/h/std_c.h
new file mode 100644
index 0000000..b55e229
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/mi2/h/std_c.h
@@ -0,0 +1,30 @@
+//*----------------------------------------------------------------------------
+//* File Name           : std_c.h
+//* Object              : Standard C Header File
+//*
+//* 1.0 27/10/02 GR     : Creation
+//*----------------------------------------------------------------------------
+
+#ifndef std_c_h
+#define std_c_h
+
+/*----------------*/
+/* Standard types */
+/*----------------*/
+
+typedef unsigned int        u_int   ;
+typedef unsigned short      u_short ;
+typedef unsigned char       u_char  ;
+
+
+/* AT91 Register type */
+typedef volatile unsigned int at91_reg ;
+
+/*----------------*/
+/* Boolean values */
+/*----------------*/
+
+#define TRUE                1
+#define FALSE               0
+
+#endif /* std_c_h */
diff --git a/Bachelor/Mikroprozessorsysteme2/mi2/h/tc.h b/Bachelor/Mikroprozessorsysteme2/mi2/h/tc.h
new file mode 100644
index 0000000..19cc48b
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/mi2/h/tc.h
@@ -0,0 +1,306 @@
+//-----------------------------------------------------------------------------
+// File Name           : tc.h
+// Object              : Timer Counter Header File
+//
+// 1.0 27/10/02 GR     : Creation
+//-----------------------------------------------------------------------------
+
+#ifndef tc_h
+#define tc_h
+
+#include    "std_c.h"
+
+/*-------------------------------------------*/
+/* Timer User Interface Structure Definition */
+/*-------------------------------------------*/
+
+typedef struct
+{
+    at91_reg        TC_CCR ;        /* Control Register */
+    at91_reg        TC_CMR ;        /* Mode Register */
+    at91_reg        Reserved0 ;
+    at91_reg        Reserved1 ;
+    at91_reg        TC_CV ;         /* Counter value */
+    at91_reg        TC_RA ;         /* Register A */
+    at91_reg        TC_RB ;         /* Register B */
+    at91_reg        TC_RC ;         /* Register C */
+    at91_reg        TC_SR ;         /* Status Register */
+    at91_reg        TC_IER ;        /* Interrupt Enable Register */
+    at91_reg        TC_IDR ;        /* Interrupt Disable Register */
+    at91_reg        TC_IMR ;        /* Interrupt Mask Register */
+    at91_reg        Reserved2 ;
+    at91_reg        Reserved3 ;
+    at91_reg        Reserved4 ;
+    at91_reg        Reserved5 ;
+} StructTC ;
+
+#define NB_TC_CHANNEL       3
+
+typedef struct
+{
+    StructTC        TC[NB_TC_CHANNEL] ;
+    at91_reg        TC_BCR ;        /* Block Control Register */
+    at91_reg        TC_BMR ;        /* Block Mode Register  */
+} StructTCBlock ;
+
+/*--------------------------------------------------------*/
+/* TC_CCR: Timer Counter Control Register Bits Definition */
+/*--------------------------------------------------------*/
+#define TC_CLKEN            0x1
+#define TC_CLKDIS           0x2
+#define TC_SWTRG            0x4
+
+/*-----------------------------------------------------*/
+/* TC_CMR: Timer Counter Mode Register Bits Definition */
+/*-----------------------------------------------------*/
+
+/*-----------------*/
+/* Clock Selection */
+/*-----------------*/
+#define TC_CLKS                  0x7
+#define TC_CLKS_MCK2             0x0
+#define TC_CLKS_MCK8             0x1
+#define TC_CLKS_MCK32            0x2
+#define TC_CLKS_MCK128           0x3
+#define TC_CLKS_MCK1024          0x4
+#define TC_CLKS_XC0              0x5
+#define TC_CLKS_XC1              0x6
+#define TC_CLKS_XC2              0x7
+
+/*-----------------*/
+/* Clock Inversion */
+/*-----------------*/
+#define TC_CLKI             0x8
+
+/*------------------------*/
+/* Burst Signal Selection */
+/*------------------------*/
+#define TC_BURST            0x30
+#define TC_BURST_NONE       0x0
+#define TC_BUSRT_XC0        0x10
+#define TC_BURST_XC1        0x20
+#define TC_BURST_XC2        0x30
+
+/*------------------------------------------------------*/
+/* Capture Mode : Counter Clock Stopped with RB Loading */
+/*------------------------------------------------------*/
+#define TC_LDBSTOP          0x40
+
+/*-------------------------------------------------------*/
+/* Waveform Mode : Counter Clock Stopped with RC Compare */
+/*-------------------------------------------------------*/
+#define TC_CPCSTOP          0x40
+
+/*-------------------------------------------------------*/
+/* Capture Mode : Counter Clock Disabled with RB Loading */
+/*--------------------------------------------------------*/
+#define TC_LDBDIS           0x80
+
+/*--------------------------------------------------------*/
+/* Waveform Mode : Counter Clock Disabled with RC Compare */
+/*--------------------------------------------------------*/
+#define TC_CPCDIS           0x80
+
+/*------------------------------------------------*/
+/* Capture Mode : External Trigger Edge Selection */
+/*------------------------------------------------*/
+#define TC_ETRGEDG                  0x300
+#define TC_ETRGEDG_EDGE_NONE        0x0
+#define TC_ETRGEDG_RISING_EDGE      0x100
+#define TC_ETRGEDG_FALLING_EDGE     0x200
+#define TC_ETRGEDG_BOTH_EDGE        0x300
+
+/*-----------------------------------------------*/
+/* Waveform Mode : External Event Edge Selection */
+/*-----------------------------------------------*/
+#define TC_EEVTEDG                  0x300
+#define TC_EEVTEDG_EDGE_NONE        0x0
+#define TC_EEVTEDG_RISING_EDGE      0x100
+#define TC_EEVTEDG_FALLING_EDGE     0x200
+#define TC_EEVTEDG_BOTH_EDGE        0x300
+
+/*--------------------------------------------------------*/
+/* Capture Mode : TIOA or TIOB External Trigger Selection */
+/*--------------------------------------------------------*/
+#define TC_ABETRG                   0x400
+#define TC_ABETRG_TIOB              0x0
+#define TC_ABETRG_TIOA              0x400
+
+/*------------------------------------------*/
+/* Waveform Mode : External Event Selection */
+/*------------------------------------------*/
+#define TC_EEVT                     0xC00
+#define TC_EEVT_TIOB                0x0
+#define TC_EEVT_XC0                 0x400
+#define TC_EEVT_XC1                 0x800
+#define TC_EEVT_XC2                 0xC00
+
+/*--------------------------------------------------*/
+/* Waveform Mode : Enable Trigger on External Event */
+/*--------------------------------------------------*/
+#define TC_ENETRG                   0x1000
+
+/*----------------------------------*/
+/* RC Compare Enable Trigger Enable */
+/*----------------------------------*/
+#define TC_CPCTRG                   0x4000
+
+/*----------------*/
+/* Mode Selection */
+/*----------------*/
+#define TC_WAVE                     0x8000
+#define TC_CAPT                     0x0
+
+/*-------------------------------------*/
+/* Capture Mode : RA Loading Selection */
+/*-------------------------------------*/
+#define TC_LDRA                     0x30000
+#define TC_LDRA_EDGE_NONE           0x0
+#define TC_LDRA_RISING_EDGE         0x10000
+#define TC_LDRA_FALLING_EDGE        0x20000
+#define TC_LDRA_BOTH_EDGE           0x30000
+
+/*-------------------------------------------*/
+/* Waveform Mode : RA Compare Effect on TIOA */
+/*-------------------------------------------*/
+#define TC_ACPA                     0x30000
+#define TC_ACPA_OUTPUT_NONE         0x0
+#define TC_ACPA_SET_OUTPUT          0x10000
+#define TC_ACPA_CLEAR_OUTPUT        0x20000
+#define TC_ACPA_TOGGLE_OUTPUT       0x30000
+
+/*-------------------------------------*/
+/* Capture Mode : RB Loading Selection */
+/*-------------------------------------*/
+#define TC_LDRB                     0xC0000
+#define TC_LDRB_EDGE_NONE           0x0
+#define TC_LDRB_RISING_EDGE         0x40000
+#define TC_LDRB_FALLING_EDGE        0x80000
+#define TC_LDRB_BOTH_EDGE           0xC0000
+
+/*-------------------------------------------*/
+/* Waveform Mode : RC Compare Effect on TIOA */
+/*-------------------------------------------*/
+#define TC_ACPC                     0xC0000
+#define TC_ACPC_OUTPUT_NONE         0x0
+#define TC_ACPC_SET_OUTPUT          0x40000
+#define TC_ACPC_CLEAR_OUTPUT        0x80000
+#define TC_ACPC_TOGGLE_OUTPUT       0xC0000
+
+/*-----------------------------------------------*/
+/* Waveform Mode : External Event Effect on TIOA */
+/*-----------------------------------------------*/
+#define TC_AEEVT                    0x300000
+#define TC_AEEVT_OUTPUT_NONE        0x0
+#define TC_AEEVT_SET_OUTPUT         0x100000
+#define TC_AEEVT_CLEAR_OUTPUT       0x200000
+#define TC_AEEVT_TOGGLE_OUTPUT      0x300000
+
+/*-------------------------------------------------*/
+/* Waveform Mode : Software Trigger Effect on TIOA */
+/*-------------------------------------------------*/
+#define TC_ASWTRG                   0xC00000
+#define TC_ASWTRG_OUTPUT_NONE       0x0
+#define TC_ASWTRG_SET_OUTPUT        0x400000
+#define TC_ASWTRG_CLEAR_OUTPUT      0x800000
+#define TC_ASWTRG_TOGGLE_OUTPUT     0xC00000
+
+/*-------------------------------------------*/
+/* Waveform Mode : RB Compare Effect on TIOB */
+/*-------------------------------------------*/
+#define TC_BCPB                     0x1000000
+#define TC_BCPB_OUTPUT_NONE         0x0
+#define TC_BCPB_SET_OUTPUT          0x1000000
+#define TC_BCPB_CLEAR_OUTPUT        0x2000000
+#define TC_BCPB_TOGGLE_OUTPUT       0x3000000
+
+/*-------------------------------------------*/
+/* Waveform Mode : RC Compare Effect on TIOB */
+/*-------------------------------------------*/
+#define TC_BCPC                     0xC000000
+#define TC_BCPC_OUTPUT_NONE         0x0
+#define TC_BCPC_SET_OUTPUT          0x4000000
+#define TC_BCPC_CLEAR_OUTPUT        0x8000000
+#define TC_BCPC_TOGGLE_OUTPUT       0xC000000
+
+/*-----------------------------------------------*/
+/* Waveform Mode : External Event Effect on TIOB */
+/*-----------------------------------------------*/
+#define TC_BEEVT                    0x10000000
+#define TC_BEEVT_OUTPUT_NONE        0x0
+#define TC_BEEVT_SET_OUTPUT         0x40000000
+#define TC_BEEVT_CLEAR_OUTPUT       0x80000000
+#define TC_BEEVT_TOGGLE_OUTPUT      0xC0000000
+
+/*- -----------------------------------------------*/
+/* Waveform Mode : Software Trigger Effect on TIOB */
+/*-------------------------------------------------*/
+#define TC_BSWTRG                   0xC0000000
+#define TC_BSWTRG_OUTPUT_NONE       0x0
+#define TC_BSWTRG_SET_OUTPUT        0x40000000
+#define TC_BSWTRG_CLEAR_OUTPUT      0x80000000
+#define TC_BSWTRG_TOGGLE_OUTPUT     0xC0000000
+
+/*-----------------------------------------------*/
+/* TC_SR: Timer Counter Status Register Bits Definition */
+/*-----------------------------------------------*/
+
+#define TC_COVFS            0x1         /* Counter Overflow Status */
+#define TC_LOVRS            0x2         /* Load Overrun Status */
+#define TC_CPAS             0x4         /* RA Compare Status */
+#define TC_CPBS             0x8         /* RB Compare Status */
+#define TC_CPCS             0x10        /* RC Compare Status */
+#define TC_LDRAS            0x20        /* RA Loading Status */
+#define TC_LDRBS            0x40        /* RB Loading Status */
+#define TC_ETRGS            0x80        /* External Trigger Status */
+#define TC_CLKSTA           0x10000     /* Clock Status */
+#define TC_MTIOA            0x20000     /* TIOA Mirror */
+#define TC_MTIOB            0x40000     /* TIOB Status */
+
+/*------------------------------------------------------*/
+/* TC_BCR: Timer Counter Block Control Register Bits Definition */
+/*------------------------------------------------------*/
+
+#define TC_SYNC             0x1         /* Synchronisation Trigger */
+
+/*---------------------------------------------------*/
+/*  TC_BMR: Timer Counter Block Mode Register Bits Definition */
+/*---------------------------------------------------*/
+#define TC_TC0XC0S          0x3        /* External Clock Signal 0 Selection */
+#define TC_TCLK0XC0         0x0         
+#define TC_NONEXC0          0x1
+#define TC_TIOA1XC0         0x2
+#define TC_TIOA2XC0         0x3
+
+#define TC_TC1XC1S          0xC        /* External Clock Signal 1 Selection */
+#define TC_TCLK1XC1         0x0
+#define TC_NONEXC1          0x4
+#define TC_TIOA0XC1         0x8
+#define TC_TIOA2XC1         0xC
+
+#define TC_TC2XC2S          0x30       /* External Clock Signal 2 Selection */
+#define TC_TCLK2XC2         0x0
+#define TC_NONEXC2          0x10
+#define TC_TIOA0XC2         0x20
+#define TC_TIOA1XC2         0x30
+
+/*-----------------------*/
+/* Peripheral Memory Map */
+/*-----------------------*/
+
+#define TCB0_BASE       ((StructTC *)0xFFFD0000)   /* Channels 0, 1, 2 */
+#define TCB1_BASE       ((StructTC *)0xFFFD0040)   /* Channels 0, 1, 2 */
+#define TCB2_BASE       ((StructTC *)0xFFFD0080)   /* Channels 0, 1, 2 */
+#define TC0_BCR         ((at91_reg *)0xFFFD00C0)
+#define TC0_BMR         ((at91_reg *)0xFFFD00C4)
+
+
+#define TCB3_BASE       ((StructTC *)0xFFFD4000)   /* Channels 3, 4, 5 */
+#define TCB4_BASE       ((StructTC *)0xFFFD4040)   /* Channels 0, 1, 2 */
+#define TCB5_BASE       ((StructTC *)0xFFFD4080)   /* Channels 0, 1, 2 */
+#define TC1_BCR         ((at91_reg *)0xFFFD40C0)
+#define TC1_BMR         ((at91_reg *)0xFFFD40C4)
+
+
+#endif /* tc_h */
+
diff --git a/Bachelor/Mikroprozessorsysteme2/mi2/h/usart.h b/Bachelor/Mikroprozessorsysteme2/mi2/h/usart.h
new file mode 100644
index 0000000..d96656d
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/mi2/h/usart.h
@@ -0,0 +1,120 @@
+//*-----------------------------------------------------------------------------
+//* File Name           : usart.h
+//* Object              : USART Header File.
+//*
+//* 1.0 27/10/02 GR    : Creation
+//*----------------------------------------------------------------------------
+
+#ifndef usart_h
+#define usart_h
+
+#include "std_c.h"
+
+
+/*-------------------------------------------*/
+/* USART User Interface Structure Definition */
+/*-------------------------------------------*/
+
+typedef struct
+{
+  at91_reg            US_CR ;         /* Control Register */
+  at91_reg            US_MR ;         /* Mode Register */
+  at91_reg            US_IER ;        /* Interrupt Enable Register */
+  at91_reg            US_IDR ;        /* Interrupt Disable Register */
+  at91_reg            US_IMR ;        /* Interrupt Mask Register */
+  at91_reg            US_CSR ;        /* Channel Status Register */
+  at91_reg            US_RHR ;        /* Receive Holding Register */
+  at91_reg            US_THR ;        /* Transmit Holding Register */
+  at91_reg            US_BRGR ;       /* Baud Rate Generator Register */
+  at91_reg            US_RTOR ;       /* Receiver Timeout Register */
+  at91_reg            US_TTGR ;       /* Transmitter Time-guard Register */
+  at91_reg            Reserved ;
+  at91_reg            US_RPR ;        /* Receiver Pointer Register */
+  at91_reg            US_RCR ;        /* Receiver Counter Register */
+  at91_reg            US_TPR ;        /* Transmitter Pointer Register */
+  at91_reg            US_TCR ;        /* Transmitter Counter Register */
+} StructUSART ;
+
+/*--------------------------*/
+/* US_CR : Control Register */
+/*--------------------------*/
+
+#define US_RSTRX                0x0004      /* Reset Receiver */
+#define US_RSTTX                0x0008      /* Reset Transmitter */
+#define US_RXEN                 0x0010      /* Receiver Enable */
+#define US_RXDIS                0x0020      /* Receiver Disable */
+#define US_TXEN                 0x0040      /* Transmitter Enable */
+#define US_TXDIS                0x0080      /* Transmitter Disable */
+#define US_RSTSTA               0x0100      /* Reset Status Bits */
+#define US_STTBRK               0x0200      /* Start Break */
+#define US_STPBRK               0x0400      /* Stop Break */
+#define US_STTTO                0x0800      /* Start Time-out */
+#define US_SENDA                0x1000      /* Send Address */
+
+/*-----------------------*/
+/* US_MR : Mode Register */
+/*-----------------------*/
+
+#define US_CLKS                 0x0030      /* Clock Selection */
+#define US_CLKS_MCK             0x00        /* Master Clock */
+#define US_CLKS_MCK8            0x10        /* Master Clock divided by 8 */
+#define US_CLKS_SCK             0x20        /* External Clock */
+#define US_CLKS_SLCK            0x30        /* Slow Clock */
+
+#define US_CHRL                 0x00C0      /* Byte Length */
+#define US_CHRL_5               0x00        /* 5 bits */
+#define US_CHRL_6               0x40        /* 6 bits */
+#define US_CHRL_7               0x80        /* 7 bits */
+#define US_CHRL_8               0xC0        /* 8 bits */
+
+#define US_SYNC                 0x0100      /* Synchronous Mode Enable */
+
+#define US_PAR                  0x0E00      /* Parity Mode */
+#define US_PAR_EVEN             0x00        /* Even Parity */
+#define US_PAR_ODD              0x200       /* Odd Parity */
+#define US_PAR_SPACE            0x400       /* Space Parity to 0 */
+#define US_PAR_MARK             0x600       /* Marked Parity to 1 */
+#define US_PAR_NO               0x800       /* No Parity */
+#define US_PAR_MULTIDROP        0xC00       /* Multi-drop Mode */
+
+#define US_NBSTOP               0x3000      /* Stop Bit Number */
+#define US_NBSTOP_1             0x0000      /* 1 Stop Bit */
+#define US_NBSTOP_1_5           0x1000      /* 1.5 Stop Bits */
+#define US_NBSTOP_2             0x2000      /* 2 Stop Bits */
+
+#define US_CHMODE                   0xC000  /* Channel Mode */
+#define US_CHMODE_NORMAL            0x0000  /* Normal Mode */
+#define US_CHMODE_AUTOMATIC_ECHO    0x4000  /* Automatic Echo */
+#define US_CHMODE_LOCAL_LOOPBACK    0x8000  /* Local Loopback */
+#define US_CHMODE_REMOTE_LOOPBACK   0xC000  /* Remote Loopback */
+
+#define US_MODE9                0x20000     /* 9 Bit Mode */
+
+#define US_CLKO                 0x40000     /* Baud Rate Output Enable */
+
+
+/*---------------------------------------------------------------*/
+/* US_IER, US_IDR, US_IMR, US_IMR: Status and Interrupt Register */
+/*---------------------------------------------------------------*/
+
+#define US_RXRDY            0x001       /* Receiver Ready */
+#define US_TXRDY            0x002       /* Transmitter Ready */
+#define US_RXBRK            0x004       /* Receiver Break */
+#define US_ENDRX            0x008       /* End of Receiver PDC Transfer */
+#define US_ENDTX            0x010       /* End of Transmitter PDC Transfer */
+#define US_OVRE             0x020       /* Overrun Error */
+#define US_FRAME            0x040       /* Framing Error */
+#define US_PARE             0x080       /* Parity Error */
+#define US_TIMEOUT          0x100       /* Receiver Timeout */
+#define US_TXEMPTY          0x200       /* Transmitter Empty */
+
+#define US_MASK_IRQ_TX      (US_TXRDY | US_ENDTX | US_TXEMPTY)
+#define US_MASK_IRQ_RX      (US_RXRDY | US_ENDRX | US_TIMEOUT)
+#define US_MASK_IRQ_ERROR   (US_PARE | US_FRAME | US_OVRE | US_RXBRK)
+
+
+#define USART2     ((StructUSART*)0xFFFC8000)      /* USART 2 */
+#define USART1     ((StructUSART*)0xFFFC4000)      /* USART 1 */
+#define USART0     ((StructUSART*)0xFFFC0000)      /* USART 0 */
+
+#endif /* usart_h */
diff --git a/Bachelor/Mikroprozessorsysteme2/mi2/h/usart.inc b/Bachelor/Mikroprozessorsysteme2/mi2/h/usart.inc
new file mode 100644
index 0000000..7cc4b5f
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/mi2/h/usart.inc
@@ -0,0 +1,115 @@
+@*-----------------------------------------------------------------------------
+@* File Name           : usart.inc
+@* Object              : USART Header File.
+@*
+@* 1.0 01/04/00	: Creation
+@*----------------------------------------------------------------------------
+
+#ifndef usart_inc
+#define usart_inc
+
+
+@-------------------------------------------
+@ USART User Interface Structure Definition 
+@-------------------------------------------
+	
+US_CR = 0x0         @ Control Register 
+US_MR = 0x4         @ Mode Register 
+US_IER = 0x8        @ Interrupt Enable Register 
+US_IDR = 0xc        @ Interrupt Disable Register 
+US_IMR = 0x10        @ Interrupt Mask Register 
+US_CSR = 0x14        @ Channel Status Register 
+US_RHR = 0x18        @ Receive Holding Register 
+US_THR = 0x1c        @ Transmit Holding Register 
+US_BRGR = 0x20       @ Baud Rate Generator Register 
+US_RTOR = 0x24       @ Receiver Timeout Register 
+US_TTGR = 0x28       @ Transmitter Time-guard Register 
+   @      Reserved 
+US_RPR = 0x30        @ Receiver Pointer Register 
+US_RCR = 0x34        @ Receiver Counter Register 
+US_TPR = 0x38        @ Transmitter Pointer Register 
+US_TCR = 0x3c        @ Transmitter Counter Register 
+
+@--------------------------
+@ US_CR : Control Register 
+@--------------------------
+
+US_RSTRX	=	0x0004      @ Reset Receiver 
+US_RSTTX	=	0x0008      @ Reset Transmitter 
+US_RXEN		=	0x0010      @ Receiver Enable 
+US_RXDIS	=	0x0020      @ Receiver Disable 
+US_TXEN		=	0x0040      @ Transmitter Enable 
+US_TXDIS	=	0x0080      @ Transmitter Disable 
+US_RSTSTA	=	0x0100      @ Reset Status Bits 
+US_STTBRK	=	0x0200      @ Start Break 
+US_STPBRK	=	0x0400      @ Stop Break 
+US_STTTO	=	0x0800      @ Start Time-out 
+US_SENDA	=	0x1000      @ Send Address 
+
+@-----------------------
+@ US_MR : Mode Register 
+@-----------------------
+
+US_CLKS         =        0x0030      @ Clock Selection 
+US_CLKS_MCK     =        0x00        @ Master Clock 
+US_CLKS_MCK8    =        0x10        @ Master Clock divided by 8 
+US_CLKS_SCK     =        0x20        @ External Clock 
+US_CLKS_SLCK    =        0x30        @ Slow Clock 
+
+US_CHRL         =        0x00C0      @ Byte Length 
+US_CHRL_5       =        0x00        @ 5 bits 
+US_CHRL_6       =        0x40        @ 6 bits 
+US_CHRL_7       =        0x80        @ 7 bits 
+US_CHRL_8       =        0xC0        @ 8 bits 
+
+US_SYNC         =        0x0100      @ Synchronous Mode Enable 
+
+US_PAR          =        0x0E00      @ Parity Mode 
+US_PAR_EVEN     =        0x00        @ Even Parity 
+US_PAR_ODD      =        0x200       @ Odd Parity 
+US_PAR_SPACE    =        0x400       @ Space Parity to 0 
+US_PAR_MARK     =        0x600       @ Marked Parity to 1 
+US_PAR_NO       =        0x800       @ No Parity 
+US_PAR_MULTIDROP =       0xC00       @ Multi-drop Mode 
+
+US_NBSTOP        =       0x3000      @ Stop Bit Number 
+US_NBSTOP_1      =       0x0000      @ 1 Stop Bit 
+US_NBSTOP_1_5    =       0x1000      @ 1.5 Stop Bits 
+US_NBSTOP_2      =       0x2000      @ 2 Stop Bits 
+
+US_CHMODE                =   0xC000  @ Channel Mode 
+US_CHMODE_NORMAL         =   0x0000  @ Normal Mode 
+US_CHMODE_AUTOMATIC_ECHO =   0x4000  @ Automatic Echo 
+US_CHMODE_LOCAL_LOOPBACK =   0x8000  @ Local Loopback 
+US_CHMODE_REMOTE_LOOPBACK =  0xC000  @ Remote Loopback 
+
+US_MODE9        =        0x20000     @ 9 Bit Mode 
+
+US_CLKO         =        0x40000     @ Baud Rate Output Enable 
+
+
+@---------------------------------------------------------------
+@ US_IER, US_IDR, US_IMR, US_IMR: Status and Interrupt Register 
+@---------------------------------------------------------------
+
+US_RXRDY       =     0x001       @ Receiver Ready 
+US_TXRDY       =     0x002       @ Transmitter Ready 
+US_RXBRK       =     0x004       @ Receiver Break 
+US_ENDRX       =     0x008       @ End of Receiver PDC Transfer 
+US_ENDTX       =     0x010       @ End of Transmitter PDC Transfer 
+US_OVRE        =     0x020       @ Overrun Error 
+US_FRAME       =     0x040       @ Framing Error 
+US_PARE        =     0x080       @ Parity Error 
+US_TIMEOUT     =     0x100       @ Receiver Timeout 
+US_TXEMPTY     =     0x200       @ Transmitter Empty 
+
+US_MASK_IRQ_TX    =  (US_TXRDY | US_ENDTX | US_TXEMPTY)
+US_MASK_IRQ_RX    =  (US_RXRDY | US_ENDRX | US_TIMEOUT)
+US_MASK_IRQ_ERROR =  (US_PARE | US_FRAME | US_OVRE | US_RXBRK)
+
+
+USART2_BASE  =   0xFFFC8000      @ USART 2 
+USART1_BASE  =   0xFFFC4000      @ USART 1 
+USART0_BASE  =   0xFFFC0000      @ USART 0 
+
+#endif