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<!DOCTYPE html PUBLIC "-//w3c//dtd html 4.0 transitional//en">
<html><head>
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
<meta name="GENERATOR" content="Mozilla/4.5 [en]C-NECCK (Win98; U) [Netscape]">
<meta name="Author" content="J. Van der Spiegel">
<meta name="Description" content="Overview of ABEL Hardware Description Language">
<meta name="KeyWords" content="ABEL, HDL, Digial Design"><title>HDL-ABEL Primer</title></head><body>
<center>
<h1>
<i>University of Pennsylvania<br>
</i><b><font size="+1"><a href="http://www.ee.upenn.edu/">Department of Electrical
Engineering</a></font></b></h1></center>
<center>
<h1>
ABEL-HDL Primer</h1></center>
<h2>
<font size="+1">ABEL Primer</font> <a name="Contents"></a><font size="+1">Contents</font></h2>
<ul>
<li>
1. <a href="#Introduction">Introduction</a></li>
<li>
2. <a href="#structure">Basic structure of an ABEL source file</a></li>
<li>
3. <a href="#Declarations">Declarations</a> (module, pin, node, constants)</li>
<li>
4. <a href="#Numbers">Numbers</a></li>
<li>
5. <a href="#Directives">Directives</a></li>
<li>
6. <a href="#Sets">Sets</a></li>
<ul>
<li>
a. <a href="#Indexing">Indexing or accessing a set</a></li>
<li>
b. <a href="#Set%20Operations">Set operations</a></li>
</ul>
<li>
6. <a href="#Operators">Operators</a></li>
<ul>
<li>
a. <a href="#Logical">Logical Operators</a></li>
<li>
b. <a href="#Arithmetic">Arithmetic operators</a></li>
<li>
c. <a href="#Relational">Relational operators</a></li>
<li>
d. <a href="#Assignment">Assignment operators</a></li>
<li>
e. <a href="#priority">Operator priority</a></li>
</ul>
<li>
8. <a href="#Logic">Logic description</a></li>
<ul>
<li>
a. <a href="#Equations">Equations</a></li>
<ul>
<li>
<a href="#%22When-Then-Else%22">When-Then-Else statement</a></li>
</ul>
<li>
b. <a href="#Truth">Truth Table</a></li>
<li>
c. <a href="#State">State Description</a></li>
<ul>
<li>
<a href="#State">State_diagram</a></li>
<li>
<a href="#If-Else-Then">If-Then-Else statement</a></li>
<li>
<a href="#with">With statement</a></li>
<li>
<a href="#Case">Case statement</a></li>
</ul>
<li>
d. <a href="#extensions">Dot extensions</a></li>
</ul>
<li>
9. <a href="#vectors">Test vectors</a></li>
<li>
10. <a href="#Property">Device Specific (Property) Statements</a></li>
<li>
11. <a href="#Miscellaneous">Miscellaneous</a></li>
<ul>
<li>
a. <a href="#Active-low">Active-low declarations</a></li>
</ul>
<li>
12. Examples</li>
<ul>
<li>
<a href="http://www.ese.upenn.edu/rca/software/abel/abel.ex2.html">Moore Finite State Machine</a></li>
<li>
<a href="http://www.ese.upenn.edu/rca/software/abel/abel.ex1.html">Mealy Finite State Machine</a></li>
<li>
<a href="http://www.ese.upenn.edu/rca/software/abel/abel.ex3.html">Synchronous Mealy Finite State Machine</a></li>
</ul>
<li>
<a href="http://www.ee.upenn.edu/rca/software/xilinx/foundation/commistakes.html">Common
Mistakes</a></li>
<li>
<a href="#References">References</a></li>
<li>
<a href="#Acknowledgement">Acknowledgement</a></li>
</ul>
<h2>
1 <a name="Introduction"></a>Introduction</h2>
ABEL (Advanced Boolean Equation Language) allows you to enter behavior-like
descriptions of a logic circuit. ABEL is an industry-standard hardware
description language (HDL) that was developed by Data I/O Corporation for
programmable logic devices (PLD). There are other hardware description
languages such as VHDL and Verilog. ABEL is a simpler language than VHDL
which is capable of describing systems of larger complexity.
<p>ABEL can be used to describe the behavior of a system in a variety of
forms, including logic equations, truth tables, and state diagrams using
C-like statements. The ABEL compiler allows designs to be simulated and
implemented into PLDs such as PALs, CPLDs and FPGAs.
</p><p>Following is a brief overview of some of the features and syntax of
ABEL. It is not intended to be a complete discussion of all its features.
This ABEL primer will get you started with writing ABEL code. In case you
are familiar with ABEL, this write-up can serve as a quick reference of
the most often used commands. For more advanced features, please consult
an ABEL manual or the Xilinx on-line documentation.
</p><h2>
2. Basic <a name="structure"></a>structure of an ABEL source file</h2>
An ABEL source file consists of the following elements.
<ul>
<li>
Header:<b> </b>including Module, Options and Title</li>
<li>
Declarations: Pin, Constant, Node, Sets, States. Library.</li>
<li>
Logic Descriptions: Equations, Truth-table, State_diagram</li>
<li>
Test Vectors: Test_vectors</li>
<li>
End</li>
</ul>
Keywords (words recognized by ABEL such as commands, e.g. goto, if, then,
module, etc.) are not case sensitive. User-supplied names and labels (identifier)
can be uppercase, lowercase or mixed-case, but <u>are case-sensitive</u>
(input1 is different from Input1).
<p>A typical <a name="template"></a>template is given below.
</p><ul><b><font face="Courier">module</font></b> <i>module name</i>
<p>[<b><font face="Courier">title</font></b> <i>string</i>]
</p><p>[deviceID <b><font face="Courier">device</font></b> deviceType;]
</p><p><i>pin declarations</i>
</p><p><i>other declarations</i>
</p><p><b><font face="Courier">equations</font></b>
</p><p><i>equations</i>
</p><p>[<b><font face="Courier">Test_Vectors</font></b>]
</p><p><i>test vectors</i>
</p><p><b><font face="Courier">end</font></b> <i>module name</i></p></ul>
The following source file is an <a name="example"></a>example of a
half adder:
<ul><font face="Courier"><b>module</b> <i>my_first_circuit;</i></font>
<br><font face="Courier"><b>title</b> <i>'ee200 assignment 1'</i></font>
<br><font face="Courier">EE200XY <b>device</b> 'XC4003E';</font>
<br>
<br>
<p><font face="Courier">" input pins</font>
<br><font face="Courier">A, B pin 3, 5;</font>
</p><p><font face="Courier">" output pins</font>
<br><font face="Courier">SUM, Carry_out pin 15, 18 istype 'com';</font>
</p><p><b><font face="Courier">equations</font></b>
</p><p><font face="Courier">SUM = (A & !B) # (!A & B) ;</font>
<br><font face="Courier">Carry_out = A & B;</font>
</p><p><font face="Courier"><b>end</b> <i>my_first_circuit;</i></font>
<br>
<br> </p></ul>
A brief explanation of the statements follow. For a more detailed discussion
see the following sections or consult an ABEL-HDL manual. When using ABEL
with the Xilinx CAD software, you can use the ABEL wizard which will give
a template of the basic structure and insert some of the keywords. Also
the Language Assistant in the ABEL editor provides on-line help. Go to
the TOOLS ->LANGUAGE ASSISTANT menu. The Language templates give a description
of most ABEL commands, syntax, hierarchy, etc, while the Synthesis template
gives examples of typical circuits.
<h2>
3. <a name="Declarations"></a>Declarations</h2>
<b><font face="Courier">Module</font></b>: each source files starts with
a module statement followed by a module name (identifier). Large source
files often consist of multiple modules with their own title, equations,
end statement, etc.
<p><b><font face="Courier">Title</font></b>: is <u>optional</u> and can
be used to identify the project. The title name must be between single
quotes. The title line is ignored by the compiler but is handy for documentation.
</p><p><b><i>String</i></b>: is a series of ASCII characters enclosed by single
quotes. Strings are used for TITLE, OPTIONS statements, and in pin, node
and attribute declarations.
</p><p><b><font face="Courier">device</font></b>: this declaration is <u>optional</u>
and associates a device identifier with a specific programmable logic device.
The device statement must end with a semicolon. When you are using the
Xilinx CAD system to compile the design, it is better not to put the device
statement in the source file to keep your design independent of the device.
When you create a new project in Xilinx you will specify the device type
(can also be changed in the Project Manager window using the Project Information
button). The format is as follows:
</p><ul>device_id <font face="Courier">device</font> 'real_device';
<p>Example: MY_DECODER <font face="Courier">device </font>'XC4003E';
<br>
<br> </p></ul>
<b><i>comments</i></b>: comments can be inserted anywhere in the file and
begin with a double quote and end with another double quote or the end
of the line, whatever comes first.
<p><b><font face="Courier">pin</font></b>: pin declarations tell the compiler
which symbolic names are associated with the devices external pins. Format:
</p><ul><font face="Courier">[!]pin_id pin [pin#] [istype 'attributes'] ;</font></ul>
One can specify more than one pin per line:
<ul>[!]pin_id , pin_id, pin_id <font face="Courier">pin [</font>pin#, [pin#,
[pin#]]] [<font face="Courier">istype</font> 'attributes'];
<p>Example:
</p><p><font face="Courier">IN1, IN2, A1 pin 2, 3, 4;</font>
</p><p><font face="Courier">OUT1 pin 9 istype 'reg';</font>
</p><p><font face="Courier">ENABLE pin;</font>
</p><p><font face="Courier">!Chip_select pin 12 istype 'com';</font>
</p><p><font face="Courier">!S0..!S6 pin istype 'com';</font>
<br>
<br> </p></ul>
You do not need to specify the pin. Pin numbers can be specified later
by using a "user constraint file " when doing the compilation using Xilinx
CAD. This has the advantage that our design is more general and flexible.
The ! indicates an active low (the signal will be inverted). The <font face="Courier">istype
</font>is an optional attribute assignment for a pin such as 'com' to indicate
that the output is a combinational signal or 'reg' for a clocked signal
(registered with a flip flop). This attribute is only for output pins.
<p><b><font face="Courier">node</font></b>: node declarations have the
same format as the pin declaration. Nodes are internal signals which are
not connected to external pins.
</p><ul>Example:
<p>tmp1 <font face="Courier">node [istype</font> 'com'];
<br>
<br> </p></ul>
<b>other declarations</b> allows one to define constants, sets, macros
and expressions which can simplify the program. As an example a constant
declaration has the following format:
<ul>id [, id],... = expr [, expr].. ;
<p>Examples:
</p><p><font face="Courier">A = 21;</font>
</p><p><font face="Courier">C=2*7;</font>
</p><p><font face="Courier">ADDR = [1,0,11];</font>
</p><p><font face="Courier">LARGE = B & C;</font>
</p><p><font face="Courier">D = [D3, D2, D1, D0];</font>
</p><p><font face="Courier">D = [D3..D0];</font></p></ul>
The last two equations are equivalent. The use of ".." is handy to specify
a range. The last example makes use of vector notations. Any time you use
D in an equation, it will refer to the vector [D3, D2, D1. D0].
<h2>
4. <a name="Numbers"></a>Numbers</h2>
Numbers can be entered in four different bases: binary, octal, decimal
and hexadecimal. The default base is decimal. Use one of the following
symbols (upper or lower case allowed) to specify the base. When no symbol
is specified it is assumed to be in the <u>decimal</u> base. You can change
the default base with the Directive "Radix" as explained in the next section.
<br>
<table border="1">
<tbody><tr>
<td width="148"><b>BASE NAME</b></td>
<td width="148"><b>BASE</b></td>
<td width="148"><b>Symbol.</b></td>
</tr>
<tr>
<td width="148">Binary</td>
<td width="148">2</td>
<td width="148">^b </td>
</tr>
<tr>
<td width="148">Octal</td>
<td width="148">8</td>
<td width="148">^o </td>
</tr>
<tr>
<td width="148">Decimal</td>
<td width="148">10</td>
<td width="148">^d (default) </td>
</tr>
<tr>
<td width="148">Hexadecimal</td>
<td width="148">16</td>
<td width="148">^h </td>
</tr>
</tbody></table>
<p>Examples:
<br>
<table>
<tbody><tr>
<td width="140">
<ul><b>Specified in ABEL</b></ul>
</td>
<td width="140"><b>Decimal Value</b></td>
</tr>
<tr>
<td width="140">
<ul>35</ul>
</td>
<td width="140">
<ul>35</ul>
</td>
</tr>
<tr>
<td width="140">
<ul>^h35</ul>
</td>
<td width="140">
<ul>53</ul>
</td>
</tr>
<tr>
<td width="140">
<ul>^b101</ul>
</td>
<td width="140">
<ul>5</ul>
</td>
</tr>
</tbody></table>
</p><h2>
5. <a name="Directives"></a>Directives</h2>
Directives allow advanced manipulation of the source file and processing,
and can be placed anywhere needed in a file.
<p><b>@ALTERNATE</b>
<br><i>Syntax</i>
<br>@alternate
<br>
<br>@ALTERNATE enables an alternate set of operators. Using the <a href="#Logical">alternate
operator</a> set precludes use of the ABEL-HDL addition (+), multiplication
(*) and division (/) operators because they represent the OR, AND and NOT
logical operators in the alternate set. The standard operator still work
when @ALTERNATE is in effect. The alternate operators remain in effect
until the @STANDARD directive is used or the end of the module is reached.
</p><p><b>@RADIX</b>
<br><i>Syntax</i>
<br>@radix <i>expr</i> ;
<br><i>Expr: </i> A valid expression that produces the number 2, 8,
10 or 16 to indicate a new default base number.
</p><p>The @Radix directive changes the default base. The default is base 10
(decimal). The newly-specified default base stays in effect until another
@radix directive is issued or until the end of the module is reached. Note
that when a new @radix is issued, the specification of the new base must
be in the current base format
</p><p>Example
</p><blockquote>@radix 2;
“change default base to binary
<br>…
<br>@radix 1010; “change back from binary
to decimal</blockquote>
<p><br><b>@STANDARD</b>
<br><i>Syntax</i>
<br>@standard
</p><p>The @standard option resets the operators to the ABEL-HDL standard.
The alternate set is chosen with the @alternative directive.
<br>
<br>
</p><h2>
</h2>
<h2>
6. <a name="Sets"></a>Sets</h2>
A set is a collection of signals or constants used to reference a group
of signals by one name. A set is very handy to simplify logic expressions.
Any operation that is applied to a set is applied to each element.
<p>A set is a list of constants or signals separated by commas or the range
operator (..) put between square brackets (required).
</p><ul>Examples:</ul>
<table>
<tbody><tr>
<td width="140">
<ul><font face="Courier">[D0,D1,D2,D4,D5]</font></ul>
</td>
<td width="234"></td>
</tr>
<tr>
<td width="140">
<ul><font face="Courier">[D0..D6]</font></ul>
</td>
<td width="234">" incrementing range </td>
</tr>
<tr>
<td width="140">
<ul><font face="Courier">[b6..b0]</font></ul>
</td>
<td width="234">" decrementing range </td>
</tr>
<tr>
<td width="140">
<ul><font face="Courier">[D7..D15]</font></ul>
</td>
<td width="234"></td>
</tr>
<tr>
<td width="140">
<ul><font face="Courier">[b1,b2,a0..a3]</font></ul>
</td>
<td width="234">" range within a larger set</td>
</tr>
<tr>
<td width="140">
<ul><font face="Courier">[!S7..!S0]</font></ul>
</td>
<td width="234">"decrementing range of active -low signals</td>
</tr>
</tbody></table>
<p>However, the following is not allowed: <tt>[D0, X];</tt>
</p><ul>in which X is also a set <tt>X = [X3..X0]</tt>; Instead one can write:
<p><tt>[D0, X3..X0]</tt>;</p></ul>
<h3>
a. <a name="Indexing"></a>Indexing or accessing a set</h3>
Indexing allows you to access elements within a set. Use numerical values
to indicate the set index. The number refers to the bit position in the
set starting with 0 for the least significant bit of the set. Here are
some examples.
<ul><font face="Courier">D1 = [D15..D0]; "set declaration</font>
<p><font face="Courier">X2 = [X3..X0]; "set declaration</font>
</p><p><font face="Courier">X2 := D1[3..0]; "makes X2 equal to [D3, D2, D1,
D0]</font>
</p><p><font face="Courier">X2 := D1[7..4]; "makes X2 equal to [D7, D6, D5,
D4]</font></p></ul>
To access one element in the set, use the following syntax:
<ul><font face="Courier">OUT = (X[2] == 1);</font></ul>
Here a comparator operator (==) is used to convert the single-element (X[2])
into a bit value equivalent to X2. The comparator (==) gives a"1" or "0"
depending if the comparison is True or False. Notice the
<i>difference
between the assignment operator (=) and the equal operator (==)</i>. The
assignment operator is used in equations rather than in expressions. Equations
assign the value of an expression to the output signals.
<h3>
b. <a name="Set Operations"></a>Set operations</h3>
Most of the operations can be applied to a set and are performed on each
element of the set according to the rules of Boolean algebra. Operations
are performed according to the <a href="#priority">operator's priority</a>;
operators with the same priority are performed from left to right (unless
one uses parentheses). Here are a couple of examples.
<br>
<br>
<p>Example 1:
</p><ul><font face="Courier">Signal = [D2,D1,D0]; "declaration of Signal set</font>
<p><font face="Courier">Signal = [1,0,1] & [0,1,1];" results in Signal
being "equal to [0,0,1]</font></p></ul>
Example 2:
<ul><font face="Courier">[A,B] = C & D;</font></ul>
this is equivalent to two statements:
<ul><font face="Courier">A = C & D;</font>
<p><font face="Courier">B = C & D;</font></p></ul>
Example 3:
<ul><font face="Courier">[A1,B1] = [D1,D2] & [C3,C2];</font>
<p><font face="Courier">is equivalent to: [A1,B1] = [D1 & C3, D2 &
C2];</font>
</p><p><font face="Courier">thus A1 = D1 & C3, and B1= D2 & C2.</font></p></ul>
Example 4:
<ul><font face="Courier">X & [A,B,C];</font></ul>
which is equivalent to
<ul>[X&A, X&B, X&C];</ul>
However consider the following expression
<ul><font face="Courier">2 & [A,B,C];</font></ul>
now the number "2" is first converted into a binary representation and
padded with zeros (0010) if necessary. Thus the above equation is equivalent
to:
<ul><font face="Courier">[0 & A, 1 & B, 0 & C];</font></ul>
Example 5:
<ul><font face="Courier">A=[A2,A1,A0]; "set declaration</font>
<p><font face="Courier">B=[B2,B1,B0]; "set declaration</font>
</p><p><font face="Courier">A # B;</font> is equivalent to <font face="Courier">[A2
# B2, A1 # B1, A0 # B0];</font>
</p><p><font face="Courier">!A;</font> is equivalent to <font face="Courier">[!A2,!A1,!A0];</font></p></ul>
Example 6:
<ul><font face="Courier">[b3,b2,b1,b0] = 2;"is equivalent to b3=0,b2=0,b1=1,b0=0.</font></ul>
The number "2" is converted into binary and padded with zeros (0010).
<p>Example 7: Sets are also handy to specify logic equations. Suppose you
need to specify the equation:
</p><ul><font face="Courier">Chip_Sel = !A7 & A6 & A5;</font></ul>
This can be done using sets. First define a constant Addr set.:
<ul><font face="Courier">Addr = [A7,A6,A5];" declares a constant set Addr.</font></ul>
One can then use the following equation to specify the address:
<ul><font face="Courier">Chip_Sel = Addr == [0,1,1];</font></ul>
which is equivalent to saying:
<ul><font face="Courier">Chip_Sel = !A7 & A6 & A5;</font></ul>
Indeed, if A7=0, A6=1 and A5=1, the expression Addr ==[0,1,1] is true (or
1) and thus Chip_Sel will be true (or 1). Another way to write the same
equation is:
<ul><font face="Courier">Chip_Sel = Addr == 3; " decimal 3 is equal to
011.</font></ul>
The above expressions are very helpful when working with a large number
of variables (ex. a 16 bit address).
<p>Example 8:
</p><p>For the same constants as in the example above, the expression,
</p><ul><font face="Courier">3 & Addr;</font></ul>
which is equivalent to
<ul><font face="Courier">[0,1,1] & [A7,A6,A5]</font>
<p><font face="Courier">[0 & A7, 1 & A6, 1 & A5]</font>
</p><p><font face="Courier">[0,A6,A5].</font></p></ul>
However, the following statement is different:
<ul><font face="Courier">3 & (Addr == 1);</font></ul>
which is equivalent to:
<ul><font face="Courier">3 & (!A7 & !A6 & A5).</font></ul>
However, the relational operator (==) gives <u>only one bit</u>, so that
the rest of the equation evaluates also to one bit, and the "3" is truncated
to "1":. Thus the above equation is equal to:
<ul><font face="Courier">1& !A7 & !A6 & A5.</font></ul>
<h2>
7. <a name="Operators"></a>Operators</h2>
There are four basic types of operators: logical, arithmetic, relational
and assignment..
<h3>
a. <a name="Logical"></a>Logical Operators</h3>
The table below gives the logical operators. They are performed bit by
bit. With the <a href="#Directives">@ALTERNATIVE directive</a>, one can
use the alternative set of operators as indicated in the table.
<br>
<table border="1">
<tbody><tr>
<td width="148"><b>Operator (default)</b></td>
<td width="148"><b>Description </b></td>
<td width="148"><b>Alternate operator</b></td>
</tr>
<tr>
<td width="148">!</td>
<td width="148">NOT (ones complement)</td>
<td width="148">/</td>
</tr>
<tr>
<td width="148">&</td>
<td width="148">AND</td>
<td width="148">* </td>
</tr>
<tr>
<td width="148">#</td>
<td width="148">OR</td>
<td width="148">+</td>
</tr>
<tr>
<td width="148">$</td>
<td width="148">XOR: exclusive or</td>
<td width="148">:+: </td>
</tr>
<tr>
<td width="148">!$</td>
<td width="148">XNOR: exclusive nor</td>
<td width="148">:*:</td>
</tr>
</tbody></table>
<h3>
b. <a name="Arithmetic"></a>Arithmetic operators</h3>
The table below gives the arithmetic operators. Note that the last four
operators are not allowed with sets. The minus sign can have different
meanings: used between two operands it indicates subtraction (or adding
the twos complement), while used with one operator it indicates the twos
complement.
<br>
<table border="1">
<tbody><tr>
<td width="118"><b>Operator</b></td>
<td width="121"><b>Example</b></td>
<td width="204"><b>Description</b></td>
</tr>
<tr>
<td width="118">-</td>
<td width="121">-D1</td>
<td width="204">Twos complement (negation) </td>
</tr>
<tr>
<td width="118">-</td>
<td width="121">C1-C2</td>
<td width="204">Subtraction </td>
</tr>
<tr>
<td width="118">+</td>
<td width="121">A+B</td>
<td width="204">Addition </td>
</tr>
<tr>
<td colspan="3" width="443">
<center><b><i>The following operators are not used with sets: </i></b></center>
</td>
</tr>
<tr>
<td width="118">*</td>
<td width="121">A*B</td>
<td width="204">Multiplication </td>
</tr>
<tr>
<td width="118">/</td>
<td width="121">A/B</td>
<td width="204">Unsigned integer division </td>
</tr>
<tr>
<td width="118">%</td>
<td width="121">A%B</td>
<td width="204">Modulus: remainder of A/B </td>
</tr>
<tr>
<td width="118"><<</td>
<td width="121">A<<B</td>
<td width="204">Shift A left by B bits </td>
</tr>
<tr>
<td width="118">>></td>
<td width="121">A>>B</td>
<td width="204">Shift B right by B bits </td>
</tr>
</tbody></table>
<h3>
c. <a name="Relational"></a>Relational operators</h3>
These operators produce a Boolean value of <u>True (-1) or False (0).</u>
The logical true value of -1 in twos complement is represented by all ones
(i.e.<i>all bits will be ones</i>: ex. for a 16 bit word all bits are one:
-1 is represented by 1111 1111 1111 1111).
<br>
<table border="1">
<tbody><tr>
<td width="148"><b>Operator </b></td>
<td width="148"><b>Example</b></td>
<td width="148"><b>Description </b></td>
</tr>
<tr>
<td width="148">==</td>
<td width="148">A==B or 3==5 (false)</td>
<td width="148">Equal</td>
</tr>
<tr>
<td width="148">!=</td>
<td width="148">A!=B or 3 != 5 (true) </td>
<td width="148">Not equal</td>
</tr>
<tr>
<td width="148"><</td>
<td width="148">A<B or 3 < 5 (true) </td>
<td width="148">Less than</td>
</tr>
<tr>
<td width="148"><=</td>
<td width="148">A<=B or 3 <= 5 (true) </td>
<td width="148">Less than or equal</td>
</tr>
<tr>
<td width="148">></td>
<td width="148">A>B or -1 > 5 (true) </td>
<td width="148">Greater than</td>
</tr>
<tr>
<td width="148">>=</td>
<td width="148">A>=B or !0 >= 5 (true) </td>
<td width="148">Greater than or equal</td>
</tr>
</tbody></table>
<br>
<p><i><font color="#914a19">Relational operators are unsigned</font></i>.
Be careful: !0 is the one complement of 0 or 11111111 (8 bits data) which
is 255 in unsigned binary. Thus !0 > 9 is true. The expression -1>5 is
true for the same reason.
</p><p>A relational expression can be used whenever a number can be used. The
-1 or 0 will be substituted depending on the logical result. As an example
:
</p><ul>A = B !$ (C == D);</ul>
A will be equal to B if C is equal to D (true or 11111...; B XNOR 1 equals
B), otherwise, A will be equal to the complement of B (if C is not equal
to B (false or 0)).
<h3>
d. <a name="Assignment"></a>Assignment operators</h3>
These operators are used in equations to assign the value of an expression
to output signals. There are two types of assignment operators: combinational
and registered. In a combinational operator the assignment occurs immediately
without any delay. The registered assignment occurs at the next clock pulse
associated with the output. As an example, one can define a flip-flop with
the following statements:
<ul><font face="Courier">Q1 pin istype 'reg';</font>
<p><font face="Courier">Q1 := D;</font></p></ul>
The first statement defines the Q1 flip-flop by using the 'reg' as istype
(registered output). The second statement tells that the output of the
flip-flop will take the value of the D input at the next clock transition.
<br>
<table border="1">
<tbody><tr>
<td width="221"><b>Operator</b></td>
<td width="221"><b>Description</b></td>
</tr>
<tr>
<td width="221">=</td>
<td width="221">Combinational assignment </td>
</tr>
<tr>
<td width="221">:=</td>
<td width="221">Registered assignment</td>
</tr>
</tbody></table>
<h3>
e. Operator <a name="priority"></a>priority</h3>
The priority of each operator is given in the following table, with priority
1 the highest and 4 the lowest. Operators with the same priority are performed
from left to right.
<br>
<table border="1">
<tbody><tr>
<td width="148"><b>Priority</b></td>
<td width="148"><b>Operator</b></td>
<td width="148"><b>Description </b></td>
</tr>
<tr>
<td width="148">1</td>
<td width="148">-</td>
<td width="148">Negation (twos complement) </td>
</tr>
<tr>
<td width="148">1</td>
<td width="148">!</td>
<td width="148">NOT </td>
</tr>
<tr>
<td width="148">2</td>
<td width="148">&</td>
<td width="148">AND </td>
</tr>
<tr>
<td width="148">2</td>
<td width="148"><<</td>
<td width="148">shift left </td>
</tr>
<tr>
<td width="148">2</td>
<td width="148">>></td>
<td width="148">shift right </td>
</tr>
<tr>
<td width="148">2</td>
<td width="148">*</td>
<td width="148">multiply </td>
</tr>
<tr>
<td width="148">2</td>
<td width="148">/</td>
<td width="148">unsigned division </td>
</tr>
<tr>
<td width="148">2</td>
<td width="148">%</td>
<td width="148">modulus </td>
</tr>
<tr>
<td width="148">3</td>
<td width="148">+</td>
<td width="148">add </td>
</tr>
<tr>
<td width="148">3</td>
<td width="148">-</td>
<td width="148">subtract </td>
</tr>
<tr>
<td width="148">3</td>
<td width="148">#</td>
<td width="148">OR</td>
</tr>
<tr>
<td width="148">3</td>
<td width="148">$</td>
<td width="148">XOR </td>
</tr>
<tr>
<td width="148">3</td>
<td width="148">!$</td>
<td width="148">XNOR </td>
</tr>
<tr>
<td width="148">4</td>
<td width="148">==</td>
<td width="148">equal </td>
</tr>
<tr>
<td width="148">4</td>
<td width="148">!=</td>
<td width="148">not equal </td>
</tr>
<tr>
<td width="148">4</td>
<td width="148"><</td>
<td width="148">less then </td>
</tr>
<tr>
<td width="148">4</td>
<td width="148"><=</td>
<td width="148">less then or equal </td>
</tr>
<tr>
<td width="148">4</td>
<td width="148">></td>
<td width="148">greater than </td>
</tr>
<tr>
<td width="148">4</td>
<td width="148">>=</td>
<td width="148">greater than or equal </td>
</tr>
</tbody></table>
<h2>
8. <a name="Logic"></a>Logic description</h2>
A logic design can be described in the following way.
<ul>
<li>
Equations</li>
<li>
Truth Table</li>
<li>
State Description</li>
</ul>
<h3>
a. <a name="Equations"></a>Equations</h3>
Use the keyword <b><font face="Courier">equations</font></b> to begin the
logic descriptions. Equations specify logic expressions using the <a href="#Operators">operators</a>
described above, or "When-Then-Else" statement.
<p>The <a name=""When-Then-Else""></a>"When-Then-Else" statement
is used in equations to describe a logic function. (Note: "<a href="#If-Else-Then">If
-Then-Else</a>" is used in the State-diagram section to describe state
progression).
</p><p>The format of the "When-Then-Else" statement is as follows:
</p><ul><font face="Courier">WHEN condition THEN element=expression;</font>
<p><font face="Courier">ELSE equation;</font>
</p><p><font face="Courier">or</font>
</p><p><font face="Courier">WHEN condition THEN equation;</font></p></ul>
Examples of equations:
<ul><font face="Courier">SUM = (A & !B) # (!A & B) ;</font>
<br><font face="Courier">A0 := EN & !D1 & D3 & !D7;</font>
<p><font face="Courier">WHEN (A == B) THEN D1_out = A1;</font>
</p><ul>
<br><font face="Courier">ELSE WHEN (A == C) THEN D1_out = A0;</font></ul>
<font face="Courier">WHEN (A>B) THEN { X1 :=D1; X2 :=D2; }</font></ul>
One can use the braces { } to group sections together in blocks. The text
in a block can be on one line or span many lines. Blocks are used in equations,
state diagrams and directives.
<h3>
b. <a name="Truth"></a>Truth Tables</h3>
The keyword <b>is <font face="Courier">truth-table </font></b>and the syntax
is
<ul><font face="Courier">TRUTH_TABLE ( in_ids -> out_ids )</font>
<p><font face="Courier">inputs -> outputs ;</font></p></ul>
or
<ul><font face="Courier">TRUTH_TABLE ( in_ids :> reg_ids )</font>
<p><font face="Courier">inputs :> reg_outs ;</font></p></ul>
or
<ul><font face="Courier">TRUTH_TABLE</font>
<p><font face="Courier">( in_ids :> reg_ids -> out_ids )</font>
</p><p><font face="Courier">inputs :> reg_outs -> outputs ;</font>
<br> </p></ul>
in which "->" is for combinational output and ":>" for registered output.
The first line of a truth table (between parentheses) defines the inputs
and the output signals. The following lines gives the values of the inputs
and outputs. Each line must end with a semicolon. The inputs and outputs
can be single signals or sets. When sets are used as inputs or outputs,
use the normal set notation, i.e. signals surrounded by square brackets
and separated by commans. A don't care is represented by a ".X.".
<p>Example 1: half adder
</p><ul><tt><font face="Courier">TRUTH_TABLE ( [ A, B] -> [Sum, Carry_out]
)</font></tt>
<ul>
<ul><tt><font face="Courier">[ 0, 0 ] -> [0, 0 ] ;</font></tt>
<br><tt><font face="Courier">[ 0, 1 ] -> [1, 0 ] ;</font></tt>
<br><tt><font face="Courier">[ 1, 0 ] -> [1, 0 ] ;</font></tt>
<br><tt><font face="Courier">[ 1, 1 ] -> [1, 1 ] ;</font></tt></ul>
</ul>
</ul>
However, if one defines a set IN = [A,B]; and OUT = [Sum, Carry_out]; the
truth table becomes simpler:
<ul><tt><font face="Courier">TRUTH_TABLE (IN -> OUT )</font></tt>
<ul>
<ul><tt><font face="Courier">0 -> 0;</font></tt>
<br><tt><font face="Courier">1 -> 2;</font></tt>
<br><tt><font face="Courier">2 -> 2;</font></tt>
<br><tt><font face="Courier">3 -> 3;</font></tt></ul>
</ul>
</ul>
Example 2: An excluse OR with two intputs and one enable (EN). This example
illustrates the use of don't cares (.X.)
<ul><tt><font face="Courier">TRUTH_TABLE ([EN, A, B] -> OUT )</font></tt>
<ul>
<ul><tt><font face="Courier">[ 0, .X.,.X.] -> .X. ;</font></tt>
<br><tt><font face="Courier">[ 1, 0 , 0 ] -> 0 ;</font></tt>
<br><tt><font face="Courier">[ 1, 0 , 1 ] -> 1 ;</font></tt>
<br><tt><font face="Courier">[ 1, 1 , 0 ] -> 1 ;</font></tt>
<br><tt><font face="Courier">[ 1, 1 , 1 ] -> 0 ;</font></tt></ul>
</ul>
</ul>
Example 3: (see Example in R. Katz, section 7.2.1 and table 7.14)
<p>Truth tables can also be used to define sequential machines. Lets implement
a three-bit up counter which counts from 000, 001, to 111 and back to 000.
Lets call QA, QB and QC the outputs of the flip-flops. In addition, we
will generate an output OUT whenever the counter reaches the state 111.
We will also reset the counter to the state 000 when the reset signal is
high.
</p><ul><tt><font face="Courier">MODULE CNT3;</font></tt>
<p><tt><font face="Courier">CLOCK pin;</font> <font face="Courier">" input
signal</font></tt>
<br><tt><font face="Courier">RESET . pin;</font> <font face="Courier">"
input signal</font></tt>
<br><tt><font face="Courier">OUT pin istype 'com';</font> <font face="Courier">"
output signal (combinational)</font></tt>
<br><tt><font face="Courier">QC,QB,QA pin istype 'reg'; " output signal
(registered)</font></tt>
</p><p><tt><font face="Courier">[QC,QB,QA].CLK = CLOCK; "FF clocked on the
CLOCK input</font></tt>
<br><tt><font face="Courier">[QC,QB,QA].AR = RESET; "asynchronous reset
by RESET</font></tt>
</p><p><tt><font face="Courier">TRUTH_TABLE ) [QC, QB, QA] :> [QC,QB,QA] ->
OUT)</font></tt>
</p><ul>
<ul>
<ul><tt><font face="Courier">[ 0 0 0 ] :> [ 0 0 1 ] -> 0;</font></tt>
<br><tt><font face="Courier">[ 0 0 1 ] :> [ 0 1 0 ] -> 0;</font></tt>
<br><tt><font face="Courier">[ 0 1 0 ] :> [ 0 1 1 ] -> 0;</font></tt>
<br><tt><font face="Courier">[ 0 1 1 ] :> [ 1 0 0 ] -> 0;</font></tt>
<br><tt><font face="Courier">[ 1 0 0 ] :> [ 1 0 1 ] -> 0;</font></tt>
<br><tt><font face="Courier">[ 1 0 1 ] :> [ 1 1 0 ] -> 0;</font></tt>
<br><tt><font face="Courier">[ 1 1 0 ] :> [ 1 1 1 ] -> 0;</font></tt>
<br><tt><font face="Courier">[ 1 1 1 ] :> [ 0 0 0 ] -> 1;</font></tt></ul>
</ul>
</ul>
<tt><font face="Courier">END CNT3;</font></tt></ul>
For the use of .DOT extensions (.CLK and .AR) see section 7d.
<h3>
c. <a name="State"></a>State Description</h3>
The State_diagram section contains the state description for the logic
design. This section uses the State_diagram syntax and the "If-Then-Else",
"Goto", "Case" and "With" statements. Usually one declares symbolic state
names in the Declaration section, which makes reading the program often
easier.
<p><i>State declaration</i> (in the declaration section) syntax:
</p><ul><font face="Courier">state_id [, state_id ...] STATE ;</font></ul>
As an example: <tt><font size="+1">SREG = [Q1, Q2];</font></tt> associates
the state name SREG with the state defined by Q1 and Q2.
<p><u>The <b>syntax </b>for <i>State_diagram</i> is as follows:</u>
</p><ul><font face="Courier">State_diagram <i>state_reg</i></font>
<p><font face="Courier">STATE <i>state_value</i> : [equation;]</font>
</p><p><font face="Courier">[equation;]</font>
</p><p><font face="Courier">:</font>
</p><p><font face="Courier">:</font>
</p><p><font face="Courier">trans_stmt ; ...</font></p></ul>
The keyword <b><font face="Courier">state_diagram </font></b>indicates
the beginning of a state machine description.
<p>The STATE keyword and following statements describe one state of the
state diagram and includes a state value or symbolic state name, state
transition statement and an optional output equation. In the above syntax,
</p><ul>
<li>
<font face="Courier">state_reg</font>: is an identifier that defines the
signals that determine the state of the machine. This can be a symbolic
state register that has been declared earlier in the declaration section.</li>
<li>
<font face="Courier">state_value</font>: can be an expression, a value
or a symbolic state name of the current state;</li>
<li>
<font face="Courier">equation</font> : an equation that defines the state
machine outputs</li>
<li>
<font face="Courier">trans_stmt</font>: the "If-Then-Else", CASE or GOTO
statements to defines the next state, followed with optional WITH transition
equations.</li>
</ul>
<a name="If-Else-Then"></a><u><b><font face="Courier">If-Then-Else</font></b>
statement:</u>
<p>This statement is used in the state_diagram section to describe the
next state and to specify mutually exclusive transition conditions.
</p><p>Syntax<font face="Courier">:</font>
</p><ul><font face="Courier">IF expression THEN state_exp</font>
<p><font face="Courier">[ELSE state_exp] ;</font></p></ul>
In which state-exp can be a logic expression or a symbolic state name.
Note that the "IF-Then-Else" statement can only be used in the state_diagram
section (use the <a href="#%22When-Then-Else%22">"When-If-Then"</a>
to describe logic functions". The ELSE clause is optional. The IF-Then-Else
statements can be nexted with <tt><font size="+1">Goto, Case</font></tt>
and <tt><font size="+1">With</font></tt> statements.
<p>Example (after R. Katz):
</p><p>in the declaration section we define first the state registers:
</p><ul><font face="Courier">SREG = [Q1, Q0];</font> "definition of state registers
<br><font face="Courier">S0 = [0, 0];</font>
<br><font face="Courier">S1 = [1, 1];</font>
<p><font face="Courier">state_diagram SREG</font>
<br><font face="Courier">state S0:</font> OUT1 = 1;
</p><ul>
<br><font face="Courier">if A then S1</font>
<br><font face="Courier">else S0;</font></ul>
<font face="Courier">state S1: OUT2 =1;</font>
<ul>
<br><font face="Courier">if A then S0</font>
<br><font face="Courier">else S1;</font></ul>
</ul>
"If-Then-Else" statements can be nested as in the following example (after
Wakerly). We assume that one has defined the registers and states in the
declaration section.
<ul><font face="Courier">state_diagram MAK</font>
<p><font face="Courier">state INIT: if RESET then INIT else LOOK;</font>
</p><p><font face="Courier">state LOOK: if REST than INIT</font>
</p><ul><font face="Courier">else if (X == LASTX) then OK</font>
<br><font face="Courier">else LOOK;</font></ul>
<font face="Courier">state OK: if RESET than INIT</font>
<ul><font face="Courier">else if Y then OK</font>
<br><font face="Courier">else if (X == LASTX) then OK</font>
<br><font face="Courier">else LOOK;</font></ul>
<font face="Courier">state OK: goto INIT;</font>
<br> </ul>
<u>"<a name="with"></a><b><font face="Courier">with</font></b>" statement:</u>
<p>Syntax:
</p><ul><font face="Courier">trans_stmt state_exp WITH equation</font>
<br><font face="Courier">[equation ] ... ;</font></ul>
in which trans_stmt can be "If-then-else", 'Goto" or a "Case" statement.
<br><tt>state_exp</tt>: is the next state, and <tt>equation</tt> is an
equation for the machine outputs.
<p>This statement can be used with the "If-Then-Else", "Goto" or "Case"
statements in place of a simple state expression. The "With" statement
allows the output equations to be written in terms of transitions.
</p><p>Example 1:
</p><ul><tt><font size="+1">if X#Y==1 then S1 with Z=1 else S2;</font></tt></ul>
In the above example, the output Z will be asserted as soon as the expression
after the if statement evaluates to a logic 1 (or TRUE). The expression
after the "With" keyword can be an equation that will be evaluated as soon
as the if condition is true as in example 2:
<p>Example 2:
</p><ul><tt><font size="+1">if X&!Y then S3 with Z=X#Y else S2 with Z=Y;</font></tt></ul>
The "With" statement is also useful to describe output behavior of registered
outputs, since registered outputs would lag by one clock cycle. It allows
one also for instance to specify that a registered output should have a
specific value after a particular transition. As an example [1],
<p>Example 3[1]:
</p><p><font face="Courier">state S1:</font>
</p><ul><font face="Courier">if RST then S2 with { OUT1 := 1;</font>
<ul><font face="Courier">Error-Adrs := ADDRESS; }</font></ul>
<font face="Courier">else if (ADDRESS <= ^hC101)</font>
<ul><font face="Courier">then S4</font>
<br><font face="Courier">else S1;</font></ul>
</ul>
Notice that one can use curly braces to control a group of outputs and
equations after the With keyword as in the example above.
<p>Example 3:
</p><ul><font face="Courier">state S1: if (A & B) then S2 with TK = 1</font>
<ul><font face="Courier">else S0 with TK = 0 ;</font></ul>
</ul>
You have to be aware of the timing when using the "With " statement with
combinational or asynchronous outputs (as in a Mealy machine). A Mealy
machine changes its outputs as soon as the input changes. This may cause
the output to change too quickly resulting in glitches. The outputs of
a Mealy machine will be valid at the end of a state time (i.e. just before
the clock transition). In this respect a Moore output (with synhronous
outputs) is less prone to timing errors. An example of a <a href="http://www.ese.upenn.edu/rca/software/abel/abel.ex1.html">Mealy
machine</a> and a <a href="http://www.ese.upenn.edu/rca/software/abel/abel.ex2.html">Moore machine</a> is available.
<p><a name="Case"></a><b><u><font face="Courier">Case</font> </u></b><u>statement</u>
</p><p>Syntax:
</p><ul><font face="Courier">CASE expression : state_exp;</font>
<p><font face="Courier">[ expression : state_exp; ]</font>
<br><font face="Courier">:</font>
</p><p><font face="Courier">ENDCASE ;</font></p></ul>
expression is any valid ABEL expression and state_exp is an expression
that indicates the next state (optionally followed by WITH statement).
<p>Example:
</p><ul><font face="Courier">State S0:</font>
<ul><font face="Courier">case ( A == 0) : S1;</font>
<ul><font face="Courier">( A == 1) : S0;</font></ul>
</ul>
<font face="Courier">endcase;</font></ul>
The case statement is used to list a sequence of mutually-exclusive transition
conditions and corresponding next states. The CASE statement conditions
must be mutually exclusive (no two transition conditions can be true at
the same time) or the resulting next state is unpredictable.
<h3>
d. Dot <a name="extensions"></a>extensions</h3>
One can use dot extensions to more precisely describe the behavior of the
circuit. The signal extensions are very handy and provide a means to refer
specifically to internal signals and nodes associated with a primary signal.
<p>The syntax is
</p><ul><font face="Courier">signal_name.ext</font></ul>
Some of the dot extensions are given in the following table. Extensions
are not case sensitive. Some dot extensions are general purpose (also called
architecture independent or pin-to-pin) and can used with a variety of
device architectures. Other dot extensions are used for specific classes
of device architectures and are called architecture-dependent or detailed
dot extensions. In general, you can use either dot extensions.
<br>
<center><table border="1">
<tbody><tr>
<td width="109"><b>Dot extension</b></td>
<td width="270"><b>Description</b></td>
</tr>
<tr>
<td colspan="2" width="379"><b>Architecture independent or pin-to-pin extensions</b></td>
</tr>
<tr>
<td width="109">.ACLR</td>
<td width="270">Asynchronous register reset </td>
</tr>
<tr>
<td width="109">.ASET</td>
<td width="270">Asynchronous register preset </td>
</tr>
<tr>
<td width="109">.CLK</td>
<td width="270">Clock input to an edge-triggered flip-flop </td>
</tr>
<tr>
<td width="109">.CLR</td>
<td width="270">Synchronous register reset </td>
</tr>
<tr>
<td width="109">.COM</td>
<td width="270">Cominbational feedback from flip-flop data input </td>
</tr>
<tr>
<td width="109">.FG</td>
<td width="270">Register feedback</td>
</tr>
<tr>
<td width="109">.OE</td>
<td width="270">Output enable</td>
</tr>
<tr>
<td width="109">.PIN</td>
<td width="270">Pin feedback</td>
</tr>
<tr>
<td width="109">.SET</td>
<td width="270">Synchronous register preset </td>
</tr>
<tr>
<td colspan="2" width="379"><b>Device Specific extensions (architecture
dependent)</b></td>
</tr>
<tr>
<td width="109">.D</td>
<td width="270">Data input to a D Flip flop </td>
</tr>
<tr>
<td width="109">.J</td>
<td width="270">J input to a JK flip-flop </td>
</tr>
<tr>
<td width="109">.K</td>
<td width="270">K input to a JK flip-flop </td>
</tr>
<tr>
<td width="109">.S</td>
<td width="270">S input to a SR flip-flop </td>
</tr>
<tr>
<td width="109">.R</td>
<td width="270">R input to a SR flip-flop </td>
</tr>
<tr>
<td width="109">.T</td>
<td width="270">T input to a T flip-flop </td>
</tr>
<tr>
<td width="109">.Q</td>
<td width="270">Register feedback</td>
</tr>
<tr>
<td width="109">.PR</td>
<td width="270">Register preset</td>
</tr>
<tr>
<td width="109">.RE</td>
<td width="270">Register reset</td>
</tr>
<tr>
<td width="109">.AP</td>
<td width="270">Asynchronous register preset </td>
</tr>
<tr>
<td width="109">.AR</td>
<td width="270">Asynchronous register reset </td>
</tr>
<tr>
<td width="109">.SP</td>
<td width="270">Synchronous register preset </td>
</tr>
<tr>
<td width="109">.SR</td>
<td width="270">Synchronous register reset </td>
</tr>
</tbody></table></center>
<p>The figure below illustrates some of the extensions.
</p><p><br>
<br>
<br>
</p><center>
<p><img src="abel.primer-Dateien/abel.gif" height="226" width="621">
</p><p>Figure 1: Illustration of DOT extensions for: (a) an architecture independent
(pin-to-pin) and (b) arhitecture dependent D-type (or T-type) Flip Flop
Architecture</p></center>
<p>Example 1:
</p><ul><font face="Courier">[S6..S0].OE = ACTIVE;</font></ul>
which accesses the tri state control signal of the output buffers of the
signals S6..S0. When ACTIVE is high, the signals will be enabled, otherwise
a high Z output is generated.
<p>Example 2:
</p><ul><font face="Courier">Q.AR = reset;</font>
<p><font face="Courier">[Z.ar, Q.ar] = reset;</font></p></ul>
which resets to output of the registers (flip flops) to zero when reset
is high.
<h2>
9. Test <a name="vectors"></a>vectors</h2>
Test vectors are optional and provide a means to verify the correct operation
of a state machine. The vectors specify the expected logical operation
of a logic device by explicitly giving the outputs as a function of the
inputs.
<p>Syntax:
</p><ul>
<br><font face="Courier">Test_vectors [note]</font>
<p><font face="Courier">(input [, input ].. -> output [, output ] .. )</font>
</p><p><font face="Courier">[invalues -> outvalues ; ]</font>
<br><font face="Courier">:</font>
<br><font face="Courier">:</font></p></ul>
Example:
<ul><font face="Courier">Test_vectors</font>
<p><font face="Courier">( [A, B] -> [Sum, Carry] )</font>
</p><p><font face="Courier">[ 0, 0 ] -> [0, 0];</font>
<br><font face="Courier">[ 0, 1 ] -> [1, 0];</font>
<br><font face="Courier">[ 1, 0 ] -> [1, 0];</font>
<br><font face="Courier">[ 1, 1 ] -> [1, 1];</font></p></ul>
One can also specify the values for the set with numeric constants as shown
below.
<ul><font face="Courier">Test_vectors</font>
<p><font face="Courier">( [A, B] -> [Sum, Carry] )</font>
</p><ul><font face="Courier">0 -> 0;</font>
<br><font face="Courier">1 -> 2;</font>
<br><font face="Courier">2 -> 2;</font>
<br><font face="Courier">3 -> 3;</font></ul>
</ul>
Don't cares (.X.), clock inputs (.C.) as well as symbolic constants are
allowed, as shown in the following example.
<br>
<br>
<ul><font face="Courier">test_vectors</font>
<p><font face="Courier">( [CLK, RESET, A, B ] -> [ Y0, Y1, Y3] )</font>
</p><ul><font face="Courier">[.X., 1, .X.,.X.]->[ S0, 0, 0];</font>
<br><font face="Courier">[.C., 0, 0, 1 ] -> [ S0, 0, 0];</font>
<br><font face="Courier">[.C., 1, 1, 0 ] -> [ S0, 0, 1];</font></ul>
</ul>
<h2>
10. <a name="Property"></a>Property Statements</h2>
ABEL allows to give device specific statements using the property statement.
This statement will be passed to the "Fitter" program during compilation.
For the CPLD devices these properties include
<ul>
<li>
Slew rates</li>
<li>
Logic optimizations</li>
<li>
Logic placement</li>
<li>
Power settings</li>
<li>
Preload values</li>
</ul>
<h2>
11. <a name="Miscellaneous"></a>Miscellaneous</h2>
<h3>
a. <a name="Active-low"></a>Active-low declarations</h3>
Active low signals are defined with a "!" operator, as shown below,
<ul><font face="Courier">!OUT pin istype 'com' ;</font></ul>
When this signal is used in a subsequent design description, it will be
automatically complemented. As an example consider the following description,
<ul><font face="Courier">module EXAMPLE</font>
<p><font face="Courier">A, B pin ;</font>
</p><p><font face="Courier">!OUT pin istype 'com';</font>
</p><p><font face="Courier">equations</font>
</p><p><font face="Courier">OUT = A & !B # !A & B ;</font>
</p><p><font face="Courier">end</font></p></ul>
In this example, the signal OUT is an XOR of A and B, i.e. OUT will be
"1" (High, or ON) when only one of the inputs is "1", otherwise OUT is
"0". However, the output pin is defined as !OUT , i.e. as an active-low
signal, which means that the pin will go low "0" (Active-low or ON) when
only one of the two inputs are "1". One could have obtained the same result
by inverting the signal in the equations and declaring the pin to be OUT,
as is shown in the following example. This is called <i>explicit pin-to-pin
active-low</i> (because one uses active-low signals in the equations).
<ul><font face="Courier">module EXAMPLE</font>
<p><font face="Courier">A, B pin ;</font>
</p><p><font face="Courier">OUT pin istype 'com';</font>
</p><p><font face="Courier">equations</font>
</p><p><font face="Courier">!OUT = A & !B # !A & B ;</font>
</p><p><font face="Courier">end</font></p></ul>
Active low can be specified for a set as well. As an example lets define
the sets A,B and C.
<ul><font face="Courier">A = [A2,A1,A0]; "set declaration</font>
<br><font face="Courier">B = [B2,B1.B0]; "set declaration</font>
<br><font face="Courier">X = [X2,X1.X0]; "set declaration</font>
<p><font face="Courier">!X = A & !B # !A & B;</font></p></ul>
The last equation is equivalent to writing
<ul>!X0 = <font face="Courier">A0 & !B0 # !A0 & B0;</font>
<br>!X1 = <font face="Courier">A1 & !B1 # !A1 & B1;</font>
<br>!X2 = <font face="Courier">A2 & !B2 # !A2 & B2;</font></ul>
<h2>
<a name="References"></a>References</h2>
<ul>
<li>
1. Xilinx-ABEL Design Software Reference Manual, Data I/O Corp., 1993.</li>
<li>
2. The ISP Application Guide and CPLD Data Book, Application Note XAPP075,
1997, Xilinx, San Jose, CA, 1997.</li>
<li>
3. D. Van den Bout, "Xilinx FPGA Student Manual", Prentice Hall, Englewoods
Cliff, NJ, 1997.</li>
<li>
4. R. Katz, "Contemporary Logic Design," Benjamin/Cummings Publ. Comp.,
Redwood City, CA, 1995.</li>
<li>
5. J. Wakerly, "Digital Design," Prentice Hall, Englewoods Cliff, NJ, 1993.</li>
<li>
6. Xilinx Foundation Series, On-line documentation, Xilinx, San Jose, CA.</li>
</ul>
<h2>
<a name="Acknowledgement"></a>Acknowledgement</h2>
The support of Mr. Jason Feinsmith and the <b><i><font size="+1"><a href="http://www.xilinx.com/">Xilinx</a></font></i></b>Corporation
is acknowledged for providing the XILINX Foundation M1(TM) Software and
FPGA Demoboards for educational purposes.
<h2>
<hr size="4" width="100%"></h2>
<font size="-1">Back to ABEL Primer <a href="#Contents">Contents</a> | To
to <a href="http://www.ee.upenn.edu/rca/software/xilinx/foundation/commistakes.html">Common
Mistakes</a> list | Go to the <a href="http://www.ee.upenn.edu/rca">EE
Undergraduate Lab</a> Homepage | Go to <a href="http://www.ee.upenn.edu/rca/software/xilinx.html">Xilinx
Lab Tutorial</a> Homepage | Go to the <a href="http://www.ee.upenn.edu/rca/software/xilinx/foundation/foundation.sch1.html">Foundation
Tutorial</a> page | Go to <a href="http://www.seas.upenn.edu/%7Eee200/">EE200
</a>or
<a href="http://www.seas.upenn.edu/%7Eee200/lab/lab.html">EE200 Lab</a> Homepage
| .</font>
<hr width="100%">
<p>Created by <a href="http://www.ee.upenn.edu/%7Ejan">J. Van der Spiegel</a>,
<jan@ee.upenn.edu> Sept. 26, 1997; Updated August 13, 1999
</p></body></html>
|
