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| author | Sven Eisenhauer <sven@sven-eisenhauer.net> | 2023-11-10 15:11:48 +0100 |
|---|---|---|
| committer | Sven Eisenhauer <sven@sven-eisenhauer.net> | 2023-11-10 15:11:48 +0100 |
| commit | 33613a85afc4b1481367fbe92a17ee59c240250b (patch) | |
| tree | 670b842326116b376b505ec2263878912fca97e2 /Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON3.S | |
| download | Studium-master.tar.gz Studium-master.tar.bz2 | |
Diffstat (limited to 'Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON3.S')
| -rw-r--r-- | Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON3.S | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON3.S b/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON3.S new file mode 100644 index 0000000..425c1de --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/BASICASM/LOADCON3.S @@ -0,0 +1,14 @@ + AREA Example, CODE
+ ENTRY ; Mark first instruction
+Start
+ ADR r0, Start ; => SUB r0, PC, #offset to Start
+ ADR r1, DataArea ; => ADD r1, PC, #offset to DataArea
+ ; ADR r2, DataArea+4300 ; This would fail as the offset is
+ ; cannot be expressed by operand2
+ ; of an ADD
+ ADRL r3, DataArea+4300 ; => ADD r2, PC, #offset1
+ ; ADD r2, r2, #offset2
+ SWI 0x11 ; Terminate
+DataArea % 8000
+
+ END
|