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| author | Sven Eisenhauer <sven@sven-eisenhauer.net> | 2023-11-10 15:11:48 +0100 |
|---|---|---|
| committer | Sven Eisenhauer <sven@sven-eisenhauer.net> | 2023-11-10 15:11:48 +0100 |
| commit | 33613a85afc4b1481367fbe92a17ee59c240250b (patch) | |
| tree | 670b842326116b376b505ec2263878912fca97e2 /Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/UDIV10.S | |
| download | Studium-33613a85afc4b1481367fbe92a17ee59c240250b.tar.gz Studium-33613a85afc4b1481367fbe92a17ee59c240250b.tar.bz2 | |
Diffstat (limited to 'Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/UDIV10.S')
| -rw-r--r-- | Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/UDIV10.S | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/UDIV10.S b/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/UDIV10.S new file mode 100644 index 0000000..787bb0b --- /dev/null +++ b/Bachelor/Mikroprozessorsysteme2/ARM202U/EXAMPLES/EXPLASM/UDIV10.S @@ -0,0 +1,23 @@ +; generated by divc 1.01 (Advanced RISC Machines) [01 Jul 92]
+
+ AREA |div10$code|, CODE, READONLY
+
+ EXPORT udiv10
+
+udiv10
+; takes argument in a1
+; returns quotient in a1, remainder in a2
+; cycles could be saved if only divide or remainder is required
+ SUB a2, a1, #10
+ SUB a1, a1, a1, lsr #2
+ ADD a1, a1, a1, lsr #4
+ ADD a1, a1, a1, lsr #8
+ ADD a1, a1, a1, lsr #16
+ MOV a1, a1, lsr #3
+ ADD a3, a1, a1, asl #2
+ SUBS a2, a2, a3, asl #1
+ ADDPL a1, a1, #1
+ ADDMI a2, a2, #10
+ MOV pc, lr
+
+ END
|