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Diffstat (limited to 'Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b1.abl')
| -rw-r--r-- | Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b1.abl | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b1.abl b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b1.abl new file mode 100644 index 0000000..257cd94 --- /dev/null +++ b/Bachelor/Digitaltechnik 2/SS07/P6/abel_samples.zip_FILES/count4b1.abl @@ -0,0 +1,25 @@ +MODULE Counter_4_bit
+
+TITLE '0 ... 9, version with equations'
+
+DEClARATIONS
+ clk pin 15; " I/O 0, Eingang für den Takt
+ rst pin 16; " I/O 1, Eingang für das Reset Signal
+ ce pin 17; " I/O 2, Eingang für das Enable Signal
+ q3,q2,q1,q0 pin 29,30,31,32 istype 'reg'; " I/O 12, 13, 14, 15, Ausgang: Bits des Zählers, 15: 2^0
+ carry pin 44 istype 'reg'; // I/O 23, Ausgang für Carry
+
+" bus definition, vector, register
+ counter = [q3,q2,q1,q0];
+
+EQUATIONS
+ counter.clk = clk;
+ counter.ar = rst;
+ carry.clk = clk;
+ when (ce & (counter < 9)) then counter := counter + 1;
+ else when (ce & (counter >= 9)) then {counter := 0; carry := 1;}
+ else counter := counter;
+
+
+END
+
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