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MODULE Counter_4_bit
TITLE '0 ... 9, version with equations'
DEClARATIONS
clk pin 15; " I/O 0, Eingang f�r den Takt
rst pin 16; " I/O 1, Eingang f�r das Reset Signal
ce pin 17; " I/O 2, Eingang f�r das Enable Signal
q3,q2,q1,q0 pin 29,30,31,32 istype 'reg'; " I/O 12, 13, 14, 15, Ausgang: Bits des Z�hlers, 15: 2^0
carry pin 44 istype 'reg'; // I/O 23, Ausgang f�r Carry
" bus definition, vector, register
counter = [q3,q2,q1,q0];
EQUATIONS
counter.clk = clk;
counter.ar = rst;
carry.clk = clk;
when (ce & (counter < 9)) then counter := counter + 1;
else when (ce & (counter >= 9)) then {counter := 0; carry := 1;}
else counter := counter;
END
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