1 files changed, 64 insertions, 0 deletions
diff --git a/Bachelor/Mikroprozessorsysteme2/mi2/Termin2/init4.h b/Bachelor/Mikroprozessorsysteme2/mi2/Termin2/init4.h
new file mode 100644
index 0000000..89a81b2
--- /dev/null
+++ b/Bachelor/Mikroprozessorsysteme2/mi2/Termin2/init4.h
@@ -0,0 +1,64 @@
+#ifndef init4_h
+#define init4_h
+
+
+// fuer AUFGABE 4:
+#define            aic_IDCR          ((volatile unsigned int*) 0xFFFFF124)     
+//Interrupt Disable Command Register
+#define            aic_ICCR          ((volatile unsigned int*) 0xFFFFF128)     
+// Interrupt Clear Command Register
+#define            aic_SMR             ((volatile unsigned int*) 0xFFFFF038)   
+// Source Mode Register !!!nachfragen
+#define            aic_SVR             ((volatile unsigned int*) 0xFFFFF0B8)   
+// Source Vector Register
+#define            aic_EOICR         ((volatile unsigned int*) 0xFFFFF130)     
+// End of Interrupt Command Reg.
+#define            aic_IECR          ((volatile unsigned int*) 0xFFFFF120)     
+// Interrupt Enable Command Register
+
+#define            pmc_PCER         ((volatile unsigned int*) 0xFFFF4010)     
+// Peripheral Clock Enable Reg
+#define            pmc_PCSR         ((volatile unsigned int*) 0xFFFF4018)     
+// Peripheral Clock Status Reg, Reset: 0x0
+
+#define            pioB_PER         ((volatile unsigned int*) 0xFFFF0000)    
+// PIOB Port Enable Reg
+#define            pioB_OER         ((volatile unsigned int*) 0xFFFF0010)    
+// PIOB Output Enable Reg
+#define            pioB_SODR         ((volatile unsigned int*) 0xFFFF0030)    
+// PIOB Set Output Data Reg
+#define            pioB_CODR         ((volatile unsigned int*) 0xFFFF0034)    
+// PIOB Clear Output Data Reg
+#define            pioB_PDSR         ((volatile unsigned int*) 0xFFFF003C)    
+// PIOB PIN Data Status Reg
+
+
+#endif
+
+/*
+#define            aic_SMR             ((volatile unsigned int*) 0xFFFFF038)   
+  // Source Mode Register !!!nachfragen
+#define            aic_SVR             ((volatile unsigned int*) 0xFFFFF0B8)   
+  // Source Vector Register
+*/
+
+//in MAIN->
+//....
+//*aic_SMR = 0x1 //
+/*
+SRCTYPE: Interrupt Source Type
+Program the input to be positive- or negative-edge triggered or positive- or 
+negative-level sensitive.
+The active level or edge is not programmable for the internal sources.
+----> hier haben wir den "Level Sensitive: Low-Level Sensitive" 00
+PRIOR: Priority Level
+
+Program the priority level for all sources except source 0 (FIQ).
+The priority level can be between 0 (lowest) and 7 (highest).
+The priority level is not used for the FIQ in the SMR0.
+---> also haben wir die 1
+sprich-> 0x01 -> 0x1;
+*/
+
+//*aic_SVR  = (volatile unsigned int) &taste_irq_handler; //im späteren Verlauf der Praktika wird
+//hier eine Interrupt-Routine-FKT kommen, die das weitere Vorgehen veranlast und in "fast" allen SVRs hinein kommt
+\ No newline at end of file